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authorDario Nieuwenhuis <[email protected]>2024-02-26 00:00:17 +0100
committerDario Nieuwenhuis <[email protected]>2024-02-26 00:00:17 +0100
commit489d0be2a2971cfae7d6413b601bbd044d42e351 (patch)
treeb930aa13b1f43efedcf8bc19e85e94036dedc7d2 /examples/stm32wl/src/bin/rtc.rs
parent497515ed57b768332295ef58630231609fb959fc (diff)
stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.
Diffstat (limited to 'examples/stm32wl/src/bin/rtc.rs')
-rw-r--r--examples/stm32wl/src/bin/rtc.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/stm32wl/src/bin/rtc.rs b/examples/stm32wl/src/bin/rtc.rs
index 4738d5770..0c26426ef 100644
--- a/examples/stm32wl/src/bin/rtc.rs
+++ b/examples/stm32wl/src/bin/rtc.rs
@@ -21,7 +21,7 @@ async fn main(_spawner: Spawner) {
21 mode: HseMode::Bypass, 21 mode: HseMode::Bypass,
22 prescaler: HsePrescaler::DIV1, 22 prescaler: HsePrescaler::DIV1,
23 }); 23 });
24 config.rcc.mux = ClockSrc::PLL1_R; 24 config.rcc.sys = Sysclk::PLL1_R;
25 config.rcc.pll = Some(Pll { 25 config.rcc.pll = Some(Pll {
26 source: PllSource::HSE, 26 source: PllSource::HSE,
27 prediv: PllPreDiv::DIV2, 27 prediv: PllPreDiv::DIV2,