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authorDario Nieuwenhuis <[email protected]>2023-10-23 00:28:54 +0200
committerDario Nieuwenhuis <[email protected]>2023-10-23 00:31:36 +0200
commitb9e13cb5d1ca3e85a02b2a37b7ee14f73663b1bd (patch)
tree1ae33453bcee12a6aaf4cfdd8dc1795187c7cadc /examples/stm32wl
parent46ff2c82aa3193dd1378b142be284aa746045923 (diff)
stm32/rcc: merge wl into l4/l5.
Diffstat (limited to 'examples/stm32wl')
-rw-r--r--examples/stm32wl/src/bin/lora_lorawan.rs22
-rw-r--r--examples/stm32wl/src/bin/random.rs23
2 files changed, 36 insertions, 9 deletions
diff --git a/examples/stm32wl/src/bin/lora_lorawan.rs b/examples/stm32wl/src/bin/lora_lorawan.rs
index 8c789afbc..e26c274ad 100644
--- a/examples/stm32wl/src/bin/lora_lorawan.rs
+++ b/examples/stm32wl/src/bin/lora_lorawan.rs
@@ -12,7 +12,8 @@ use embassy_lora::LoraTimer;
12use embassy_stm32::gpio::{Level, Output, Pin, Speed}; 12use embassy_stm32::gpio::{Level, Output, Pin, Speed};
13use embassy_stm32::rng::{self, Rng}; 13use embassy_stm32::rng::{self, Rng};
14use embassy_stm32::spi::Spi; 14use embassy_stm32::spi::Spi;
15use embassy_stm32::{bind_interrupts, pac, peripherals}; 15use embassy_stm32::time::Hertz;
16use embassy_stm32::{bind_interrupts, peripherals};
16use embassy_time::Delay; 17use embassy_time::Delay;
17use lora_phy::mod_params::*; 18use lora_phy::mod_params::*;
18use lora_phy::sx1261_2::SX1261_2; 19use lora_phy::sx1261_2::SX1261_2;
@@ -33,11 +34,24 @@ bind_interrupts!(struct Irqs{
33#[embassy_executor::main] 34#[embassy_executor::main]
34async fn main(_spawner: Spawner) { 35async fn main(_spawner: Spawner) {
35 let mut config = embassy_stm32::Config::default(); 36 let mut config = embassy_stm32::Config::default();
36 config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE; 37 {
38 use embassy_stm32::rcc::*;
39 config.rcc.hse = Some(Hse {
40 freq: Hertz(32_000_000),
41 mode: HseMode::Bypass,
42 });
43 config.rcc.mux = ClockSrc::PLL1_R;
44 config.rcc.pll = Some(Pll {
45 source: PLLSource::HSE,
46 prediv: PllPreDiv::DIV2,
47 mul: PllMul::MUL6,
48 divp: None,
49 divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG
50 divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2)
51 });
52 }
37 let p = embassy_stm32::init(config); 53 let p = embassy_stm32::init(config);
38 54
39 pac::RCC.ccipr().modify(|w| w.set_rngsel(0b01));
40
41 let spi = Spi::new_subghz(p.SUBGHZSPI, p.DMA1_CH1, p.DMA1_CH2); 55 let spi = Spi::new_subghz(p.SUBGHZSPI, p.DMA1_CH1, p.DMA1_CH2);
42 56
43 // Set CTRL1 and CTRL3 for high-power transmission, while CTRL2 acts as an RF switch between tx and rx 57 // Set CTRL1 and CTRL3 for high-power transmission, while CTRL2 acts as an RF switch between tx and rx
diff --git a/examples/stm32wl/src/bin/random.rs b/examples/stm32wl/src/bin/random.rs
index 70676c704..2cf7ef9d0 100644
--- a/examples/stm32wl/src/bin/random.rs
+++ b/examples/stm32wl/src/bin/random.rs
@@ -4,9 +4,9 @@
4 4
5use defmt::*; 5use defmt::*;
6use embassy_executor::Spawner; 6use embassy_executor::Spawner;
7use embassy_stm32::rcc::{ClockSrc, MSIRange};
8use embassy_stm32::rng::{self, Rng}; 7use embassy_stm32::rng::{self, Rng};
9use embassy_stm32::{bind_interrupts, pac, peripherals}; 8use embassy_stm32::time::Hertz;
9use embassy_stm32::{bind_interrupts, peripherals};
10use {defmt_rtt as _, panic_probe as _}; 10use {defmt_rtt as _, panic_probe as _};
11 11
12bind_interrupts!(struct Irqs{ 12bind_interrupts!(struct Irqs{
@@ -16,11 +16,24 @@ bind_interrupts!(struct Irqs{
16#[embassy_executor::main] 16#[embassy_executor::main]
17async fn main(_spawner: Spawner) { 17async fn main(_spawner: Spawner) {
18 let mut config = embassy_stm32::Config::default(); 18 let mut config = embassy_stm32::Config::default();
19 config.rcc.mux = ClockSrc::MSI(MSIRange::RANGE32M); 19 {
20 use embassy_stm32::rcc::*;
21 config.rcc.hse = Some(Hse {
22 freq: Hertz(32_000_000),
23 mode: HseMode::Bypass,
24 });
25 config.rcc.mux = ClockSrc::PLL1_R;
26 config.rcc.pll = Some(Pll {
27 source: PLLSource::HSE,
28 prediv: PllPreDiv::DIV2,
29 mul: PllMul::MUL6,
30 divp: None,
31 divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG
32 divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2)
33 });
34 }
20 let p = embassy_stm32::init(config); 35 let p = embassy_stm32::init(config);
21 36
22 pac::RCC.ccipr().modify(|w| w.set_rngsel(0b11)); // msi
23
24 info!("Hello World!"); 37 info!("Hello World!");
25 38
26 let mut rng = Rng::new(p.RNG, Irqs); 39 let mut rng = Rng::new(p.RNG, Irqs);