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authorxoviat <[email protected]>2023-06-19 16:05:59 -0500
committerxoviat <[email protected]>2023-06-19 16:05:59 -0500
commit09982214788def209316ef70cae08eead964e206 (patch)
tree3e6bdceafe1868d0a86e09f66a966362907f6256 /examples
parentaaad9068156305e5f6f41ee4013e025083bd0668 (diff)
stm32/can: update interrupts
Diffstat (limited to 'examples')
-rw-r--r--examples/stm32f4/src/bin/can.rs13
1 files changed, 11 insertions, 2 deletions
diff --git a/examples/stm32f4/src/bin/can.rs b/examples/stm32f4/src/bin/can.rs
index e8377b9a1..da8955053 100644
--- a/examples/stm32f4/src/bin/can.rs
+++ b/examples/stm32f4/src/bin/can.rs
@@ -4,12 +4,21 @@
4 4
5use cortex_m_rt::entry; 5use cortex_m_rt::entry;
6use defmt::*; 6use defmt::*;
7use embassy_stm32::bind_interrupts;
7use embassy_stm32::can::bxcan::filter::Mask32; 8use embassy_stm32::can::bxcan::filter::Mask32;
8use embassy_stm32::can::bxcan::{Fifo, Frame, StandardId}; 9use embassy_stm32::can::bxcan::{Fifo, Frame, StandardId};
9use embassy_stm32::can::Can; 10use embassy_stm32::can::{Can, Rx0InterruptHandler, Rx1InterruptHandler, SceInterruptHandler, TxInterruptHandler};
10use embassy_stm32::gpio::{Input, Pull}; 11use embassy_stm32::gpio::{Input, Pull};
12use embassy_stm32::peripherals::CAN1;
11use {defmt_rtt as _, panic_probe as _}; 13use {defmt_rtt as _, panic_probe as _};
12 14
15bind_interrupts!(struct Irqs {
16 CAN1_RX0 => Rx0InterruptHandler<CAN1>;
17 CAN1_RX1 => Rx1InterruptHandler<CAN1>;
18 CAN1_SCE => SceInterruptHandler<CAN1>;
19 CAN1_TX => TxInterruptHandler<CAN1>;
20});
21
13#[entry] 22#[entry]
14fn main() -> ! { 23fn main() -> ! {
15 info!("Hello World!"); 24 info!("Hello World!");
@@ -23,7 +32,7 @@ fn main() -> ! {
23 let rx_pin = Input::new(&mut p.PA11, Pull::Up); 32 let rx_pin = Input::new(&mut p.PA11, Pull::Up);
24 core::mem::forget(rx_pin); 33 core::mem::forget(rx_pin);
25 34
26 let mut can = Can::new(p.CAN1, p.PA11, p.PA12); 35 let mut can = Can::new(p.CAN1, p.PA11, p.PA12, Irqs);
27 36
28 can.modify_filters().enable_bank(0, Fifo::Fifo0, Mask32::accept_all()); 37 can.modify_filters().enable_bank(0, Fifo::Fifo0, Mask32::accept_all());
29 38