Merge branch 'main' into main

4 files changed, 194 insertions, 8 deletions

diff --git a/examples/stm32g4/Cargo.toml b/examples/stm32g4/Cargo.toml
index 6fd282d6d..8bbeb594c 100644
--- a/examples/stm32g4/Cargo.toml
+++ b/examples/stm32g4/Cargo.toml
@@ -7,12 +7,12 @@ publish = false
 
 [dependencies]
 # Change stm32g491re to your chip name, if necessary.
-embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32g491re", "memory-x", "unstable-pac", "exti"]  }
-embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
-embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
-embassy-usb = { version = "0.5.1", path = "../../embassy-usb", features = ["defmt"] }
-embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
+embassy-stm32 = { path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32g491re", "memory-x", "unstable-pac", "exti"]  }
+embassy-sync = { path = "../../embassy-sync", features = ["defmt"] }
+embassy-executor = { path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
+embassy-time = { path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
+embassy-usb = { path = "../../embassy-usb", features = ["defmt"] }
+embassy-futures = { path = "../../embassy-futures" }
 usbd-hid = "0.8.1"
 
 defmt = "1.0.1"
@@ -25,6 +25,7 @@ embedded-can = { version = "0.4" }
 panic-probe = { version = "1.0.0", features = ["print-defmt"] }
 heapless = { version = "0.8", default-features = false }
 static_cell = "2.0.0"
+critical-section = "1.1"
 
 [profile.release]
 debug = 2
diff --git a/examples/stm32g4/src/bin/adc_dma.rs b/examples/stm32g4/src/bin/adc_dma.rs
index a82067049..ef8b0c3c2 100644
--- a/examples/stm32g4/src/bin/adc_dma.rs
+++ b/examples/stm32g4/src/bin/adc_dma.rs
@@ -12,7 +12,7 @@ static mut DMA_BUF: [u16; 2] = [0; 2];
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
-    let mut read_buffer = unsafe { &mut DMA_BUF[..] };
+    let read_buffer = unsafe { &mut DMA_BUF[..] };
 
     let mut config = Config::default();
     {
@@ -47,7 +47,7 @@ async fn main(_spawner: Spawner) {
                 (&mut pa0, SampleTime::CYCLES247_5),
             ]
             .into_iter(),
-            &mut read_buffer,
+            read_buffer,
         )
         .await;
 
diff --git a/examples/stm32g4/src/bin/adc_injected_and_regular.rs b/examples/stm32g4/src/bin/adc_injected_and_regular.rs
new file mode 100644
index 000000000..3ae2ff064
--- /dev/null
+++ b/examples/stm32g4/src/bin/adc_injected_and_regular.rs
@@ -0,0 +1,154 @@
+//! adc injected and regular conversions
+//!
+//! This example both regular and injected ADC conversions at the same time
+//! p:pa0 n:pa2
+
+#![no_std]
+#![no_main]
+
+use core::cell::RefCell;
+
+use defmt::info;
+use embassy_stm32::adc::{
+    Adc, AdcChannel as _, ConversionTrigger, Exten, InjectedAdc, RegularConversionMode, SampleTime,
+};
+use embassy_stm32::interrupt::typelevel::{ADC1_2, Interrupt};
+use embassy_stm32::peripherals::ADC1;
+use embassy_stm32::time::Hertz;
+use embassy_stm32::timer::complementary_pwm::{ComplementaryPwm, Mms2};
+use embassy_stm32::timer::low_level::CountingMode;
+use embassy_stm32::{Config, interrupt};
+use embassy_sync::blocking_mutex::CriticalSectionMutex;
+use {defmt_rtt as _, panic_probe as _};
+
+static ADC1_HANDLE: CriticalSectionMutex<RefCell<Option<InjectedAdc<ADC1, 1>>>> =
+    CriticalSectionMutex::new(RefCell::new(None));
+
+/// This example showcases how to use both regular ADC conversions with DMA and injected ADC
+/// conversions with ADC interrupt simultaneously. Both conversion types can be configured with
+/// different triggers and thanks to DMA it is possible to use the measurements in different task
+/// without needing to access the ADC peripheral.
+///
+/// If you don't need both regular and injected conversions the example code can easily be reworked
+/// to only include one of the ADC conversion types.
+#[embassy_executor::main]
+async fn main(_spawner: embassy_executor::Spawner) {
+    // See Table 166 and 167 in RM0440 Rev 9 for ADC1/2 External triggers
+    // Note: Regular and Injected channels use different tables!!
+    const ADC1_INJECTED_TRIGGER_TIM1_TRGO2: u8 = 8;
+    const ADC1_REGULAR_TRIGGER_TIM1_TRGO2: u8 = 10;
+
+    // --- RCC config ---
+    let mut config = Config::default();
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.pll = Some(Pll {
+            source: PllSource::HSI,
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL85,
+            divp: None,
+            divq: None,
+            divr: Some(PllRDiv::DIV2),
+        });
+        config.rcc.mux.adc12sel = mux::Adcsel::SYS;
+        config.rcc.sys = Sysclk::PLL1_R;
+    }
+    let p = embassy_stm32::init(config);
+
+    // In this example we use tim1_trgo2 event to trigger the ADC conversions
+    let tim1 = p.TIM1;
+    let pwm_freq = 1;
+    let mut pwm = ComplementaryPwm::new(
+        tim1,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        Hertz::hz(pwm_freq),
+        CountingMode::EdgeAlignedUp,
+    );
+    pwm.set_master_output_enable(false);
+    // Mms2 is used to configure which timer event that is connected to tim1_trgo2.
+    // In this case we use the update event of the timer.
+    pwm.set_mms2(Mms2::UPDATE);
+
+    // Configure regular conversions with DMA
+    let adc1 = Adc::new(p.ADC1);
+
+    let vrefint_channel = adc1.enable_vrefint().degrade_adc();
+    let pa0 = p.PC1.degrade_adc();
+    let regular_sequence = [
+        (vrefint_channel, SampleTime::CYCLES247_5),
+        (pa0, SampleTime::CYCLES247_5),
+    ]
+    .into_iter();
+
+    // Configurations of Injected ADC measurements
+    let pa2 = p.PA2.degrade_adc();
+    let injected_sequence = [(pa2, SampleTime::CYCLES247_5)];
+
+    // Configure DMA for retrieving regular ADC measurements
+    let dma1_ch1 = p.DMA1_CH1;
+    // Using buffer of double size means the half-full interrupts will generate at the expected rate
+    let mut readings = [0u16; 4];
+
+    let injected_trigger = ConversionTrigger {
+        channel: ADC1_INJECTED_TRIGGER_TIM1_TRGO2,
+        edge: Exten::RISING_EDGE,
+    };
+    let regular_trigger = ConversionTrigger {
+        channel: ADC1_REGULAR_TRIGGER_TIM1_TRGO2,
+        edge: Exten::RISING_EDGE,
+    };
+
+    let (mut ring_buffered_adc, injected_adc) = adc1.into_ring_buffered_and_injected(
+        dma1_ch1,
+        &mut readings,
+        regular_sequence,
+        RegularConversionMode::Triggered(regular_trigger),
+        injected_sequence,
+        injected_trigger,
+        true,
+    );
+
+    // Store ADC globally to allow access from ADC interrupt
+    critical_section::with(|cs| {
+        ADC1_HANDLE.borrow(cs).replace(Some(injected_adc));
+    });
+    // Enable interrupt for ADC1_2
+    unsafe { ADC1_2::enable() };
+
+    // Main loop for reading regular ADC measurements periodically
+    let mut data = [0u16; 2];
+    loop {
+        {
+            match ring_buffered_adc.read(&mut data).await {
+                Ok(n) => {
+                    defmt::info!("Regular ADC reading, VrefInt: {}, PA0: {}", data[0], data[1]);
+                    defmt::info!("Remaining samples: {}", n,);
+                }
+                Err(e) => {
+                    defmt::error!("DMA error: {:?}", e);
+                    ring_buffered_adc.clear();
+                }
+            }
+        }
+    }
+}
+
+/// Use ADC1_2 interrupt to retrieve injected ADC measurements
+/// Interrupt must be unsafe as hardware can invoke it any-time. Critical sections ensure safety
+/// within the interrupt.
+#[interrupt]
+unsafe fn ADC1_2() {
+    critical_section::with(|cs| {
+        if let Some(injected_adc) = ADC1_HANDLE.borrow(cs).borrow_mut().as_mut() {
+            let injected_data = injected_adc.read_injected_samples();
+            info!("Injected reading of PA2: {}", injected_data[0]);
+        }
+    });
+}
diff --git a/examples/stm32h5/src/bin/backup_sram.rs b/examples/stm32h5/src/bin/backup_sram.rs
new file mode 100644
index 000000000..f8db1853e
--- /dev/null
+++ b/examples/stm32h5/src/bin/backup_sram.rs
@@ -0,0 +1,31 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::Config;
+use embassy_stm32::backup_sram::BackupMemory;
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.rcc.ls.enable_backup_sram = true;
+
+    let p = embassy_stm32::init(config);
+    info!("Started!");
+
+    let (bytes, status) = BackupMemory::new(p.BKPSRAM);
+
+    match status {
+        false => info!("BKPSRAM just enabled"),
+        true => info!("BKPSRAM already enabled"),
+    }
+
+    loop {
+        info!("byte0: {}", bytes[0]);
+        bytes[0] = bytes[0].wrapping_add(1);
+        Timer::after_millis(500).await;
+    }
+}