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authorDario Nieuwenhuis <[email protected]>2022-09-25 23:37:54 +0200
committerGitHub <[email protected]>2022-09-25 23:37:54 +0200
commit6b35f654ba070e2ff539bd84a36054c95817bae3 (patch)
tree2ef4979b47a2a89906ab6a13ff8d2570401ee994 /src
parent11387c3b036935716b2fdeeb0e5312808aa782ff (diff)
parent28bf4b7b6da0e0f6ce0878580363f135c7e7a879 (diff)
Merge pull request #22 from danbev/antdiv-const
Add const for IOCTL ANTDIV
Diffstat (limited to 'src')
-rw-r--r--src/lib.rs4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/lib.rs b/src/lib.rs
index 7fd9200fe..6978695d9 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -138,6 +138,7 @@ const IRQ_F3_INTR: u16 = 0x8000;
138 138
139const IOCTL_CMD_UP: u32 = 2; 139const IOCTL_CMD_UP: u32 = 2;
140const IOCTL_CMD_SET_SSID: u32 = 26; 140const IOCTL_CMD_SET_SSID: u32 = 26;
141const IOCTL_CMD_ANTDIV: u32 = 64;
141const IOCTL_CMD_SET_VAR: u32 = 263; 142const IOCTL_CMD_SET_VAR: u32 = 263;
142const IOCTL_CMD_GET_VAR: u32 = 262; 143const IOCTL_CMD_GET_VAR: u32 = 262;
143const IOCTL_CMD_SET_PASSPHRASE: u32 = 268; 144const IOCTL_CMD_SET_PASSPHRASE: u32 = 268;
@@ -317,7 +318,8 @@ impl<'a> Control<'a> {
317 // set country takes some time, next ioctls fail if we don't wait. 318 // set country takes some time, next ioctls fail if we don't wait.
318 Timer::after(Duration::from_millis(100)).await; 319 Timer::after(Duration::from_millis(100)).await;
319 320
320 self.ioctl_set_u32(64, 0, 0).await; // WLC_SET_ANTDIV 321 // Set antenna to chip antenna
322 self.ioctl_set_u32(IOCTL_CMD_ANTDIV, 0, 0).await;
321 323
322 self.set_iovar_u32("bus:txglom", 0).await; 324 self.set_iovar_u32("bus:txglom", 0).await;
323 Timer::after(Duration::from_millis(100)).await; 325 Timer::after(Duration::from_millis(100)).await;