diff options
| author | HybridChild <[email protected]> | 2025-11-13 09:14:03 +0100 |
|---|---|---|
| committer | HybridChild <[email protected]> | 2025-11-13 09:21:23 +0100 |
| commit | 03050a369befb7aeed88079626de21b4055ebccb (patch) | |
| tree | 28ed438a437b818f674619b886527748ff24e89b /tests | |
| parent | 9e2a4161b32154f19963a222b3eb8f956b60d820 (diff) | |
stm32/i2c: Add comprehensive v2 Master API tests and fix async issues
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/stm32/Cargo.toml | 4 | ||||
| -rw-r--r-- | tests/stm32/src/bin/i2c_v2_master.rs (renamed from tests/stm32/src/bin/i2c_v2.rs) | 266 |
2 files changed, 245 insertions, 25 deletions
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml index fa757e276..1912a772c 100644 --- a/tests/stm32/Cargo.toml +++ b/tests/stm32/Cargo.toml | |||
| @@ -161,8 +161,8 @@ path = "src/bin/hash.rs" | |||
| 161 | required-features = [ "hash",] | 161 | required-features = [ "hash",] |
| 162 | 162 | ||
| 163 | [[bin]] | 163 | [[bin]] |
| 164 | name = "i2c_v2" | 164 | name = "i2c_v2_master" |
| 165 | path = "src/bin/i2c_v2.rs" | 165 | path = "src/bin/i2c_v2_master.rs" |
| 166 | required-features = [ "stm32f072rb",] | 166 | required-features = [ "stm32f072rb",] |
| 167 | 167 | ||
| 168 | [[bin]] | 168 | [[bin]] |
diff --git a/tests/stm32/src/bin/i2c_v2.rs b/tests/stm32/src/bin/i2c_v2_master.rs index 087b8bbd9..b841d556a 100644 --- a/tests/stm32/src/bin/i2c_v2.rs +++ b/tests/stm32/src/bin/i2c_v2_master.rs | |||
| @@ -9,11 +9,12 @@ | |||
| 9 | // - Pull-up resistors: 4.7kΩ on both SCL and SDA | 9 | // - Pull-up resistors: 4.7kΩ on both SCL and SDA |
| 10 | // - CN5 Pin 10 (PB8/SCL) and CN5 Pin 9 (PB9/SDA) | 10 | // - CN5 Pin 10 (PB8/SCL) and CN5 Pin 9 (PB9/SDA) |
| 11 | // | 11 | // |
| 12 | // Analog Discovery Setup: | 12 | // Analog Discovery - Waveforms Setup: |
| 13 | // - Increase buffer size: Settings -> Device Manager -> Option 4 | ||
| 14 | // - Run Protocol Analyzer | ||
| 13 | // - Configure as I2C Slave at address 0x50 | 15 | // - Configure as I2C Slave at address 0x50 |
| 14 | // - DIO 0: SCL | 16 | // - Connect and configure DIO pins for SCL and SDA |
| 15 | // - DIO 1: SDA | 17 | // - Frequency: 100kHz - [✓] Clock Stretching |
| 16 | // - Enable pull-ups or use external 4.7kΩ pull-up resistors | ||
| 17 | 18 | ||
| 18 | #[path = "../common.rs"] | 19 | #[path = "../common.rs"] |
| 19 | mod common; | 20 | mod common; |
| @@ -29,7 +30,7 @@ use embedded_hal_1::i2c::Operation; | |||
| 29 | #[embassy_executor::main] | 30 | #[embassy_executor::main] |
| 30 | async fn main(_spawner: Spawner) { | 31 | async fn main(_spawner: Spawner) { |
| 31 | let p = init(); | 32 | let p = init(); |
| 32 | info!("I2C v2 Transaction Test Starting..."); | 33 | info!("Run stm32 I2C v2 Master Tests..."); |
| 33 | 34 | ||
| 34 | let mut i2c_peri = peri!(p, I2C); | 35 | let mut i2c_peri = peri!(p, I2C); |
| 35 | let mut scl = peri!(p, I2C_SCL); | 36 | let mut scl = peri!(p, I2C_SCL); |
| @@ -44,7 +45,37 @@ async fn main(_spawner: Spawner) { | |||
| 44 | // Wait for slave device to be ready | 45 | // Wait for slave device to be ready |
| 45 | Timer::after_millis(100).await; | 46 | Timer::after_millis(100).await; |
| 46 | 47 | ||
| 47 | // ========== BLOCKING TESTS ========== | 48 | // ========== BLOCKING DIRECT API TESTS ========== |
| 49 | info!("========== BLOCKING DIRECT API TESTS =========="); | ||
| 50 | { | ||
| 51 | let mut i2c = I2c::new_blocking( | ||
| 52 | i2c_peri.reborrow(), | ||
| 53 | scl.reborrow(), | ||
| 54 | sda.reborrow(), | ||
| 55 | config, | ||
| 56 | ); | ||
| 57 | |||
| 58 | info!("=== Test 1: Direct blocking_write ==="); | ||
| 59 | test_blocking_write(&mut i2c, slave_addr); | ||
| 60 | |||
| 61 | info!("=== Test 2: Direct blocking_read ==="); | ||
| 62 | test_blocking_read(&mut i2c, slave_addr); | ||
| 63 | |||
| 64 | info!("=== Test 3: Direct blocking_write_read ==="); | ||
| 65 | test_blocking_write_read(&mut i2c, slave_addr); | ||
| 66 | |||
| 67 | info!("=== Test 4: Direct blocking_write_vectored ==="); | ||
| 68 | test_blocking_write_vectored(&mut i2c, slave_addr); | ||
| 69 | |||
| 70 | info!("=== Test 5: Large buffer (>255 bytes) ==="); | ||
| 71 | test_blocking_large_buffer(&mut i2c, slave_addr); | ||
| 72 | |||
| 73 | info!("Blocking direct API tests OK"); | ||
| 74 | } | ||
| 75 | |||
| 76 | Timer::after_millis(100).await; | ||
| 77 | |||
| 78 | // ========== BLOCKING TRANSACTION TESTS ========== | ||
| 48 | info!("========== BLOCKING TRANSACTION TESTS =========="); | 79 | info!("========== BLOCKING TRANSACTION TESTS =========="); |
| 49 | { | 80 | { |
| 50 | let mut i2c = I2c::new_blocking( | 81 | let mut i2c = I2c::new_blocking( |
| @@ -54,31 +85,31 @@ async fn main(_spawner: Spawner) { | |||
| 54 | config, | 85 | config, |
| 55 | ); | 86 | ); |
| 56 | 87 | ||
| 57 | info!("=== Test 1: Consecutive Writes (Should Merge) ==="); | 88 | info!("=== Test 6: Consecutive Writes (Should Merge) ==="); |
| 58 | test_consecutive_writes_blocking(&mut i2c, slave_addr); | 89 | test_consecutive_writes_blocking(&mut i2c, slave_addr); |
| 59 | 90 | ||
| 60 | info!("=== Test 2: Consecutive Reads (Should Merge) ==="); | 91 | info!("=== Test 7: Consecutive Reads (Should Merge) ==="); |
| 61 | test_consecutive_reads_blocking(&mut i2c, slave_addr); | 92 | test_consecutive_reads_blocking(&mut i2c, slave_addr); |
| 62 | 93 | ||
| 63 | info!("=== Test 3: Write then Read (RESTART) ==="); | 94 | info!("=== Test 8: Write then Read (RESTART) ==="); |
| 64 | test_write_then_read_blocking(&mut i2c, slave_addr); | 95 | test_write_then_read_blocking(&mut i2c, slave_addr); |
| 65 | 96 | ||
| 66 | info!("=== Test 4: Read then Write (RESTART) ==="); | 97 | info!("=== Test 9: Read then Write (RESTART) ==="); |
| 67 | test_read_then_write_blocking(&mut i2c, slave_addr); | 98 | test_read_then_write_blocking(&mut i2c, slave_addr); |
| 68 | 99 | ||
| 69 | info!("=== Test 5: Complex Mixed Sequence ==="); | 100 | info!("=== Test 10: Complex Mixed Sequence ==="); |
| 70 | test_mixed_sequence_blocking(&mut i2c, slave_addr); | 101 | test_mixed_sequence_blocking(&mut i2c, slave_addr); |
| 71 | 102 | ||
| 72 | info!("=== Test 6: Single Operations ==="); | 103 | info!("=== Test 11: Single Operations ==="); |
| 73 | test_single_operations_blocking(&mut i2c, slave_addr); | 104 | test_single_operations_blocking(&mut i2c, slave_addr); |
| 74 | 105 | ||
| 75 | info!("Blocking tests OK"); | 106 | info!("Blocking transaction tests OK"); |
| 76 | } | 107 | } |
| 77 | 108 | ||
| 78 | Timer::after_millis(100).await; | 109 | Timer::after_millis(100).await; |
| 79 | 110 | ||
| 80 | // ========== ASYNC TESTS ========== | 111 | // ========== ASYNC TESTS (DMA) ========== |
| 81 | info!("========== ASYNC TRANSACTION TESTS (DMA) =========="); | 112 | info!("========== ASYNC TESTS (DMA) =========="); |
| 82 | { | 113 | { |
| 83 | let tx_dma = peri!(p, I2C_TX_DMA); | 114 | let tx_dma = peri!(p, I2C_TX_DMA); |
| 84 | let rx_dma = peri!(p, I2C_RX_DMA); | 115 | let rx_dma = peri!(p, I2C_RX_DMA); |
| @@ -86,31 +117,136 @@ async fn main(_spawner: Spawner) { | |||
| 86 | 117 | ||
| 87 | let mut i2c = I2c::new(i2c_peri, scl, sda, irq, tx_dma, rx_dma, config); | 118 | let mut i2c = I2c::new(i2c_peri, scl, sda, irq, tx_dma, rx_dma, config); |
| 88 | 119 | ||
| 89 | info!("=== Test 1: Consecutive Writes (Should Merge) ==="); | 120 | // Direct API tests (reusing same I2C instance) |
| 121 | info!("=== Direct API Test 1: write() ==="); | ||
| 122 | test_async_write(&mut i2c, slave_addr).await; | ||
| 123 | |||
| 124 | info!("=== Direct API Test 2: read() ==="); | ||
| 125 | test_async_read(&mut i2c, slave_addr).await; | ||
| 126 | |||
| 127 | info!("=== Direct API Test 3: write_read() ==="); | ||
| 128 | test_async_write_read(&mut i2c, slave_addr).await; | ||
| 129 | |||
| 130 | info!("=== Direct API Test 4: write_vectored() ==="); | ||
| 131 | test_async_write_vectored(&mut i2c, slave_addr).await; | ||
| 132 | |||
| 133 | info!("=== Direct API Test 5: Large buffer (>255 bytes) ==="); | ||
| 134 | test_async_large_buffer(&mut i2c, slave_addr).await; | ||
| 135 | |||
| 136 | info!("Async Direct API tests OK"); | ||
| 137 | |||
| 138 | // Transaction tests | ||
| 139 | info!("=== Transaction Test 6: Consecutive Writes (Should Merge) ==="); | ||
| 90 | test_consecutive_writes_async(&mut i2c, slave_addr).await; | 140 | test_consecutive_writes_async(&mut i2c, slave_addr).await; |
| 91 | 141 | ||
| 92 | info!("=== Test 2: Consecutive Reads (Should Merge) ==="); | 142 | info!("=== Transaction Test 7: Consecutive Reads (Should Merge) ==="); |
| 93 | test_consecutive_reads_async(&mut i2c, slave_addr).await; | 143 | test_consecutive_reads_async(&mut i2c, slave_addr).await; |
| 94 | 144 | ||
| 95 | info!("=== Test 3: Write then Read (RESTART) ==="); | 145 | info!("=== Transaction Test 8: Write then Read (RESTART) ==="); |
| 96 | test_write_then_read_async(&mut i2c, slave_addr).await; | 146 | test_write_then_read_async(&mut i2c, slave_addr).await; |
| 97 | 147 | ||
| 98 | info!("=== Test 4: Read then Write (RESTART) ==="); | 148 | info!("=== Transaction Test 9: Read then Write (RESTART) ==="); |
| 99 | test_read_then_write_async(&mut i2c, slave_addr).await; | 149 | test_read_then_write_async(&mut i2c, slave_addr).await; |
| 100 | 150 | ||
| 101 | info!("=== Test 5: Complex Mixed Sequence ==="); | 151 | info!("=== Transaction Test 10: Complex Mixed Sequence ==="); |
| 102 | test_mixed_sequence_async(&mut i2c, slave_addr).await; | 152 | test_mixed_sequence_async(&mut i2c, slave_addr).await; |
| 103 | 153 | ||
| 104 | info!("=== Test 6: Single Operations ==="); | 154 | info!("=== Transaction Test 11: Single Operations ==="); |
| 105 | test_single_operations_async(&mut i2c, slave_addr).await; | 155 | test_single_operations_async(&mut i2c, slave_addr).await; |
| 106 | 156 | ||
| 107 | info!("Async tests OK"); | 157 | info!("Async transaction tests OK"); |
| 108 | } | 158 | } |
| 109 | 159 | ||
| 110 | info!("All tests OK"); | 160 | info!("All tests OK"); |
| 111 | cortex_m::asm::bkpt(); | 161 | cortex_m::asm::bkpt(); |
| 112 | } | 162 | } |
| 113 | 163 | ||
| 164 | // ==================== BLOCKING DIRECT API TEST FUNCTIONS ==================== | ||
| 165 | |||
| 166 | fn test_blocking_write(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) { | ||
| 167 | let write_data = [0x42, 0x43, 0x44, 0x45]; | ||
| 168 | |||
| 169 | match i2c.blocking_write(addr, &write_data) { | ||
| 170 | Ok(_) => info!("✓ blocking_write succeeded: {:02x}", write_data), | ||
| 171 | Err(e) => { | ||
| 172 | error!("✗ blocking_write failed: {:?}", e); | ||
| 173 | defmt::panic!("Test failed: blocking_write"); | ||
| 174 | } | ||
| 175 | } | ||
| 176 | } | ||
| 177 | |||
| 178 | fn test_blocking_read(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) { | ||
| 179 | let mut read_buf = [0u8; 8]; | ||
| 180 | |||
| 181 | match i2c.blocking_read(addr, &mut read_buf) { | ||
| 182 | Ok(_) => info!("✓ blocking_read succeeded: {:02x}", read_buf), | ||
| 183 | Err(e) => { | ||
| 184 | error!("✗ blocking_read failed: {:?}", e); | ||
| 185 | defmt::panic!("Test failed: blocking_read"); | ||
| 186 | } | ||
| 187 | } | ||
| 188 | } | ||
| 189 | |||
| 190 | fn test_blocking_write_read(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) { | ||
| 191 | let write_data = [0x50, 0x51]; | ||
| 192 | let mut read_buf = [0u8; 6]; | ||
| 193 | |||
| 194 | match i2c.blocking_write_read(addr, &write_data, &mut read_buf) { | ||
| 195 | Ok(_) => { | ||
| 196 | info!("✓ blocking_write_read succeeded"); | ||
| 197 | info!(" Written: {:02x}", write_data); | ||
| 198 | info!(" Read: {:02x}", read_buf); | ||
| 199 | } | ||
| 200 | Err(e) => { | ||
| 201 | error!("✗ blocking_write_read failed: {:?}", e); | ||
| 202 | defmt::panic!("Test failed: blocking_write_read"); | ||
| 203 | } | ||
| 204 | } | ||
| 205 | } | ||
| 206 | |||
| 207 | fn test_blocking_write_vectored(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) { | ||
| 208 | let buf1 = [0x60, 0x61, 0x62]; | ||
| 209 | let buf2 = [0x70, 0x71]; | ||
| 210 | let buf3 = [0x80, 0x81, 0x82, 0x83]; | ||
| 211 | let bufs = [&buf1[..], &buf2[..], &buf3[..]]; | ||
| 212 | |||
| 213 | match i2c.blocking_write_vectored(addr, &bufs) { | ||
| 214 | Ok(_) => info!("✓ blocking_write_vectored succeeded (9 bytes total)"), | ||
| 215 | Err(e) => { | ||
| 216 | error!("✗ blocking_write_vectored failed: {:?}", e); | ||
| 217 | defmt::panic!("Test failed: blocking_write_vectored"); | ||
| 218 | } | ||
| 219 | } | ||
| 220 | } | ||
| 221 | |||
| 222 | fn test_blocking_large_buffer(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) { | ||
| 223 | // Test with 300 bytes to verify RELOAD mechanism works (needs chunking at 255 bytes) | ||
| 224 | let mut write_buf = [0u8; 300]; | ||
| 225 | for (i, byte) in write_buf.iter_mut().enumerate() { | ||
| 226 | *byte = (i & 0xFF) as u8; | ||
| 227 | } | ||
| 228 | |||
| 229 | match i2c.blocking_write(addr, &write_buf) { | ||
| 230 | Ok(_) => info!("✓ Large buffer write succeeded (300 bytes, tests RELOAD)"), | ||
| 231 | Err(e) => { | ||
| 232 | error!("✗ Large buffer write failed: {:?}", e); | ||
| 233 | defmt::panic!("Test failed: large buffer write"); | ||
| 234 | } | ||
| 235 | } | ||
| 236 | |||
| 237 | // Test large read | ||
| 238 | let mut read_buf = [0u8; 300]; | ||
| 239 | match i2c.blocking_read(addr, &mut read_buf) { | ||
| 240 | Ok(_) => info!("✓ Large buffer read succeeded (300 bytes, tests RELOAD)"), | ||
| 241 | Err(e) => { | ||
| 242 | error!("✗ Large buffer read failed: {:?}", e); | ||
| 243 | defmt::panic!("Test failed: large buffer read"); | ||
| 244 | } | ||
| 245 | } | ||
| 246 | } | ||
| 247 | |||
| 248 | // ==================== BLOCKING TRANSACTION TEST FUNCTIONS ==================== | ||
| 249 | |||
| 114 | fn test_consecutive_writes_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) { | 250 | fn test_consecutive_writes_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) { |
| 115 | // Expected on bus: START, ADDR+W, data1, data2, data3, STOP | 251 | // Expected on bus: START, ADDR+W, data1, data2, data3, STOP |
| 116 | // NO intermediate RESTART/STOP between writes - they should be merged | 252 | // NO intermediate RESTART/STOP between writes - they should be merged |
| @@ -257,7 +393,91 @@ fn test_single_operations_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8 | |||
| 257 | } | 393 | } |
| 258 | } | 394 | } |
| 259 | 395 | ||
| 260 | // ==================== ASYNC TEST FUNCTIONS ==================== | 396 | // ==================== ASYNC DIRECT API TEST FUNCTIONS ==================== |
| 397 | |||
| 398 | async fn test_async_write(i2c: &mut I2c<'_, Async, Master>, addr: u8) { | ||
| 399 | let write_data = [0x42, 0x43, 0x44, 0x45]; | ||
| 400 | |||
| 401 | match i2c.write(addr, &write_data).await { | ||
| 402 | Ok(_) => info!("✓ async write succeeded: {:02x}", write_data), | ||
| 403 | Err(e) => { | ||
| 404 | error!("✗ async write failed: {:?}", e); | ||
| 405 | defmt::panic!("Test failed: async write"); | ||
| 406 | } | ||
| 407 | } | ||
| 408 | } | ||
| 409 | |||
| 410 | async fn test_async_read(i2c: &mut I2c<'_, Async, Master>, addr: u8) { | ||
| 411 | let mut read_buf = [0u8; 8]; | ||
| 412 | |||
| 413 | match i2c.read(addr, &mut read_buf).await { | ||
| 414 | Ok(_) => info!("✓ async read succeeded: {:02x}", read_buf), | ||
| 415 | Err(e) => { | ||
| 416 | error!("✗ async read failed: {:?}", e); | ||
| 417 | defmt::panic!("Test failed: async read"); | ||
| 418 | } | ||
| 419 | } | ||
| 420 | } | ||
| 421 | |||
| 422 | async fn test_async_write_read(i2c: &mut I2c<'_, Async, Master>, addr: u8) { | ||
| 423 | let write_data = [0x50, 0x51]; | ||
| 424 | let mut read_buf = [0u8; 6]; | ||
| 425 | |||
| 426 | match i2c.write_read(addr, &write_data, &mut read_buf).await { | ||
| 427 | Ok(_) => { | ||
| 428 | info!("✓ async write_read succeeded"); | ||
| 429 | info!(" Written: {:02x}", write_data); | ||
| 430 | info!(" Read: {:02x}", read_buf); | ||
| 431 | } | ||
| 432 | Err(e) => { | ||
| 433 | error!("✗ async write_read failed: {:?}", e); | ||
| 434 | defmt::panic!("Test failed: async write_read"); | ||
| 435 | } | ||
| 436 | } | ||
| 437 | } | ||
| 438 | |||
| 439 | async fn test_async_write_vectored(i2c: &mut I2c<'_, Async, Master>, addr: u8) { | ||
| 440 | let buf1 = [0x60, 0x61, 0x62]; | ||
| 441 | let buf2 = [0x70, 0x71]; | ||
| 442 | let buf3 = [0x80, 0x81, 0x82, 0x83]; | ||
| 443 | let bufs = [&buf1[..], &buf2[..], &buf3[..]]; | ||
| 444 | |||
| 445 | match i2c.write_vectored(addr.into(), &bufs).await { | ||
| 446 | Ok(_) => info!("✓ async write_vectored succeeded (9 bytes total)"), | ||
| 447 | Err(e) => { | ||
| 448 | error!("✗ async write_vectored failed: {:?}", e); | ||
| 449 | defmt::panic!("Test failed: async write_vectored"); | ||
| 450 | } | ||
| 451 | } | ||
| 452 | } | ||
| 453 | |||
| 454 | async fn test_async_large_buffer(i2c: &mut I2c<'_, Async, Master>, addr: u8) { | ||
| 455 | // Test with 300 bytes to verify RELOAD mechanism works with DMA (needs chunking at 255 bytes) | ||
| 456 | let mut write_buf = [0u8; 300]; | ||
| 457 | for (i, byte) in write_buf.iter_mut().enumerate() { | ||
| 458 | *byte = (i & 0xFF) as u8; | ||
| 459 | } | ||
| 460 | |||
| 461 | match i2c.write(addr, &write_buf).await { | ||
| 462 | Ok(_) => info!("✓ Large buffer async write succeeded (300 bytes, tests RELOAD with DMA)"), | ||
| 463 | Err(e) => { | ||
| 464 | error!("✗ Large buffer async write failed: {:?}", e); | ||
| 465 | defmt::panic!("Test failed: large buffer async write"); | ||
| 466 | } | ||
| 467 | } | ||
| 468 | |||
| 469 | // Test large read | ||
| 470 | let mut read_buf = [0u8; 300]; | ||
| 471 | match i2c.read(addr, &mut read_buf).await { | ||
| 472 | Ok(_) => info!("✓ Large buffer async read succeeded (300 bytes, tests RELOAD with DMA)"), | ||
| 473 | Err(e) => { | ||
| 474 | error!("✗ Large buffer async read failed: {:?}", e); | ||
| 475 | defmt::panic!("Test failed: large buffer async read"); | ||
| 476 | } | ||
| 477 | } | ||
| 478 | } | ||
| 479 | |||
| 480 | // ==================== ASYNC TRANSACTION TEST FUNCTIONS ==================== | ||
| 261 | 481 | ||
| 262 | async fn test_consecutive_writes_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) { | 482 | async fn test_consecutive_writes_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) { |
| 263 | let data1 = [0x10, 0x11, 0x12]; | 483 | let data1 = [0x10, 0x11, 0x12]; |
