stm32/i2c: Fix v2 async transaction implementation

3 files changed, 210 insertions, 31 deletions

diff --git a/tests/stm32/build.rs b/tests/stm32/build.rs
index 556d77a20..34030c206 100644
--- a/tests/stm32/build.rs
+++ b/tests/stm32/build.rs
@@ -15,6 +15,7 @@ fn main() -> Result<(), Box<dyn Error>> {
         feature = "stm32c071rb", // 24 kb
         feature = "stm32l073rz", // 20 kb
         feature = "stm32h503rb", // 32 kb
+        feature = "stm32f072rb", // 16 kb - I2C v2 test with async too large for RAM
         // no VTOR, so interrupts can't work when running from RAM
         feature = "stm32f091rc",
     )) {
diff --git a/tests/stm32/src/bin/i2c_v2.rs b/tests/stm32/src/bin/i2c_v2.rs
index 9a23e28e1..087b8bbd9 100644
--- a/tests/stm32/src/bin/i2c_v2.rs
+++ b/tests/stm32/src/bin/i2c_v2.rs
@@ -7,7 +7,7 @@
 // - Connect to I2C slave device (e.g., Digilent Analog Discovery I2C slave, or EEPROM)
 // - Default slave address: 0x50
 // - Pull-up resistors: 4.7kΩ on both SCL and SDA
-// - CN5 Pin 5 (PB8/SCL) and CN5 Pin 9 (PB9/SDA)
+// - CN5 Pin 10 (PB8/SCL) and CN5 Pin 9 (PB9/SDA)
 //
 // Analog Discovery Setup:
 // - Configure as I2C Slave at address 0x50
@@ -21,9 +21,9 @@ mod common;
 use common::*;
 use embassy_executor::Spawner;
 use embassy_stm32::i2c::{Config, I2c, Master};
-use embassy_stm32::mode::Blocking;
+use embassy_stm32::mode::{Async, Blocking};
 use embassy_stm32::time::Hertz;
-use embassy_time::block_for;
+use embassy_time::Timer;
 use embedded_hal_1::i2c::Operation;
 
 #[embassy_executor::main]
@@ -38,42 +38,80 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     config.frequency = Hertz(100_000);
 
-    let mut i2c = I2c::new_blocking(
-        i2c_peri.reborrow(),
-        scl.reborrow(),
-        sda.reborrow(),
-        config,
-    );
-
     // I2C slave address for Analog Discovery or test EEPROM
     let slave_addr = 0x50u8;
 
     // Wait for slave device to be ready
-    block_for(embassy_time::Duration::from_millis(100));
+    Timer::after_millis(100).await;
+
+    // ========== BLOCKING TESTS ==========
+    info!("========== BLOCKING TRANSACTION TESTS ==========");
+    {
+        let mut i2c = I2c::new_blocking(
+            i2c_peri.reborrow(),
+            scl.reborrow(),
+            sda.reborrow(),
+            config,
+        );
+
+        info!("=== Test 1: Consecutive Writes (Should Merge) ===");
+        test_consecutive_writes_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 2: Consecutive Reads (Should Merge) ===");
+        test_consecutive_reads_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 3: Write then Read (RESTART) ===");
+        test_write_then_read_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 4: Read then Write (RESTART) ===");
+        test_read_then_write_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 5: Complex Mixed Sequence ===");
+        test_mixed_sequence_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 6: Single Operations ===");
+        test_single_operations_blocking(&mut i2c, slave_addr);
+
+        info!("Blocking tests OK");
+    }
+
+    Timer::after_millis(100).await;
+
+    // ========== ASYNC TESTS ==========
+    info!("========== ASYNC TRANSACTION TESTS (DMA) ==========");
+    {
+        let tx_dma = peri!(p, I2C_TX_DMA);
+        let rx_dma = peri!(p, I2C_RX_DMA);
+        let irq = irqs!(I2C);
 
-    info!("=== Test 1: Consecutive Writes (Should Merge) ===");
-    test_consecutive_writes(&mut i2c, slave_addr);
+        let mut i2c = I2c::new(i2c_peri, scl, sda, irq, tx_dma, rx_dma, config);
 
-    info!("=== Test 2: Consecutive Reads (Should Merge) ===");
-    test_consecutive_reads(&mut i2c, slave_addr);
+        info!("=== Test 1: Consecutive Writes (Should Merge) ===");
+        test_consecutive_writes_async(&mut i2c, slave_addr).await;
 
-    info!("=== Test 3: Write then Read (RESTART) ===");
-    test_write_then_read(&mut i2c, slave_addr);
+        info!("=== Test 2: Consecutive Reads (Should Merge) ===");
+        test_consecutive_reads_async(&mut i2c, slave_addr).await;
 
-    info!("=== Test 4: Read then Write (RESTART) ===");
-    test_read_then_write(&mut i2c, slave_addr);
+        info!("=== Test 3: Write then Read (RESTART) ===");
+        test_write_then_read_async(&mut i2c, slave_addr).await;
 
-    info!("=== Test 5: Complex Mixed Sequence ===");
-    test_mixed_sequence(&mut i2c, slave_addr);
+        info!("=== Test 4: Read then Write (RESTART) ===");
+        test_read_then_write_async(&mut i2c, slave_addr).await;
 
-    info!("=== Test 6: Single Operations ===");
-    test_single_operations(&mut i2c, slave_addr);
+        info!("=== Test 5: Complex Mixed Sequence ===");
+        test_mixed_sequence_async(&mut i2c, slave_addr).await;
 
-    info!("Test OK");
+        info!("=== Test 6: Single Operations ===");
+        test_single_operations_async(&mut i2c, slave_addr).await;
+
+        info!("Async tests OK");
+    }
+
+    info!("All tests OK");
     cortex_m::asm::bkpt();
 }
 
-fn test_consecutive_writes(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+fn test_consecutive_writes_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Expected on bus: START, ADDR+W, data1, data2, data3, STOP
     // NO intermediate RESTART/STOP between writes - they should be merged
     let data1 = [0x10, 0x11, 0x12];
@@ -95,7 +133,7 @@ fn test_consecutive_writes(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     }
 }
 
-fn test_consecutive_reads(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+fn test_consecutive_reads_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Expected on bus: START, ADDR+R, data1, data2, data3, NACK, STOP
     // NO intermediate RESTART/STOP between reads - they should be merged
     let mut buf1 = [0u8; 4];
@@ -122,7 +160,7 @@ fn test_consecutive_reads(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     }
 }
 
-fn test_write_then_read(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+fn test_write_then_read_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Expected: START, ADDR+W, data, RESTART, ADDR+R, data, NACK, STOP
     let write_data = [0xAA, 0xBB];
     let mut read_buf = [0u8; 4];
@@ -142,7 +180,7 @@ fn test_write_then_read(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     }
 }
 
-fn test_read_then_write(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+fn test_read_then_write_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Expected: START, ADDR+R, data, NACK, RESTART, ADDR+W, data, STOP
     let mut read_buf = [0u8; 3];
     let write_data = [0xCC, 0xDD, 0xEE];
@@ -162,7 +200,7 @@ fn test_read_then_write(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     }
 }
 
-fn test_mixed_sequence(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+fn test_mixed_sequence_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Complex: W, W, R, R, W, R
     // Groups: [W,W] RESTART [R,R] RESTART [W] RESTART [R]
     let w1 = [0x01, 0x02];
@@ -193,7 +231,7 @@ fn test_mixed_sequence(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     }
 }
 
-fn test_single_operations(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+fn test_single_operations_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Test single write
     let write_data = [0xFF];
     let mut ops = [Operation::Write(&write_data)];
@@ -218,3 +256,143 @@ fn test_single_operations(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
         }
     }
 }
+
+// ==================== ASYNC TEST FUNCTIONS ====================
+
+async fn test_consecutive_writes_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let data1 = [0x10, 0x11, 0x12];
+    let data2 = [0x20, 0x21];
+    let data3 = [0x30, 0x31, 0x32, 0x33];
+
+    let mut ops = [
+        Operation::Write(&data1),
+        Operation::Write(&data2),
+        Operation::Write(&data3),
+    ];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => info!("✓ Consecutive writes succeeded (merged 9 bytes)"),
+        Err(e) => {
+            error!("✗ Consecutive writes failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive writes");
+        }
+    }
+}
+
+async fn test_consecutive_reads_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let mut buf1 = [0u8; 4];
+    let mut buf2 = [0u8; 3];
+    let mut buf3 = [0u8; 2];
+
+    let mut ops = [
+        Operation::Read(&mut buf1),
+        Operation::Read(&mut buf2),
+        Operation::Read(&mut buf3),
+    ];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Consecutive reads succeeded (merged 9 bytes)");
+            info!("  buf1: {:02x}", buf1);
+            info!("  buf2: {:02x}", buf2);
+            info!("  buf3: {:02x}", buf3);
+        }
+        Err(e) => {
+            error!("✗ Consecutive reads failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive reads");
+        }
+    }
+}
+
+async fn test_write_then_read_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let write_data = [0xAA, 0xBB];
+    let mut read_buf = [0u8; 4];
+
+    let mut ops = [Operation::Write(&write_data), Operation::Read(&mut read_buf)];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Write-then-read succeeded with RESTART");
+            info!("  Written: {:02x}", write_data);
+            info!("  Read: {:02x}", read_buf);
+        }
+        Err(e) => {
+            error!("✗ Write-then-read failed: {:?}", e);
+            defmt::panic!("Test failed: write-then-read");
+        }
+    }
+}
+
+async fn test_read_then_write_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let mut read_buf = [0u8; 3];
+    let write_data = [0xCC, 0xDD, 0xEE];
+
+    let mut ops = [Operation::Read(&mut read_buf), Operation::Write(&write_data)];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Read-then-write succeeded with RESTART");
+            info!("  Read: {:02x}", read_buf);
+            info!("  Written: {:02x}", write_data);
+        }
+        Err(e) => {
+            error!("✗ Read-then-write failed: {:?}", e);
+            defmt::panic!("Test failed: read-then-write");
+        }
+    }
+}
+
+async fn test_mixed_sequence_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let w1 = [0x01, 0x02];
+    let w2 = [0x03, 0x04];
+    let mut r1 = [0u8; 2];
+    let mut r2 = [0u8; 2];
+    let w3 = [0x05];
+    let mut r3 = [0u8; 1];
+
+    let mut ops = [
+        Operation::Write(&w1),
+        Operation::Write(&w2),
+        Operation::Read(&mut r1),
+        Operation::Read(&mut r2),
+        Operation::Write(&w3),
+        Operation::Read(&mut r3),
+    ];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Mixed sequence succeeded");
+            info!("  Groups: [W4] RESTART [R4] RESTART [W1] RESTART [R1]");
+        }
+        Err(e) => {
+            error!("✗ Mixed sequence failed: {:?}", e);
+            defmt::panic!("Test failed: mixed sequence");
+        }
+    }
+}
+
+async fn test_single_operations_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    // Test single write
+    let write_data = [0xFF];
+    let mut ops = [Operation::Write(&write_data)];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => info!("✓ Single write succeeded"),
+        Err(e) => {
+            error!("✗ Single write failed: {:?}", e);
+            defmt::panic!("Test failed: single write");
+        }
+    }
+
+    // Test single read
+    let mut read_buf = [0u8; 1];
+    let mut ops = [Operation::Read(&mut read_buf)];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => info!("✓ Single read succeeded, data: 0x{:02x}", read_buf[0]),
+        Err(e) => {
+            error!("✗ Single read failed: {:?}", e);
+            defmt::panic!("Test failed: single read");
+        }
+    }
+}
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 07b667ade..de06cb267 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -109,7 +109,7 @@ define_peris!(
 define_peris!(
     UART = USART1, UART_TX = PA9, UART_RX = PA10, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
-    I2C = I2C1, I2C_SCL = PB8, I2C_SDA = PB9,
+    I2C = I2C1, I2C_SCL = PB8, I2C_SDA = PB9, I2C_TX_DMA = DMA1_CH6, I2C_RX_DMA = DMA1_CH7,
     @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
     @irq I2C = {I2C1 => embassy_stm32::i2c::EventInterruptHandler<embassy_stm32::peripherals::I2C1>, embassy_stm32::i2c::ErrorInterruptHandler<embassy_stm32::peripherals::I2C1>;},
 );