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authorxoviat <[email protected]>2023-10-17 01:05:18 +0000
committerGitHub <[email protected]>2023-10-17 01:05:18 +0000
commit683d5c30669bbb788e60ee3dd31ce30ba14c2d69 (patch)
tree525e40103da60e5c1664897a472ae602f65d09ae /tests
parent3e3317e8bd4a0c11655fb48a4bcff77791c105bc (diff)
parenta3574e519ad191c3c4c49fe9779a0a71d61cae3b (diff)
Merge pull request #2077 from xoviat/rcc
stm32: update metapac
Diffstat (limited to 'tests')
-rw-r--r--tests/stm32/src/common.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 6dc1b3002..a802cdfcf 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -290,7 +290,7 @@ pub fn config() -> Config {
290 config.rcc.mux = ClockSrc::PLL; 290 config.rcc.mux = ClockSrc::PLL;
291 config.rcc.hsi16 = true; 291 config.rcc.hsi16 = true;
292 config.rcc.pll = Some(Pll { 292 config.rcc.pll = Some(Pll {
293 source: PLLSource::HSI16, 293 source: PLLSource::HSI,
294 prediv: PllPreDiv::DIV1, 294 prediv: PllPreDiv::DIV1,
295 mul: PllMul::MUL18, 295 mul: PllMul::MUL18,
296 divp: None, 296 divp: None,