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authorLachezar Lechev <[email protected]>2023-03-26 18:14:17 +0300
committerLachezar Lechev <[email protected]>2023-03-26 18:14:17 +0300
commit7be63b3468f72fc684267c90093a00e77cff1bdc (patch)
treee0d3ba0505dd665d14460b14fc016b3d055bd1d1 /tests
parentcd2f28d2abb5b66981b7fdbb32566e6b942c7a54 (diff)
fix: spi transfer bug and additions to test
Signed-off-by: Lachezar Lechev <[email protected]>
Diffstat (limited to 'tests')
-rw-r--r--tests/rp/src/bin/spi_async.rs26
1 files changed, 23 insertions, 3 deletions
diff --git a/tests/rp/src/bin/spi_async.rs b/tests/rp/src/bin/spi_async.rs
index e3fe6e84c..2e22c9de7 100644
--- a/tests/rp/src/bin/spi_async.rs
+++ b/tests/rp/src/bin/spi_async.rs
@@ -33,9 +33,11 @@ async fn main(_spawner: Spawner) {
33 { 33 {
34 let tx_buf = [7_u8, 8, 9, 10, 11, 12]; 34 let tx_buf = [7_u8, 8, 9, 10, 11, 12];
35 35
36 let mut rx_buf = [0_u8, 3]; 36 let mut rx_buf = [0_u8; 3];
37 spi.transfer(&mut rx_buf, &tx_buf).await.unwrap(); 37 spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
38 assert_eq!(rx_buf, tx_buf[..3]); 38 assert_eq!(rx_buf, tx_buf[..3]);
39
40 defmt::info!("tx > rx buffer - OK");
39 } 41 }
40 42
41 // we make sure to that clearing FIFO works after the uneven buffers 43 // we make sure to that clearing FIFO works after the uneven buffers
@@ -45,18 +47,36 @@ async fn main(_spawner: Spawner) {
45 let tx_buf = [13_u8, 14, 15, 16, 17, 18]; 47 let tx_buf = [13_u8, 14, 15, 16, 17, 18];
46 let mut rx_buf = [0_u8; 6]; 48 let mut rx_buf = [0_u8; 6];
47 spi.transfer(&mut rx_buf, &tx_buf).await.unwrap(); 49 spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
48
49 assert_eq!(rx_buf, tx_buf); 50 assert_eq!(rx_buf, tx_buf);
51
52 defmt::info!("buffer rx length == tx length - OK");
50 } 53 }
51 54
52 // rx > tx buffer 55 // rx > tx buffer
53 { 56 {
54 let tx_buf = [19_u8, 20, 21]; 57 let tx_buf = [19_u8, 20, 21];
55 let mut rx_buf = [0_u8; 6]; 58 let mut rx_buf = [0_u8; 6];
59
60 // we should have written dummy data to tx buffer to sync clock.
56 spi.transfer(&mut rx_buf, &tx_buf).await.unwrap(); 61 spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
57 62
58 assert_eq!(rx_buf[..3], tx_buf, "only the first 3 TX bytes should have been received in the RX buffer"); 63 assert_eq!(
64 rx_buf[..3],
65 tx_buf,
66 "only the first 3 TX bytes should have been received in the RX buffer"
67 );
59 assert_eq!(rx_buf[3..], [0, 0, 0], "the rest of the RX bytes should be empty"); 68 assert_eq!(rx_buf[3..], [0, 0, 0], "the rest of the RX bytes should be empty");
69 defmt::info!("buffer rx length > tx length - OK");
70 }
71
72 // equal rx & tx buffers
73 {
74 let tx_buf = [22_u8, 23, 24, 25, 26, 27];
75 let mut rx_buf = [0_u8; 6];
76 spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
77
78 assert_eq!(rx_buf, tx_buf);
79 defmt::info!("buffer rx length = tx length - OK");
60 } 80 }
61 81
62 info!("Test OK"); 82 info!("Test OK");