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-rw-r--r--embassy-net-adin1110/Cargo.toml5
-rw-r--r--embassy-net-adin1110/src/fmt.rs254
-rw-r--r--embassy-net-adin1110/src/lib.rs101
-rw-r--r--embassy-net-adin1110/src/regs.rs14
4 files changed, 308 insertions, 66 deletions
diff --git a/embassy-net-adin1110/Cargo.toml b/embassy-net-adin1110/Cargo.toml
index e74fb7cd4..c13f10187 100644
--- a/embassy-net-adin1110/Cargo.toml
+++ b/embassy-net-adin1110/Cargo.toml
@@ -21,7 +21,6 @@ embassy-time = { version = "0.1.0" }
21embassy-futures = { version = "0.1.0", path = "../embassy-futures" } 21embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
22bitfield = "0.14.0" 22bitfield = "0.14.0"
23 23
24
25[dev-dependencies] 24[dev-dependencies]
26# reenable when https://github.com/dbrgn/embedded-hal-mock/pull/86 is merged. 25# reenable when https://github.com/dbrgn/embedded-hal-mock/pull/86 is merged.
27#embedded-hal-mock = { git = "https://github.com/dbrgn/embedded-hal-mock", branch = "1-alpha", features = ["embedded-hal-async", "eh1"] }] } 26#embedded-hal-mock = { git = "https://github.com/dbrgn/embedded-hal-mock", branch = "1-alpha", features = ["embedded-hal-async", "eh1"] }] }
@@ -33,9 +32,11 @@ futures-test = "0.3.17"
33 32
34[features] 33[features]
35default = [ ] 34default = [ ]
36defmt = [ "dep:defmt" ] 35defmt = [ "dep:defmt", "embedded-hal-1/defmt-03" ]
36log = ["dep:log"]
37 37
38[package.metadata.embassy_docs] 38[package.metadata.embassy_docs]
39src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-adin1110-v$VERSION/embassy-net-adin1110/src/" 39src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-adin1110-v$VERSION/embassy-net-adin1110/src/"
40src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-adin1110/src/" 40src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-adin1110/src/"
41target = "thumbv7em-none-eabi" 41target = "thumbv7em-none-eabi"
42features = ["defmt"]
diff --git a/embassy-net-adin1110/src/fmt.rs b/embassy-net-adin1110/src/fmt.rs
new file mode 100644
index 000000000..12737c690
--- /dev/null
+++ b/embassy-net-adin1110/src/fmt.rs
@@ -0,0 +1,254 @@
1#![macro_use]
2#![allow(unused_macros)]
3
4use core::fmt::{Debug, Display, LowerHex};
5
6#[cfg(all(feature = "defmt", feature = "log"))]
7compile_error!("You may not enable both `defmt` and `log` features.");
8
9macro_rules! assert {
10 ($($x:tt)*) => {
11 {
12 #[cfg(not(feature = "defmt"))]
13 ::core::assert!($($x)*);
14 #[cfg(feature = "defmt")]
15 ::defmt::assert!($($x)*);
16 }
17 };
18}
19
20macro_rules! assert_eq {
21 ($($x:tt)*) => {
22 {
23 #[cfg(not(feature = "defmt"))]
24 ::core::assert_eq!($($x)*);
25 #[cfg(feature = "defmt")]
26 ::defmt::assert_eq!($($x)*);
27 }
28 };
29}
30
31macro_rules! assert_ne {
32 ($($x:tt)*) => {
33 {
34 #[cfg(not(feature = "defmt"))]
35 ::core::assert_ne!($($x)*);
36 #[cfg(feature = "defmt")]
37 ::defmt::assert_ne!($($x)*);
38 }
39 };
40}
41
42macro_rules! debug_assert {
43 ($($x:tt)*) => {
44 {
45 #[cfg(not(feature = "defmt"))]
46 ::core::debug_assert!($($x)*);
47 #[cfg(feature = "defmt")]
48 ::defmt::debug_assert!($($x)*);
49 }
50 };
51}
52
53macro_rules! debug_assert_eq {
54 ($($x:tt)*) => {
55 {
56 #[cfg(not(feature = "defmt"))]
57 ::core::debug_assert_eq!($($x)*);
58 #[cfg(feature = "defmt")]
59 ::defmt::debug_assert_eq!($($x)*);
60 }
61 };
62}
63
64macro_rules! debug_assert_ne {
65 ($($x:tt)*) => {
66 {
67 #[cfg(not(feature = "defmt"))]
68 ::core::debug_assert_ne!($($x)*);
69 #[cfg(feature = "defmt")]
70 ::defmt::debug_assert_ne!($($x)*);
71 }
72 };
73}
74
75macro_rules! todo {
76 ($($x:tt)*) => {
77 {
78 #[cfg(not(feature = "defmt"))]
79 ::core::todo!($($x)*);
80 #[cfg(feature = "defmt")]
81 ::defmt::todo!($($x)*);
82 }
83 };
84}
85
86macro_rules! unreachable {
87 ($($x:tt)*) => {
88 {
89 #[cfg(not(feature = "defmt"))]
90 ::core::unreachable!($($x)*);
91 #[cfg(feature = "defmt")]
92 ::defmt::unreachable!($($x)*);
93 }
94 };
95}
96
97macro_rules! panic {
98 ($($x:tt)*) => {
99 {
100 #[cfg(not(feature = "defmt"))]
101 ::core::panic!($($x)*);
102 #[cfg(feature = "defmt")]
103 ::defmt::panic!($($x)*);
104 }
105 };
106}
107
108macro_rules! trace {
109 ($s:literal $(, $x:expr)* $(,)?) => {
110 {
111 #[cfg(feature = "log")]
112 ::log::trace!($s $(, $x)*);
113 #[cfg(feature = "defmt")]
114 ::defmt::trace!($s $(, $x)*);
115 #[cfg(not(any(feature = "log", feature="defmt")))]
116 let _ignored = ($( & $x ),*);
117 }
118 };
119}
120
121macro_rules! debug {
122 ($s:literal $(, $x:expr)* $(,)?) => {
123 {
124 #[cfg(feature = "log")]
125 ::log::debug!($s $(, $x)*);
126 #[cfg(feature = "defmt")]
127 ::defmt::debug!($s $(, $x)*);
128 #[cfg(not(any(feature = "log", feature="defmt")))]
129 let _ignored = ($( & $x ),*);
130 }
131 };
132}
133
134macro_rules! info {
135 ($s:literal $(, $x:expr)* $(,)?) => {
136 {
137 #[cfg(feature = "log")]
138 ::log::info!($s $(, $x)*);
139 #[cfg(feature = "defmt")]
140 ::defmt::info!($s $(, $x)*);
141 #[cfg(not(any(feature = "log", feature="defmt")))]
142 let _ignored = ($( & $x ),*);
143 }
144 };
145}
146
147macro_rules! warn {
148 ($s:literal $(, $x:expr)* $(,)?) => {
149 {
150 #[cfg(feature = "log")]
151 ::log::warn!($s $(, $x)*);
152 #[cfg(feature = "defmt")]
153 ::defmt::warn!($s $(, $x)*);
154 #[cfg(not(any(feature = "log", feature="defmt")))]
155 let _ignored = ($( & $x ),*);
156 }
157 };
158}
159
160macro_rules! error {
161 ($s:literal $(, $x:expr)* $(,)?) => {
162 {
163 #[cfg(feature = "log")]
164 ::log::error!($s $(, $x)*);
165 #[cfg(feature = "defmt")]
166 ::defmt::error!($s $(, $x)*);
167 #[cfg(not(any(feature = "log", feature="defmt")))]
168 let _ignored = ($( & $x ),*);
169 }
170 };
171}
172
173#[cfg(feature = "defmt")]
174macro_rules! unwrap {
175 ($($x:tt)*) => {
176 ::defmt::unwrap!($($x)*)
177 };
178}
179
180#[cfg(not(feature = "defmt"))]
181macro_rules! unwrap {
182 ($arg:expr) => {
183 match $crate::fmt::Try::into_result($arg) {
184 ::core::result::Result::Ok(t) => t,
185 ::core::result::Result::Err(e) => {
186 ::core::panic!("unwrap of `{}` failed: {:?}", ::core::stringify!($arg), e);
187 }
188 }
189 };
190 ($arg:expr, $($msg:expr),+ $(,)? ) => {
191 match $crate::fmt::Try::into_result($arg) {
192 ::core::result::Result::Ok(t) => t,
193 ::core::result::Result::Err(e) => {
194 ::core::panic!("unwrap of `{}` failed: {}: {:?}", ::core::stringify!($arg), ::core::format_args!($($msg,)*), e);
195 }
196 }
197 }
198}
199
200#[derive(Debug, Copy, Clone, Eq, PartialEq)]
201pub struct NoneError;
202
203pub trait Try {
204 type Ok;
205 type Error;
206 fn into_result(self) -> Result<Self::Ok, Self::Error>;
207}
208
209impl<T> Try for Option<T> {
210 type Ok = T;
211 type Error = NoneError;
212
213 #[inline]
214 fn into_result(self) -> Result<T, NoneError> {
215 self.ok_or(NoneError)
216 }
217}
218
219impl<T, E> Try for Result<T, E> {
220 type Ok = T;
221 type Error = E;
222
223 #[inline]
224 fn into_result(self) -> Self {
225 self
226 }
227}
228
229pub struct Bytes<'a>(pub &'a [u8]);
230
231impl<'a> Debug for Bytes<'a> {
232 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
233 write!(f, "{:#02x?}", self.0)
234 }
235}
236
237impl<'a> Display for Bytes<'a> {
238 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
239 write!(f, "{:#02x?}", self.0)
240 }
241}
242
243impl<'a> LowerHex for Bytes<'a> {
244 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
245 write!(f, "{:#02x?}", self.0)
246 }
247}
248
249#[cfg(feature = "defmt")]
250impl<'a> defmt::Format for Bytes<'a> {
251 fn format(&self, fmt: defmt::Formatter) {
252 defmt::write!(fmt, "{:02x}", self.0)
253 }
254}
diff --git a/embassy-net-adin1110/src/lib.rs b/embassy-net-adin1110/src/lib.rs
index 8d73e024f..4af054aea 100644
--- a/embassy-net-adin1110/src/lib.rs
+++ b/embassy-net-adin1110/src/lib.rs
@@ -6,6 +6,9 @@
6#![allow(clippy::missing_panics_doc)] 6#![allow(clippy::missing_panics_doc)]
7#![doc = include_str!("../README.md")] 7#![doc = include_str!("../README.md")]
8 8
9// must go first!
10mod fmt;
11
9mod crc32; 12mod crc32;
10mod crc8; 13mod crc8;
11mod mdio; 14mod mdio;
@@ -20,12 +23,13 @@ use embassy_net_driver_channel as ch;
20use embassy_time::{Duration, Timer}; 23use embassy_time::{Duration, Timer};
21use embedded_hal_1::digital::OutputPin; 24use embedded_hal_1::digital::OutputPin;
22use embedded_hal_async::digital::Wait; 25use embedded_hal_async::digital::Wait;
23use embedded_hal_async::spi::{Operation, SpiDevice}; 26use embedded_hal_async::spi::{Error, Operation, SpiDevice};
24use heapless::Vec; 27use heapless::Vec;
25pub use mdio::MdioBus; 28pub use mdio::MdioBus;
26pub use phy::{Phy10BaseT1x, RegsC22, RegsC45}; 29pub use phy::{Phy10BaseT1x, RegsC22, RegsC45};
27pub use regs::{Config0, Config2, SpiRegisters as sr, Status0, Status1}; 30pub use regs::{Config0, Config2, SpiRegisters as sr, Status0, Status1};
28 31
32use crate::fmt::Bytes;
29use crate::regs::{LedCntrl, LedFunc, LedPol, LedPolarity, SpiHeader}; 33use crate::regs::{LedCntrl, LedFunc, LedPol, LedPolarity, SpiHeader};
30 34
31pub const PHYID: u32 = 0x0283_BC91; 35pub const PHYID: u32 = 0x0283_BC91;
@@ -153,8 +157,7 @@ impl<SPI: SpiDevice> ADIN1110<SPI> {
153 157
154 let value = u32::from_be_bytes(rx_buf[0..4].try_into().unwrap()); 158 let value = u32::from_be_bytes(rx_buf[0..4].try_into().unwrap());
155 159
156 #[cfg(feature = "defmt")] 160 trace!("REG Read {} = {:08x} SPI {}", reg, value, Bytes(&tx_buf));
157 defmt::trace!("REG Read {} = {:08x} SPI {:02x}", reg, value, &tx_buf);
158 161
159 Ok(value) 162 Ok(value)
160 } 163 }
@@ -181,8 +184,7 @@ impl<SPI: SpiDevice> ADIN1110<SPI> {
181 let _ = tx_buf.push(crc8(val.as_slice())); 184 let _ = tx_buf.push(crc8(val.as_slice()));
182 } 185 }
183 186
184 #[cfg(feature = "defmt")] 187 trace!("REG Write {} = {:08x} SPI {}", reg, value, Bytes(&tx_buf));
185 defmt::trace!("REG Write {} = {:08x} SPI {:02x}", reg, value, &tx_buf);
186 188
187 self.spi.write(&tx_buf).await.map_err(AdinError::Spi) 189 self.spi.write(&tx_buf).await.map_err(AdinError::Spi)
188 } 190 }
@@ -219,8 +221,7 @@ impl<SPI: SpiDevice> ADIN1110<SPI> {
219 let packet_size = fifo_frame_size - FRAME_HEADER_LEN - FCS_LEN; 221 let packet_size = fifo_frame_size - FRAME_HEADER_LEN - FCS_LEN;
220 222
221 if packet_size > frame.len() { 223 if packet_size > frame.len() {
222 #[cfg(feature = "defmt")] 224 trace!("MAX: {} WANT: {}", frame.len(), packet_size);
223 defmt::trace!("MAX: {} WANT: {}", frame.len(), packet_size);
224 return Err(AdinError::PACKET_TOO_BIG); 225 return Err(AdinError::PACKET_TOO_BIG);
225 } 226 }
226 227
@@ -333,14 +334,13 @@ impl<SPI: SpiDevice> ADIN1110<SPI> {
333 334
334 self.write_reg(sr::TX_FSIZE, send_len).await?; 335 self.write_reg(sr::TX_FSIZE, send_len).await?;
335 336
336 #[cfg(feature = "defmt")] 337 trace!(
337 defmt::trace!( 338 "TX: hdr {} [{}] {}-{}-{} SIZE: {}",
338 "TX: hdr {} [{}] {:02x}-{:02x}-{:02x} SIZE: {}",
339 head_data.len(), 339 head_data.len(),
340 frame.len(), 340 frame.len(),
341 head_data.as_slice(), 341 Bytes(head_data.as_slice()),
342 frame, 342 Bytes(frame),
343 tail_data.as_slice(), 343 Bytes(tail_data.as_slice()),
344 send_len, 344 send_len,
345 ); 345 );
346 346
@@ -445,16 +445,14 @@ impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
445 let (state_chan, mut rx_chan, mut tx_chan) = self.ch.split(); 445 let (state_chan, mut rx_chan, mut tx_chan) = self.ch.split();
446 446
447 loop { 447 loop {
448 #[cfg(feature = "defmt")] 448 debug!("Waiting for interrupts");
449 defmt::debug!("Waiting for interrupts");
450 match select(self.int.wait_for_low(), tx_chan.tx_buf()).await { 449 match select(self.int.wait_for_low(), tx_chan.tx_buf()).await {
451 Either::First(_) => { 450 Either::First(_) => {
452 let mut status1_clr = Status1(0); 451 let mut status1_clr = Status1(0);
453 let mut status1 = Status1(self.mac.read_reg(sr::STATUS1).await.unwrap()); 452 let mut status1 = Status1(self.mac.read_reg(sr::STATUS1).await.unwrap());
454 453
455 while status1.p1_rx_rdy() { 454 while status1.p1_rx_rdy() {
456 #[cfg(feature = "defmt")] 455 debug!("alloc RX packet buffer");
457 defmt::debug!("alloc RX packet buffer");
458 match select(rx_chan.rx_buf(), tx_chan.tx_buf()).await { 456 match select(rx_chan.rx_buf(), tx_chan.tx_buf()).await {
459 // Handle frames that needs to transmit from the wire. 457 // Handle frames that needs to transmit from the wire.
460 // Note: rx_chan.rx_buf() channel don´t accept new request 458 // Note: rx_chan.rx_buf() channel don´t accept new request
@@ -466,22 +464,18 @@ impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
466 } 464 }
467 Err(e) => match e { 465 Err(e) => match e {
468 AdinError::PACKET_TOO_BIG => { 466 AdinError::PACKET_TOO_BIG => {
469 #[cfg(feature = "defmt")] 467 error!("RX Packet too big, DROP");
470 defmt::error!("RX Packet too big, DROP");
471 self.mac.write_reg(sr::FIFO_CLR, 1).await.unwrap(); 468 self.mac.write_reg(sr::FIFO_CLR, 1).await.unwrap();
472 } 469 }
473 AdinError::PACKET_TOO_SMALL => { 470 AdinError::PACKET_TOO_SMALL => {
474 #[cfg(feature = "defmt")] 471 error!("RX Packet too small, DROP");
475 defmt::error!("RX Packet too small, DROP");
476 self.mac.write_reg(sr::FIFO_CLR, 1).await.unwrap(); 472 self.mac.write_reg(sr::FIFO_CLR, 1).await.unwrap();
477 } 473 }
478 AdinError::Spi(_) => { 474 AdinError::Spi(e) => {
479 #[cfg(feature = "defmt")] 475 error!("RX Spi error {}", e.kind());
480 defmt::error!("RX Spi error")
481 } 476 }
482 _ => { 477 _ => {
483 #[cfg(feature = "defmt")] 478 error!("RX Error");
484 defmt::error!("RX Error")
485 } 479 }
486 }, 480 },
487 }, 481 },
@@ -496,21 +490,18 @@ impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
496 490
497 let status0 = Status0(self.mac.read_reg(sr::STATUS0).await.unwrap()); 491 let status0 = Status0(self.mac.read_reg(sr::STATUS0).await.unwrap());
498 if status1.0 & !0x1b != 0 { 492 if status1.0 & !0x1b != 0 {
499 #[cfg(feature = "defmt")] 493 error!("SPE CHIP STATUS 0:{:08x} 1:{:08x}", status0.0, status1.0);
500 defmt::error!("SPE CHIP STATUS 0:{:08x} 1:{:08x}", status0.0, status1.0);
501 } 494 }
502 495
503 if status1.tx_rdy() { 496 if status1.tx_rdy() {
504 status1_clr.set_tx_rdy(true); 497 status1_clr.set_tx_rdy(true);
505 #[cfg(feature = "defmt")] 498 trace!("TX_DONE");
506 defmt::info!("TX_DONE");
507 } 499 }
508 500
509 if status1.link_change() { 501 if status1.link_change() {
510 let link = status1.p1_link_status(); 502 let link = status1.p1_link_status();
511 self.is_link_up = link; 503 self.is_link_up = link;
512 504
513 #[cfg(feature = "defmt")]
514 if link { 505 if link {
515 let link_status = self 506 let link_status = self
516 .mac 507 .mac
@@ -530,9 +521,9 @@ impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
530 .await 521 .await
531 .unwrap(); 522 .unwrap();
532 523
533 defmt::info!("LINK Changed: Link Up, Volt: {} V p-p, MSE: {:0004}", volt, mse); 524 info!("LINK Changed: Link Up, Volt: {} V p-p, MSE: {:0004}", volt, mse);
534 } else { 525 } else {
535 defmt::info!("LINK Changed: Link Down"); 526 info!("LINK Changed: Link Down");
536 } 527 }
537 528
538 state_chan.set_link_state(if link { LinkState::Up } else { LinkState::Down }); 529 state_chan.set_link_state(if link { LinkState::Up } else { LinkState::Down });
@@ -540,50 +531,42 @@ impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
540 } 531 }
541 532
542 if status1.tx_ecc_err() { 533 if status1.tx_ecc_err() {
543 #[cfg(feature = "defmt")] 534 error!("SPI TX_ECC_ERR error, CLEAR TX FIFO");
544 defmt::error!("SPI TX_ECC_ERR error, CLEAR TX FIFO");
545 self.mac.write_reg(sr::FIFO_CLR, 2).await.unwrap(); 535 self.mac.write_reg(sr::FIFO_CLR, 2).await.unwrap();
546 status1_clr.set_tx_ecc_err(true); 536 status1_clr.set_tx_ecc_err(true);
547 } 537 }
548 538
549 if status1.rx_ecc_err() { 539 if status1.rx_ecc_err() {
550 #[cfg(feature = "defmt")] 540 error!("SPI RX_ECC_ERR error");
551 defmt::error!("SPI RX_ECC_ERR error");
552 status1_clr.set_rx_ecc_err(true); 541 status1_clr.set_rx_ecc_err(true);
553 } 542 }
554 543
555 if status1.spi_err() { 544 if status1.spi_err() {
556 #[cfg(feature = "defmt")] 545 error!("SPI SPI_ERR CRC error");
557 defmt::error!("SPI SPI_ERR CRC error");
558 status1_clr.set_spi_err(true); 546 status1_clr.set_spi_err(true);
559 } 547 }
560 548
561 if status0.phyint() { 549 if status0.phyint() {
562 #[cfg_attr(not(feature = "defmt"), allow(unused_variables))]
563 let crsm_irq_st = self 550 let crsm_irq_st = self
564 .mac 551 .mac
565 .read_cl45(MDIO_PHY_ADDR, RegsC45::DA1E::CRSM_IRQ_STATUS.into()) 552 .read_cl45(MDIO_PHY_ADDR, RegsC45::DA1E::CRSM_IRQ_STATUS.into())
566 .await 553 .await
567 .unwrap(); 554 .unwrap();
568 555
569 #[cfg_attr(not(feature = "defmt"), allow(unused_variables))]
570 let phy_irq_st = self 556 let phy_irq_st = self
571 .mac 557 .mac
572 .read_cl45(MDIO_PHY_ADDR, RegsC45::DA1F::PHY_SYBSYS_IRQ_STATUS.into()) 558 .read_cl45(MDIO_PHY_ADDR, RegsC45::DA1F::PHY_SYBSYS_IRQ_STATUS.into())
573 .await 559 .await
574 .unwrap(); 560 .unwrap();
575 561
576 #[cfg(feature = "defmt")] 562 warn!(
577 defmt::warn!(
578 "SPE CHIP PHY CRSM_IRQ_STATUS {:04x} PHY_SUBSYS_IRQ_STATUS {:04x}", 563 "SPE CHIP PHY CRSM_IRQ_STATUS {:04x} PHY_SUBSYS_IRQ_STATUS {:04x}",
579 crsm_irq_st, 564 crsm_irq_st, phy_irq_st
580 phy_irq_st
581 ); 565 );
582 } 566 }
583 567
584 if status0.txfcse() { 568 if status0.txfcse() {
585 #[cfg(feature = "defmt")] 569 error!("Ethernet Frame FCS and calc FCS don't match!");
586 defmt::error!("SPE CHIP PHY TX Frame CRC error");
587 } 570 }
588 571
589 // Clear status0 572 // Clear status0
@@ -613,8 +596,7 @@ pub async fn new<const N_RX: usize, const N_TX: usize, SPI: SpiDevice, INT: Wait
613) -> (Device<'_>, Runner<'_, SPI, INT, RST>) { 596) -> (Device<'_>, Runner<'_, SPI, INT, RST>) {
614 use crate::regs::{IMask0, IMask1}; 597 use crate::regs::{IMask0, IMask1};
615 598
616 #[cfg(feature = "defmt")] 599 info!("INIT ADIN1110");
617 defmt::info!("INIT ADIN1110");
618 600
619 // Reset sequence 601 // Reset sequence
620 reset.set_low().unwrap(); 602 reset.set_low().unwrap();
@@ -634,23 +616,20 @@ pub async fn new<const N_RX: usize, const N_TX: usize, SPI: SpiDevice, INT: Wait
634 let id = mac.read_reg(sr::PHYID).await.unwrap(); 616 let id = mac.read_reg(sr::PHYID).await.unwrap();
635 assert_eq!(id, PHYID); 617 assert_eq!(id, PHYID);
636 618
637 #[cfg(feature = "defmt")] 619 debug!("SPE: CHIP MAC/ID: {:08x}", id);
638 defmt::debug!("SPE: CHIP MAC/ID: {:08x}", id);
639 620
640 #[cfg(feature = "defmt")] 621 #[cfg(any(feature = "defmt", feature = "log"))]
641 let adin_phy = Phy10BaseT1x::default(); 622 {
642 #[cfg(feature = "defmt")] 623 let adin_phy = Phy10BaseT1x::default();
643 let phy_id = adin_phy.get_id(&mut mac).await.unwrap(); 624 let phy_id = adin_phy.get_id(&mut mac).await.unwrap();
644 #[cfg(feature = "defmt")] 625 debug!("SPE: CHIP: PHY ID: {:08x}", phy_id);
645 defmt::debug!("SPE: CHIP: PHY ID: {:08x}", phy_id); 626 }
646 627
647 let mi_control = mac.read_cl22(MDIO_PHY_ADDR, RegsC22::CONTROL as u8).await.unwrap(); 628 let mi_control = mac.read_cl22(MDIO_PHY_ADDR, RegsC22::CONTROL as u8).await.unwrap();
648 #[cfg(feature = "defmt")] 629 debug!("SPE CHIP PHY MI_CONTROL {:04x}", mi_control);
649 defmt::println!("SPE CHIP PHY MI_CONTROL {:04x}", mi_control);
650 if mi_control & 0x0800 != 0 { 630 if mi_control & 0x0800 != 0 {
651 let val = mi_control & !0x0800; 631 let val = mi_control & !0x0800;
652 #[cfg(feature = "defmt")] 632 debug!("SPE CHIP PHY MI_CONTROL Disable PowerDown");
653 defmt::println!("SPE CHIP PHY MI_CONTROL Disable PowerDown");
654 mac.write_cl22(MDIO_PHY_ADDR, RegsC22::CONTROL as u8, val) 633 mac.write_cl22(MDIO_PHY_ADDR, RegsC22::CONTROL as u8, val)
655 .await 634 .await
656 .unwrap(); 635 .unwrap();
diff --git a/embassy-net-adin1110/src/regs.rs b/embassy-net-adin1110/src/regs.rs
index 46466c7d1..beaf9466e 100644
--- a/embassy-net-adin1110/src/regs.rs
+++ b/embassy-net-adin1110/src/regs.rs
@@ -1,3 +1,5 @@
1use core::fmt::{Debug, Display};
2
1use bitfield::{bitfield, bitfield_bitrange, bitfield_fields}; 3use bitfield::{bitfield, bitfield_bitrange, bitfield_fields};
2 4
3#[allow(non_camel_case_types)] 5#[allow(non_camel_case_types)]
@@ -34,6 +36,12 @@ pub enum SpiRegisters {
34 RX = 0x91, 36 RX = 0x91,
35} 37}
36 38
39impl Display for SpiRegisters {
40 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
41 write!(f, "{self:?}")
42 }
43}
44
37impl From<SpiRegisters> for u16 { 45impl From<SpiRegisters> for u16 {
38 fn from(val: SpiRegisters) -> Self { 46 fn from(val: SpiRegisters) -> Self {
39 val as u16 47 val as u16
@@ -68,7 +76,7 @@ impl From<u16> for SpiRegisters {
68 0x73 => Self::ADDR_MSK_UPR1, 76 0x73 => Self::ADDR_MSK_UPR1,
69 0x90 => Self::RX_FSIZE, 77 0x90 => Self::RX_FSIZE,
70 0x91 => Self::RX, 78 0x91 => Self::RX,
71 e => panic!("Unknown value {e}"), 79 e => panic!("Unknown value {}", e),
72 } 80 }
73 } 81 }
74} 82}
@@ -313,7 +321,7 @@ impl From<u8> for LedFunc {
313 26 => LedFunc::Clk25Ref, 321 26 => LedFunc::Clk25Ref,
314 27 => LedFunc::TxTCLK, 322 27 => LedFunc::TxTCLK,
315 28 => LedFunc::Clk120MHz, 323 28 => LedFunc::Clk120MHz,
316 e => panic!("Invalid value {e}"), 324 e => panic!("Invalid value {}", e),
317 } 325 }
318 } 326 }
319} 327}
@@ -369,7 +377,7 @@ impl From<u8> for LedPol {
369 0 => LedPol::AutoSense, 377 0 => LedPol::AutoSense,
370 1 => LedPol::ActiveHigh, 378 1 => LedPol::ActiveHigh,
371 2 => LedPol::ActiveLow, 379 2 => LedPol::ActiveLow,
372 e => panic!("Invalid value {e}"), 380 e => panic!("Invalid value {}", e),
373 } 381 }
374 } 382 }
375} 383}
generated by cgit (git 2.34.1) at 2026-04-05 18:52:34 +0000