4 files changed, 18 insertions, 9 deletions

diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index a6af1175a..da432f6ce 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -208,7 +208,7 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().enable();
         T::regs().convert();
 
-        unsafe { *T::regs().data() }
+        unsafe { core::ptr::read_volatile(T::regs().data()) }
     }
 
     #[cfg(any(adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs
index e62de0454..b5fa3c897 100644
--- a/embassy-stm32/src/hsem/mod.rs
+++ b/embassy-stm32/src/hsem/mod.rs
@@ -148,6 +148,7 @@ impl<'a, T: Instance> HardwareSemaphoreChannel<'a, T> {
     /// The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to
     /// check if the lock has been successful, carried out from the HSEM_Rx register.
     pub async fn lock(&mut self, process_id: u8) -> HardwareSemaphoreMutex<'a, T> {
+        let _scoped_block_stop = T::RCC_INFO.block_stop();
         let core_id = CoreId::current();
 
         poll_fn(|cx| {
@@ -241,7 +242,7 @@ impl<T: Instance> HardwareSemaphore<T> {
         _peripheral: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, HardwareSemaphoreInterruptHandler<T>> + 'd,
     ) -> Self {
-        rcc::enable_and_reset::<T>();
+        rcc::enable_and_reset_without_stop::<T>();
 
         HardwareSemaphore { _type: PhantomData }
     }
diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs
index 183986fdc..74ce0b29e 100644
--- a/embassy-stm32/src/ipcc.rs
+++ b/embassy-stm32/src/ipcc.rs
@@ -10,6 +10,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::interrupt::typelevel::Interrupt;
 use crate::peripherals::IPCC;
+use crate::rcc::SealedRccPeripheral;
 use crate::{interrupt, rcc};
 
 /// Interrupt handler.
@@ -84,6 +85,7 @@ impl<'a> IpccTxChannel<'a> {
 
     /// Send data to an IPCC channel. The closure is called to write the data when appropriate.
     pub async fn send(&mut self, f: impl FnOnce()) {
+        let _scoped_block_stop = IPCC::RCC_INFO.block_stop();
         let regs = IPCC::regs();
 
         self.flush().await;
@@ -98,6 +100,7 @@ impl<'a> IpccTxChannel<'a> {
 
     /// Wait for the tx channel to become clear
     pub async fn flush(&mut self) {
+        let _scoped_block_stop = IPCC::RCC_INFO.block_stop();
         let regs = IPCC::regs();
 
         // This is a race, but is nice for debugging
@@ -143,6 +146,7 @@ impl<'a> IpccRxChannel<'a> {
 
     /// Receive data from an IPCC channel. The closure is called to read the data when appropriate.
     pub async fn receive<R>(&mut self, mut f: impl FnMut() -> Option<R>) -> R {
+        let _scoped_block_stop = IPCC::RCC_INFO.block_stop();
         let regs = IPCC::regs();
 
         loop {
@@ -220,14 +224,11 @@ impl Ipcc {
         + 'd,
         _config: Config,
     ) -> Self {
-        rcc::enable_and_reset::<IPCC>();
+        rcc::enable_and_reset_without_stop::<IPCC>();
         IPCC::set_cpu2(true);
 
-        #[cfg(stm32wb)]
-        // DO NOT REMOVE THIS UNLESS YOU FIX THE EXAMPLES AND TEST FIRST
-        crate::pac::RCC
-            .csr()
-            .modify(|w| w.set_rfwkpsel(stm32_metapac::rcc::vals::Rfwkpsel::LSE));
+        // Verify rfwkpsel is set
+        let _ = IPCC::frequency();
 
         let regs = IPCC::regs();
 
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index 2e1cbd702..0d668103c 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -135,7 +135,14 @@ pub const WPAN_DEFAULT: Config = Config {
     apb1_pre: APBPrescaler::DIV1,
     apb2_pre: APBPrescaler::DIV1,
 
-    mux: super::mux::ClockMux::default(),
+    mux: {
+        use crate::pac::rcc::vals::Rfwkpsel;
+
+        let mut mux = super::mux::ClockMux::default();
+
+        mux.rfwkpsel = Rfwkpsel::LSE;
+        mux
+    },
 };
 
 fn msi_enable(range: MSIRange) {