2 files changed, 8 insertions, 8 deletions

diff --git a/embassy-stm32/src/rcc/f2.rs b/embassy-stm32/src/rcc/f2.rs
index 7074d7c3a..7e5992bba 100644
--- a/embassy-stm32/src/rcc/f2.rs
+++ b/embassy-stm32/src/rcc/f2.rs
@@ -424,10 +424,10 @@ pub(crate) unsafe fn init(config: Config) {
 
     let pll_src_freq = match config.pll_mux {
         PLLSrc::HSE => {
-            config
+            let hse_config = config
                 .hse
-                .expect("HSE must be configured to be used as PLL input")
-                .frequency
+                .unwrap_or_else(|| panic!("HSE must be configured to be used as PLL input"));
+            hse_config.frequency
         }
         PLLSrc::HSI => HSI,
     };
@@ -458,7 +458,7 @@ pub(crate) unsafe fn init(config: Config) {
         ClockSrc::HSE => {
             let hse_config = config
                 .hse
-                .expect("HSE must be configured to be used as system clock");
+                .unwrap_or_else(|| panic!("HSE must be configured to be used as PLL input"));
             (hse_config.frequency, Sw::HSE)
         }
         ClockSrc::PLL => {
@@ -475,7 +475,7 @@ pub(crate) unsafe fn init(config: Config) {
     // Reference: STM32F215xx/217xx datasheet Table 13. General operating conditions
     assert!(ahb_freq <= Hertz(120_000_000));
 
-    let flash_ws = config.voltage.wait_states(ahb_freq).expect("Invalid HCLK");
+    let flash_ws = unwrap!(config.voltage.wait_states(ahb_freq));
     FLASH.acr().modify(|w| w.set_latency(flash_ws));
 
     RCC.cfgr().modify(|w| {
diff --git a/examples/stm32f2/src/bin/pll.rs b/examples/stm32f2/src/bin/pll.rs
index 348a583ab..4bd74f0bd 100644
--- a/examples/stm32f2/src/bin/pll.rs
+++ b/examples/stm32f2/src/bin/pll.rs
@@ -30,13 +30,13 @@ fn config() -> Config {
     config.rcc.pll_mux = PLLSrc::HSE;
     config.rcc.pll = PLLConfig {
         // 8 MHz clock source / 8 = 1 MHz PLL input
-        pre_div: PLLPreDiv::try_from(8).unwrap(),
+        pre_div: unwrap!(PLLPreDiv::try_from(8)),
         // 1 MHz PLL input * 240 = 240 MHz PLL VCO
-        mul: PLLMul::try_from(240).unwrap(),
+        mul: unwrap!(PLLMul::try_from(240)),
         // 240 MHz PLL VCO / 2 = 120 MHz main PLL output
         main_div: PLLMainDiv::Div2,
         // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
-        pll48_div: PLL48Div::try_from(5).unwrap(),
+        pll48_div: unwrap!(PLL48Div::try_from(5)),
     };
     // System clock comes from PLL (= the 120 MHz main PLL output)
     config.rcc.mux = ClockSrc::PLL;