1 files changed, 25 insertions, 11 deletions

diff --git a/embassy-mspm0/src/gpio.rs b/embassy-mspm0/src/gpio.rs
index d5fd36dbf..709102c59 100644
--- a/embassy-mspm0/src/gpio.rs
+++ b/embassy-mspm0/src/gpio.rs
@@ -5,12 +5,12 @@ use core::future::Future;
 use core::pin::Pin as FuturePin;
 use core::task::{Context, Poll};
 
-use embassy_hal_internal::{impl_peripheral, Peri, PeripheralType};
+use embassy_hal_internal::{Peri, PeripheralType, impl_peripheral};
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::pac::gpio::vals::*;
 use crate::pac::gpio::{self};
-#[cfg(all(feature = "rt", any(mspm0c110x, mspm0c1105_c1106, mspm0l110x)))]
+#[cfg(all(feature = "rt", any(gpioa_interrupt, gpiob_interrupt)))]
 use crate::pac::interrupt;
 use crate::pac::{self};
 
@@ -156,7 +156,12 @@ impl<'d> Flex<'d> {
             w.set_pf(GPIO_PF);
             w.set_hiz1(true);
             w.set_pc(true);
-            w.set_inena(false);
+            w.set_inena(true);
+        });
+
+        // Enable output driver (DOE) - required for open-drain to drive low
+        self.pin.block().doeset31_0().write(|w| {
+            w.set_dio(self.pin.bit_index(), true);
         });
 
         self.set_pull(Pull::None);
@@ -836,6 +841,7 @@ impl<'d> embedded_hal_async::digital::Wait for OutputOpenDrain<'d> {
     }
 }
 
+#[cfg_attr(mspm0g518x, allow(dead_code))]
 #[derive(Copy, Clone)]
 pub struct PfType {
     pull: Pull,
@@ -943,6 +949,7 @@ pub(crate) trait SealedPin {
         });
     }
 
+    #[cfg_attr(mspm0g518x, allow(dead_code))]
     fn update_pf(&self, ty: PfType) {
         let pincm = pac::IOMUX.pincm(self._pin_cm() as usize);
         let pf = pincm.read().pf();
@@ -950,6 +957,7 @@ pub(crate) trait SealedPin {
         set_pf(self._pin_cm() as usize, pf, ty);
     }
 
+    #[cfg_attr(mspm0g518x, allow(dead_code))]
     fn set_as_pf(&self, pf: u8, ty: PfType) {
         set_pf(self._pin_cm() as usize, pf, ty)
     }
@@ -962,6 +970,7 @@ pub(crate) trait SealedPin {
     ///
     /// Note that this also disables the internal weak pull-up and pull-down resistors.
     #[inline]
+    #[cfg_attr(mspm0g518x, allow(dead_code))]
     fn set_as_disconnected(&self) {
         self.set_as_analog();
     }
@@ -1105,16 +1114,21 @@ fn irq_handler(gpio: gpio::Gpio, wakers: &[AtomicWaker; 32]) {
     }
 }
 
+#[cfg(all(gpioa_interrupt, gpioa_group))]
+compile_error!("gpioa_interrupt and gpioa_group are mutually exclusive cfgs");
+#[cfg(all(gpiob_interrupt, gpiob_group))]
+compile_error!("gpiob_interrupt and gpiob_group are mutually exclusive cfgs");
+
 // C110x and L110x have a dedicated interrupts just for GPIOA.
 //
 // These chips do not have a GROUP1 interrupt.
-#[cfg(all(feature = "rt", any(mspm0c110x, mspm0c1105_c1106, mspm0l110x)))]
+#[cfg(all(feature = "rt", gpioa_interrupt))]
 #[interrupt]
 fn GPIOA() {
     irq_handler(pac::GPIOA, &PORTA_WAKERS);
 }
 
-#[cfg(all(feature = "rt", mspm0c1105_c1106))]
+#[cfg(all(feature = "rt", gpiob_interrupt))]
 #[interrupt]
 fn GPIOB() {
     irq_handler(pac::GPIOB, &PORTB_WAKERS);
@@ -1124,23 +1138,23 @@ fn GPIOB() {
 //
 // Defining these as no_mangle is required so that the linker will pick these over the default handler.
 
-#[cfg(all(feature = "rt", not(any(mspm0c110x, mspm0c1105_c1106, mspm0l110x))))]
-#[no_mangle]
+#[cfg(all(feature = "rt", gpioa_group))]
+#[unsafe(no_mangle)]
 #[allow(non_snake_case)]
 fn GPIOA() {
     irq_handler(pac::GPIOA, &PORTA_WAKERS);
 }
 
-#[cfg(all(feature = "rt", gpio_pb, not(mspm0c1105_c1106)))]
-#[no_mangle]
+#[cfg(all(feature = "rt", gpiob_group))]
+#[unsafe(no_mangle)]
 #[allow(non_snake_case)]
 fn GPIOB() {
     irq_handler(pac::GPIOB, &PORTB_WAKERS);
 }
 
-#[cfg(all(feature = "rt", gpio_pc))]
+#[cfg(all(feature = "rt", gpioc_group))]
 #[allow(non_snake_case)]
-#[no_mangle]
+#[unsafe(no_mangle)]
 fn GPIOC() {
     irq_handler(pac::GPIOC, &PORTC_WAKERS);
 }