12 files changed, 949 insertions, 44 deletions

diff --git a/embassy-mspm0/src/adc.rs b/embassy-mspm0/src/adc.rs
index 5b93e9a6e..948801679 100644
--- a/embassy-mspm0/src/adc.rs
+++ b/embassy-mspm0/src/adc.rs
@@ -4,13 +4,13 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
 
-use embassy_hal_internal::{impl_peripheral, PeripheralType};
+use embassy_hal_internal::{PeripheralType, impl_peripheral};
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::interrupt::{Interrupt, InterruptExt};
 use crate::mode::{Async, Blocking, Mode};
-use crate::pac::adc::{vals, Adc as Regs};
-use crate::{interrupt, Peri};
+use crate::pac::adc::{Adc as Regs, vals};
+use crate::{Peri, interrupt};
 
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
diff --git a/embassy-mspm0/src/dma.rs b/embassy-mspm0/src/dma.rs
index 66b79709c..58b087761 100644
--- a/embassy-mspm0/src/dma.rs
+++ b/embassy-mspm0/src/dma.rs
@@ -5,18 +5,18 @@
 use core::future::Future;
 use core::mem;
 use core::pin::Pin;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::{Context, Poll};
 
 use critical_section::CriticalSection;
 use embassy_hal_internal::interrupt::InterruptExt;
-use embassy_hal_internal::{impl_peripheral, PeripheralType};
+use embassy_hal_internal::{PeripheralType, impl_peripheral};
 use embassy_sync::waitqueue::AtomicWaker;
-use mspm0_metapac::common::{Reg, RW};
+use mspm0_metapac::common::{RW, Reg};
 use mspm0_metapac::dma::regs;
 use mspm0_metapac::dma::vals::{self, Autoen, Em, Incr, Preirq, Wdth};
 
-use crate::{interrupt, pac, Peri};
+use crate::{Peri, interrupt, pac};
 
 /// The burst size of a DMA transfer.
 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
diff --git a/embassy-mspm0/src/gpio.rs b/embassy-mspm0/src/gpio.rs
index d5fd36dbf..709102c59 100644
--- a/embassy-mspm0/src/gpio.rs
+++ b/embassy-mspm0/src/gpio.rs
@@ -5,12 +5,12 @@ use core::future::Future;
 use core::pin::Pin as FuturePin;
 use core::task::{Context, Poll};
 
-use embassy_hal_internal::{impl_peripheral, Peri, PeripheralType};
+use embassy_hal_internal::{Peri, PeripheralType, impl_peripheral};
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::pac::gpio::vals::*;
 use crate::pac::gpio::{self};
-#[cfg(all(feature = "rt", any(mspm0c110x, mspm0c1105_c1106, mspm0l110x)))]
+#[cfg(all(feature = "rt", any(gpioa_interrupt, gpiob_interrupt)))]
 use crate::pac::interrupt;
 use crate::pac::{self};
 
@@ -156,7 +156,12 @@ impl<'d> Flex<'d> {
             w.set_pf(GPIO_PF);
             w.set_hiz1(true);
             w.set_pc(true);
-            w.set_inena(false);
+            w.set_inena(true);
+        });
+
+        // Enable output driver (DOE) - required for open-drain to drive low
+        self.pin.block().doeset31_0().write(|w| {
+            w.set_dio(self.pin.bit_index(), true);
         });
 
         self.set_pull(Pull::None);
@@ -836,6 +841,7 @@ impl<'d> embedded_hal_async::digital::Wait for OutputOpenDrain<'d> {
     }
 }
 
+#[cfg_attr(mspm0g518x, allow(dead_code))]
 #[derive(Copy, Clone)]
 pub struct PfType {
     pull: Pull,
@@ -943,6 +949,7 @@ pub(crate) trait SealedPin {
         });
     }
 
+    #[cfg_attr(mspm0g518x, allow(dead_code))]
     fn update_pf(&self, ty: PfType) {
         let pincm = pac::IOMUX.pincm(self._pin_cm() as usize);
         let pf = pincm.read().pf();
@@ -950,6 +957,7 @@ pub(crate) trait SealedPin {
         set_pf(self._pin_cm() as usize, pf, ty);
     }
 
+    #[cfg_attr(mspm0g518x, allow(dead_code))]
     fn set_as_pf(&self, pf: u8, ty: PfType) {
         set_pf(self._pin_cm() as usize, pf, ty)
     }
@@ -962,6 +970,7 @@ pub(crate) trait SealedPin {
     ///
     /// Note that this also disables the internal weak pull-up and pull-down resistors.
     #[inline]
+    #[cfg_attr(mspm0g518x, allow(dead_code))]
     fn set_as_disconnected(&self) {
         self.set_as_analog();
     }
@@ -1105,16 +1114,21 @@ fn irq_handler(gpio: gpio::Gpio, wakers: &[AtomicWaker; 32]) {
     }
 }
 
+#[cfg(all(gpioa_interrupt, gpioa_group))]
+compile_error!("gpioa_interrupt and gpioa_group are mutually exclusive cfgs");
+#[cfg(all(gpiob_interrupt, gpiob_group))]
+compile_error!("gpiob_interrupt and gpiob_group are mutually exclusive cfgs");
+
 // C110x and L110x have a dedicated interrupts just for GPIOA.
 //
 // These chips do not have a GROUP1 interrupt.
-#[cfg(all(feature = "rt", any(mspm0c110x, mspm0c1105_c1106, mspm0l110x)))]
+#[cfg(all(feature = "rt", gpioa_interrupt))]
 #[interrupt]
 fn GPIOA() {
     irq_handler(pac::GPIOA, &PORTA_WAKERS);
 }
 
-#[cfg(all(feature = "rt", mspm0c1105_c1106))]
+#[cfg(all(feature = "rt", gpiob_interrupt))]
 #[interrupt]
 fn GPIOB() {
     irq_handler(pac::GPIOB, &PORTB_WAKERS);
@@ -1124,23 +1138,23 @@ fn GPIOB() {
 //
 // Defining these as no_mangle is required so that the linker will pick these over the default handler.
 
-#[cfg(all(feature = "rt", not(any(mspm0c110x, mspm0c1105_c1106, mspm0l110x))))]
-#[no_mangle]
+#[cfg(all(feature = "rt", gpioa_group))]
+#[unsafe(no_mangle)]
 #[allow(non_snake_case)]
 fn GPIOA() {
     irq_handler(pac::GPIOA, &PORTA_WAKERS);
 }
 
-#[cfg(all(feature = "rt", gpio_pb, not(mspm0c1105_c1106)))]
-#[no_mangle]
+#[cfg(all(feature = "rt", gpiob_group))]
+#[unsafe(no_mangle)]
 #[allow(non_snake_case)]
 fn GPIOB() {
     irq_handler(pac::GPIOB, &PORTB_WAKERS);
 }
 
-#[cfg(all(feature = "rt", gpio_pc))]
+#[cfg(all(feature = "rt", gpioc_group))]
 #[allow(non_snake_case)]
-#[no_mangle]
+#[unsafe(no_mangle)]
 fn GPIOC() {
     irq_handler(pac::GPIOC, &PORTC_WAKERS);
 }
diff --git a/embassy-mspm0/src/i2c.rs b/embassy-mspm0/src/i2c.rs
index 1906e37ba..3067f4833 100644
--- a/embassy-mspm0/src/i2c.rs
+++ b/embassy-mspm0/src/i2c.rs
@@ -10,13 +10,13 @@ use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 use mspm0_metapac::i2c;
 
+use crate::Peri;
 use crate::gpio::{AnyPin, PfType, Pull, SealedPin};
 use crate::interrupt::typelevel::Binding;
 use crate::interrupt::{Interrupt, InterruptExt};
 use crate::mode::{Async, Blocking, Mode};
-use crate::pac::i2c::{vals, I2c as Regs};
+use crate::pac::i2c::{I2c as Regs, vals};
 use crate::pac::{self};
-use crate::Peri;
 
 /// The clock source for the I2C.
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
@@ -56,7 +56,7 @@ pub enum ClockDiv {
 }
 
 impl ClockDiv {
-    fn into(self) -> vals::Ratio {
+    pub(crate) fn into(self) -> vals::Ratio {
         match self {
             Self::DivBy1 => vals::Ratio::DIV_BY_1,
             Self::DivBy2 => vals::Ratio::DIV_BY_2,
@@ -133,6 +133,11 @@ pub enum ConfigError {
     ///
     /// The clock soure is not enabled is SYSCTL.
     ClockSourceNotEnabled,
+
+    /// Invalid target address.
+    ///
+    /// The target address is not 7-bit.
+    InvalidTargetAddress,
 }
 
 #[non_exhaustive]
@@ -140,7 +145,7 @@ pub enum ConfigError {
 /// Config
 pub struct Config {
     /// I2C clock source.
-    clock_source: ClockSel,
+    pub(crate) clock_source: ClockSel,
 
     /// I2C clock divider.
     pub clock_div: ClockDiv,
@@ -196,7 +201,7 @@ impl Config {
     }
 
     #[cfg(any(mspm0c110x, mspm0c1105_c1106))]
-    fn calculate_clock_source(&self) -> u32 {
+    pub(crate) fn calculate_clock_source(&self) -> u32 {
         // Assume that BusClk has default value.
         // TODO: calculate BusClk more precisely.
         match self.clock_source {
@@ -206,10 +211,10 @@ impl Config {
     }
 
     #[cfg(any(
-        mspm0g110x, mspm0g150x, mspm0g151x, mspm0g310x, mspm0g350x, mspm0g351x, mspm0l110x, mspm0l122x, mspm0l130x,
-        mspm0l134x, mspm0l222x
+        mspm0g110x, mspm0g150x, mspm0g151x, mspm0g310x, mspm0g350x, mspm0g351x, mspm0h321x, mspm0l110x, mspm0l122x,
+        mspm0l130x, mspm0l134x, mspm0l222x
     ))]
-    fn calculate_clock_source(&self) -> u32 {
+    pub(crate) fn calculate_clock_source(&self) -> u32 {
         // Assume that BusClk has default value.
         // TODO: calculate BusClk more precisely.
         match self.clock_source {
diff --git a/embassy-mspm0/src/i2c_target.rs b/embassy-mspm0/src/i2c_target.rs
new file mode 100644
index 000000000..e371fa903
--- /dev/null
+++ b/embassy-mspm0/src/i2c_target.rs
@@ -0,0 +1,510 @@
+//! Inter-Integrated-Circuit (I2C) Target
+// The following code is modified from embassy-stm32 and embassy-rp
+// https://github.com/embassy-rs/embassy/tree/main/embassy-stm32
+// https://github.com/embassy-rs/embassy/tree/main/embassy-rp
+
+use core::future::poll_fn;
+use core::marker::PhantomData;
+use core::sync::atomic::Ordering;
+use core::task::Poll;
+
+use embassy_embedded_hal::SetConfig;
+use mspm0_metapac::i2c::vals::CpuIntIidxStat;
+
+use crate::gpio::{AnyPin, SealedPin};
+// Re-use I2c controller types
+use crate::i2c::{ClockSel, ConfigError, Info, Instance, InterruptHandler, SclPin, SdaPin, State};
+use crate::interrupt::InterruptExt;
+use crate::mode::{Async, Blocking, Mode};
+use crate::pac::i2c::vals;
+use crate::pac::{self};
+use crate::{Peri, i2c, i2c_target, interrupt};
+
+#[non_exhaustive]
+#[derive(Clone, Copy, PartialEq, Eq, Debug)]
+/// Config
+pub struct Config {
+    /// 7-bit Target Address
+    pub target_addr: u8,
+
+    /// Control if the target should ack to and report general calls.
+    pub general_call: bool,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            target_addr: 0x48,
+            general_call: false,
+        }
+    }
+}
+
+/// I2C error
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum Error {
+    /// User passed in a response buffer that was 0 length
+    InvalidResponseBufferLength,
+    /// The response buffer length was too short to contain the message
+    ///
+    /// The length parameter will always be the length of the buffer, and is
+    /// provided as a convenience for matching alongside `Command::Write`.
+    PartialWrite(usize),
+    /// The response buffer length was too short to contain the message
+    ///
+    /// The length parameter will always be the length of the buffer, and is
+    /// provided as a convenience for matching alongside `Command::GeneralCall`.
+    PartialGeneralCall(usize),
+}
+
+/// Received command from the controller.
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Command {
+    /// General Call Write: Controller sent the General Call address (0x00) followed by data.
+    /// Contains the number of bytes written by the controller.
+    GeneralCall(usize),
+    /// Read: Controller wants to read data from the target.
+    Read,
+    /// Write: Controller sent the target's address followed by data.
+    /// Contains the number of bytes written by the controller.
+    Write(usize),
+    /// Write followed by Read (Repeated Start): Controller wrote data, then issued a repeated
+    /// start and wants to read data. Contains the number of bytes written before the read.
+    WriteRead(usize),
+}
+
+/// Status after responding to a controller read request.
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum ReadStatus {
+    /// Transaction completed successfully. The controller either NACKed the last byte
+    /// or sent a STOP condition.
+    Done,
+    /// Transaction incomplete, controller trying to read more bytes than were provided
+    NeedMoreBytes,
+    /// Transaction complete, but controller stopped reading bytes before we ran out
+    LeftoverBytes(u16),
+}
+
+/// I2C Target driver.
+// Use the same Instance, SclPin, SdaPin traits as the controller
+pub struct I2cTarget<'d, M: Mode> {
+    info: &'static Info,
+    state: &'static State,
+    scl: Option<Peri<'d, AnyPin>>,
+    sda: Option<Peri<'d, AnyPin>>,
+    config: i2c::Config,
+    target_config: i2c_target::Config,
+    _phantom: PhantomData<M>,
+}
+
+impl<'d> SetConfig for I2cTarget<'d, Async> {
+    type Config = (i2c::Config, i2c_target::Config);
+    type ConfigError = ConfigError;
+
+    fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
+        self.info.interrupt.disable();
+
+        if let Some(ref sda) = self.sda {
+            sda.update_pf(config.0.sda_pf());
+        }
+
+        if let Some(ref scl) = self.scl {
+            scl.update_pf(config.0.scl_pf());
+        }
+
+        self.config = config.0.clone();
+        self.target_config = config.1.clone();
+
+        self.reset()
+    }
+}
+
+impl<'d> SetConfig for I2cTarget<'d, Blocking> {
+    type Config = (i2c::Config, i2c_target::Config);
+    type ConfigError = ConfigError;
+
+    fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
+        if let Some(ref sda) = self.sda {
+            sda.update_pf(config.0.sda_pf());
+        }
+
+        if let Some(ref scl) = self.scl {
+            scl.update_pf(config.0.scl_pf());
+        }
+
+        self.config = config.0.clone();
+        self.target_config = config.1.clone();
+
+        self.reset()
+    }
+}
+
+impl<'d> I2cTarget<'d, Async> {
+    /// Create a new asynchronous I2C target driver using interrupts
+    /// The `config` reuses the i2c controller config to setup the clock while `target_config`
+    /// configures i2c target specific parameters.
+    pub fn new<T: Instance>(
+        peri: Peri<'d, T>,
+        scl: Peri<'d, impl SclPin<T>>,
+        sda: Peri<'d, impl SdaPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+        config: i2c::Config,
+        target_config: i2c_target::Config,
+    ) -> Result<Self, ConfigError> {
+        let mut this = Self::new_inner(
+            peri,
+            new_pin!(scl, config.scl_pf()),
+            new_pin!(sda, config.sda_pf()),
+            config,
+            target_config,
+        );
+        this.reset()?;
+        Ok(this)
+    }
+
+    /// Reset the i2c peripheral. If you cancel a respond_to_read, you may stall the bus.
+    /// You can recover the bus by calling this function, but doing so will almost certainly cause
+    /// an i/o error in the controller.
+    pub fn reset(&mut self) -> Result<(), ConfigError> {
+        self.init()?;
+        unsafe { self.info.interrupt.enable() };
+        Ok(())
+    }
+}
+
+impl<'d> I2cTarget<'d, Blocking> {
+    /// Create a new blocking I2C target driver.
+    /// The `config` reuses the i2c controller config to setup the clock while `target_config`
+    /// configures i2c target specific parameters.
+    pub fn new_blocking<T: Instance>(
+        peri: Peri<'d, T>,
+        scl: Peri<'d, impl SclPin<T>>,
+        sda: Peri<'d, impl SdaPin<T>>,
+        config: i2c::Config,
+        target_config: i2c_target::Config,
+    ) -> Result<Self, ConfigError> {
+        let mut this = Self::new_inner(
+            peri,
+            new_pin!(scl, config.scl_pf()),
+            new_pin!(sda, config.sda_pf()),
+            config,
+            target_config,
+        );
+        this.reset()?;
+        Ok(this)
+    }
+
+    /// Reset the i2c peripheral. If you cancel a respond_to_read, you may stall the bus.
+    /// You can recover the bus by calling this function, but doing so will almost certainly cause
+    /// an i/o error in the controller.
+    pub fn reset(&mut self) -> Result<(), ConfigError> {
+        self.init()?;
+        Ok(())
+    }
+}
+
+impl<'d, M: Mode> I2cTarget<'d, M> {
+    fn new_inner<T: Instance>(
+        _peri: Peri<'d, T>,
+        scl: Option<Peri<'d, AnyPin>>,
+        sda: Option<Peri<'d, AnyPin>>,
+        config: i2c::Config,
+        target_config: i2c_target::Config,
+    ) -> Self {
+        if let Some(ref scl) = scl {
+            let pincm = pac::IOMUX.pincm(scl._pin_cm() as usize);
+            pincm.modify(|w| {
+                w.set_hiz1(true);
+            });
+        }
+        if let Some(ref sda) = sda {
+            let pincm = pac::IOMUX.pincm(sda._pin_cm() as usize);
+            pincm.modify(|w| {
+                w.set_hiz1(true);
+            });
+        }
+
+        Self {
+            info: T::info(),
+            state: T::state(),
+            scl,
+            sda,
+            config,
+            target_config,
+            _phantom: PhantomData,
+        }
+    }
+
+    fn init(&mut self) -> Result<(), ConfigError> {
+        let mut config = self.config;
+        let target_config = self.target_config;
+        let regs = self.info.regs;
+
+        config.check_config()?;
+        // Target address must be 7-bit
+        if !(target_config.target_addr < 0x80) {
+            return Err(ConfigError::InvalidTargetAddress);
+        }
+
+        regs.target(0).tctr().modify(|w| {
+            w.set_active(false);
+        });
+
+        // Init power for I2C
+        regs.gprcm(0).rstctl().write(|w| {
+            w.set_resetstkyclr(true);
+            w.set_resetassert(true);
+            w.set_key(vals::ResetKey::KEY);
+        });
+
+        regs.gprcm(0).pwren().write(|w| {
+            w.set_enable(true);
+            w.set_key(vals::PwrenKey::KEY);
+        });
+
+        self.info.interrupt.disable();
+
+        // Init delay from the M0 examples by TI in CCStudio (16 cycles)
+        cortex_m::asm::delay(16);
+
+        // Select and configure the I2C clock using the CLKSEL and CLKDIV registers
+        regs.clksel().write(|w| match config.clock_source {
+            ClockSel::BusClk => {
+                w.set_mfclk_sel(false);
+                w.set_busclk_sel(true);
+            }
+            ClockSel::MfClk => {
+                w.set_mfclk_sel(true);
+                w.set_busclk_sel(false);
+            }
+        });
+        regs.clkdiv().write(|w| w.set_ratio(config.clock_div.into()));
+
+        // Configure at least one target address by writing the 7-bit address to I2Cx.SOAR register. The additional
+        // target address can be enabled and configured by using I2Cx.TOAR2 register.
+        regs.target(0).toar().modify(|w| {
+            w.set_oaren(true);
+            w.set_oar(target_config.target_addr as u16);
+        });
+
+        self.state
+            .clock
+            .store(config.calculate_clock_source(), Ordering::Relaxed);
+
+        regs.target(0).tctr().modify(|w| {
+            w.set_gencall(target_config.general_call);
+            w.set_tclkstretch(true);
+            // Disable target wakeup, follow TI example. (TI note: Workaround for errata I2C_ERR_04.)
+            w.set_twuen(false);
+            w.set_txempty_on_treq(true);
+        });
+
+        // Enable the I2C target mode by setting the ACTIVE bit in I2Cx.TCTR register.
+        regs.target(0).tctr().modify(|w| {
+            w.set_active(true);
+        });
+
+        Ok(())
+    }
+
+    #[inline(always)]
+    fn drain_fifo(&mut self, buffer: &mut [u8], offset: &mut usize) {
+        let regs = self.info.regs;
+
+        for b in &mut buffer[*offset..] {
+            if regs.target(0).tfifosr().read().rxfifocnt() == 0 {
+                break;
+            }
+
+            *b = regs.target(0).trxdata().read().value();
+            *offset += 1;
+        }
+    }
+
+    /// Blocking function to empty the tx fifo
+    ///
+    /// This function can be used to empty the transmit FIFO if data remains after handling a 'read' command (LeftoverBytes).
+    pub fn flush_tx_fifo(&mut self) {
+        self.info.regs.target(0).tfifoctl().modify(|w| {
+            w.set_txflush(true);
+        });
+        while self.info.regs.target(0).tfifosr().read().txfifocnt() as usize != self.info.fifo_size {}
+        self.info.regs.target(0).tfifoctl().modify(|w| {
+            w.set_txflush(false);
+        });
+    }
+}
+
+impl<'d> I2cTarget<'d, Async> {
+    /// Wait asynchronously for commands from an I2C controller.
+    /// `buffer` is provided in case controller does a 'write', 'write read', or 'general call' and is unused for 'read'.
+    pub async fn listen(&mut self, buffer: &mut [u8]) -> Result<Command, Error> {
+        let regs = self.info.regs;
+
+        let mut len = 0;
+
+        // Set the rx fifo interrupt to avoid a fifo overflow
+        regs.target(0).tfifoctl().modify(|r| {
+            r.set_rxtrig(vals::TfifoctlRxtrig::LEVEL_6);
+        });
+
+        self.wait_on(
+            |me| {
+                // Check if address matches the General Call address (0x00)
+                let is_gencall = regs.target(0).tsr().read().addrmatch() == 0;
+
+                if regs.target(0).tfifosr().read().rxfifocnt() > 0 {
+                    me.drain_fifo(buffer, &mut len);
+                }
+
+                if buffer.len() == len && regs.target(0).tfifosr().read().rxfifocnt() > 0 {
+                    if is_gencall {
+                        return Poll::Ready(Err(Error::PartialGeneralCall(buffer.len())));
+                    } else {
+                        return Poll::Ready(Err(Error::PartialWrite(buffer.len())));
+                    }
+                }
+
+                let iidx = regs.cpu_int(0).iidx().read().stat();
+                trace!("ls:{} len:{}", iidx as u8, len);
+                let result = match iidx {
+                    CpuIntIidxStat::TTXEMPTY => match len {
+                        0 => Poll::Ready(Ok(Command::Read)),
+                        w => Poll::Ready(Ok(Command::WriteRead(w))),
+                    },
+                    CpuIntIidxStat::TSTOPFG => match (is_gencall, len) {
+                        (_, 0) => Poll::Pending,
+                        (true, w) => Poll::Ready(Ok(Command::GeneralCall(w))),
+                        (false, w) => Poll::Ready(Ok(Command::Write(w))),
+                    },
+                    _ => Poll::Pending,
+                };
+                if !result.is_pending() {
+                    regs.cpu_int(0).imask().write(|_| {});
+                }
+                result
+            },
+            |_me| {
+                regs.cpu_int(0).imask().write(|_| {});
+                regs.cpu_int(0).imask().modify(|w| {
+                    w.set_tgencall(true);
+                    w.set_trxfifotrg(true);
+                    w.set_tstop(true);
+                    w.set_ttxempty(true);
+                });
+            },
+        )
+        .await
+    }
+
+    /// Respond to an I2C controller 'read' command, asynchronously.
+    pub async fn respond_to_read(&mut self, buffer: &[u8]) -> Result<ReadStatus, Error> {
+        if buffer.is_empty() {
+            return Err(Error::InvalidResponseBufferLength);
+        }
+
+        let regs = self.info.regs;
+        let fifo_size = self.info.fifo_size;
+        let mut chunks = buffer.chunks(self.info.fifo_size);
+
+        self.wait_on(
+            |_me| {
+                if let Some(chunk) = chunks.next() {
+                    for byte in chunk {
+                        regs.target(0).ttxdata().write(|w| w.set_value(*byte));
+                    }
+
+                    return Poll::Pending;
+                }
+
+                let iidx = regs.cpu_int(0).iidx().read().stat();
+                let fifo_bytes = fifo_size - regs.target(0).tfifosr().read().txfifocnt() as usize;
+                trace!("rs:{}, fifo:{}", iidx as u8, fifo_bytes);
+
+                let result = match iidx {
+                    CpuIntIidxStat::TTXEMPTY => Poll::Ready(Ok(ReadStatus::NeedMoreBytes)),
+                    CpuIntIidxStat::TSTOPFG => match fifo_bytes {
+                        0 => Poll::Ready(Ok(ReadStatus::Done)),
+                        w => Poll::Ready(Ok(ReadStatus::LeftoverBytes(w as u16))),
+                    },
+                    _ => Poll::Pending,
+                };
+                if !result.is_pending() {
+                    regs.cpu_int(0).imask().write(|_| {});
+                }
+                result
+            },
+            |_me| {
+                regs.cpu_int(0).imask().write(|_| {});
+                regs.cpu_int(0).imask().modify(|w| {
+                    w.set_ttxempty(true);
+                    w.set_tstop(true);
+                });
+            },
+        )
+        .await
+    }
+
+    /// Respond to reads with the fill byte until the controller stops asking
+    pub async fn respond_till_stop(&mut self, fill: u8) -> Result<(), Error> {
+        // The buffer size could be increased to reduce interrupt noise but has higher probability
+        // of LeftoverBytes
+        let buff = [fill];
+        loop {
+            match self.respond_to_read(&buff).await {
+                Ok(ReadStatus::NeedMoreBytes) => (),
+                Ok(_) => break Ok(()),
+                Err(e) => break Err(e),
+            }
+        }
+    }
+
+    /// Respond to a controller read, then fill any remaining read bytes with `fill`
+    pub async fn respond_and_fill(&mut self, buffer: &[u8], fill: u8) -> Result<ReadStatus, Error> {
+        let resp_stat = self.respond_to_read(buffer).await?;
+
+        if resp_stat == ReadStatus::NeedMoreBytes {
+            self.respond_till_stop(fill).await?;
+            Ok(ReadStatus::Done)
+        } else {
+            Ok(resp_stat)
+        }
+    }
+
+    /// Calls `f` to check if we are ready or not.
+    /// If not, `g` is called once(to eg enable the required interrupts).
+    /// The waker will always be registered prior to calling `f`.
+    #[inline(always)]
+    async fn wait_on<F, U, G>(&mut self, mut f: F, mut g: G) -> U
+    where
+        F: FnMut(&mut Self) -> Poll<U>,
+        G: FnMut(&mut Self),
+    {
+        poll_fn(|cx| {
+            // Register prior to checking the condition
+            self.state.waker.register(cx.waker());
+            let r = f(self);
+
+            if r.is_pending() {
+                g(self);
+            }
+
+            r
+        })
+        .await
+    }
+}
+
+impl<'d, M: Mode> Drop for I2cTarget<'d, M> {
+    fn drop(&mut self) {
+        // Ensure peripheral is disabled and pins are reset
+        self.info.regs.target(0).tctr().modify(|w| w.set_active(false));
+
+        self.scl.as_ref().map(|x| x.set_as_disconnected());
+        self.sda.as_ref().map(|x| x.set_as_disconnected());
+    }
+}
diff --git a/embassy-mspm0/src/lib.rs b/embassy-mspm0/src/lib.rs
index 13f0ce662..548fb33ca 100644
--- a/embassy-mspm0/src/lib.rs
+++ b/embassy-mspm0/src/lib.rs
@@ -1,4 +1,5 @@
 #![no_std]
+#![allow(unsafe_op_in_unsafe_fn)]
 // Doc feature labels can be tested locally by running RUSTDOCFLAGS="--cfg=docsrs" cargo +nightly doc
 #![cfg_attr(docsrs, feature(doc_auto_cfg, doc_cfg_hide), doc(cfg_hide(doc, docsrs)))]
 #![cfg_attr(
@@ -7,17 +8,23 @@
 )]
 #![doc = include_str!("../README.md")]
 
-// This mod MUST go first, so that the others see its macros.
+// These mods MUST go first, so that the others see the macros.
 pub(crate) mod fmt;
-
-// This must be declared early as well for
 mod macros;
 
 pub mod adc;
 pub mod dma;
 pub mod gpio;
+// TODO: I2C unicomm
+#[cfg(not(unicomm))]
 pub mod i2c;
+#[cfg(not(unicomm))]
+pub mod i2c_target;
+#[cfg(any(mspm0g150x, mspm0g151x, mspm0g350x, mspm0g351x))]
+pub mod mathacl;
 pub mod timer;
+// TODO: UART unicomm
+#[cfg(not(unicomm))]
 pub mod uart;
 pub mod wwdt;
 
@@ -54,7 +61,7 @@ pub(crate) mod _generated {
 
 // Reexports
 pub(crate) use _generated::gpio_pincm;
-pub use _generated::{peripherals, Peripherals};
+pub use _generated::{Peripherals, peripherals};
 pub use embassy_hal_internal::Peri;
 #[cfg(feature = "unstable-pac")]
 pub use mspm0_metapac as pac;
@@ -111,7 +118,7 @@ macro_rules! bind_interrupts {
 
         $(
             #[allow(non_snake_case)]
-            #[no_mangle]
+            #[unsafe(no_mangle)]
             $(#[cfg($cond_irq)])?
             unsafe extern "C" fn $irq() {
                 unsafe {
@@ -232,3 +239,115 @@ impl Iterator for BitIter {
         }
     }
 }
+
+/// Reset cause values from SYSCTL.RSTCAUSE register.
+/// Based on MSPM0 L-series Technical Reference Manual Table 2-9 and
+/// MSPM0 G-series Technical Reference Manual Table 2-12.
+#[derive(Clone, Copy, PartialEq, Eq, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum ResetCause {
+    /// No reset since last read
+    NoReset,
+    /// VDD < POR- violation, PMU trim parity fault, or SHUTDNSTOREx parity fault
+    PorHwFailure,
+    /// NRST pin reset (>1s)
+    PorExternalNrst,
+    /// Software-triggered POR
+    PorSwTriggered,
+    /// VDD < BOR- violation
+    BorSupplyFailure,
+    /// Wake from SHUTDOWN
+    BorWakeFromShutdown,
+    /// Non-PMU trim parity fault
+    #[cfg(not(any(
+        mspm0c110x,
+        mspm0c1105_c1106,
+        mspm0g110x,
+        mspm0g150x,
+        mspm0g151x,
+        mspm0g310x,
+        mspm0g350x,
+        mspm0g351x
+    )))]
+    BootrstNonPmuParityFault,
+    /// Fatal clock fault
+    BootrstClockFault,
+    /// Software-triggered BOOTRST
+    BootrstSwTriggered,
+    /// NRST pin reset (<1s)
+    BootrstExternalNrst,
+    /// WWDT0 violation
+    BootrstWwdt0Violation,
+    /// WWDT1 violation (G-series only)
+    #[cfg(any(mspm0g110x, mspm0g150x, mspm0g151x, mspm0g310x, mspm0g350x, mspm0g351x, mspm0g518x))]
+    SysrstWwdt1Violation,
+    /// BSL exit (if present)
+    SysrstBslExit,
+    /// BSL entry (if present)
+    SysrstBslEntry,
+    /// Uncorrectable flash ECC error (if present)
+    #[cfg(not(any(mspm0c110x, mspm0c1105_c1106, mspm0g351x, mspm0g151x)))]
+    SysrstFlashEccError,
+    /// CPU lockup violation
+    SysrstCpuLockupViolation,
+    /// Debug-triggered SYSRST
+    SysrstDebugTriggered,
+    /// Software-triggered SYSRST
+    SysrstSwTriggered,
+    /// Debug-triggered CPURST
+    CpurstDebugTriggered,
+    /// Software-triggered CPURST
+    CpurstSwTriggered,
+}
+
+/// Read the reset cause from the SYSCTL.RSTCAUSE register.
+///
+/// This function reads the reset cause register which indicates why the last
+/// system reset occurred. The register is automatically cleared after being read,
+/// so this should be called only once per application startup.
+///
+/// If the reset cause is not recognized, an `Err` containing the raw value is returned.
+#[must_use = "Reading reset cause will clear it"]
+pub fn read_reset_cause() -> Result<ResetCause, u8> {
+    let cause_raw = pac::SYSCTL.rstcause().read().id();
+
+    use ResetCause::*;
+    use pac::sysctl::vals::Id;
+
+    match cause_raw {
+        Id::NORST => Ok(NoReset),
+        Id::PORHWFAIL => Ok(PorHwFailure),
+        Id::POREXNRST => Ok(PorExternalNrst),
+        Id::PORSW => Ok(PorSwTriggered),
+        Id::BORSUPPLY => Ok(BorSupplyFailure),
+        Id::BORWAKESHUTDN => Ok(BorWakeFromShutdown),
+        #[cfg(not(any(
+            mspm0c110x,
+            mspm0c1105_c1106,
+            mspm0g110x,
+            mspm0g150x,
+            mspm0g151x,
+            mspm0g310x,
+            mspm0g350x,
+            mspm0g351x,
+            mspm0g518x,
+        )))]
+        Id::BOOTNONPMUPARITY => Ok(BootrstNonPmuParityFault),
+        Id::BOOTCLKFAIL => Ok(BootrstClockFault),
+        Id::BOOTSW => Ok(BootrstSwTriggered),
+        Id::BOOTEXNRST => Ok(BootrstExternalNrst),
+        Id::BOOTWWDT0 => Ok(BootrstWwdt0Violation),
+        Id::SYSBSLEXIT => Ok(SysrstBslExit),
+        Id::SYSBSLENTRY => Ok(SysrstBslEntry),
+        #[cfg(any(mspm0g110x, mspm0g150x, mspm0g151x, mspm0g310x, mspm0g350x, mspm0g351x, mspm0g518x))]
+        Id::SYSWWDT1 => Ok(SysrstWwdt1Violation),
+        #[cfg(not(any(mspm0c110x, mspm0c1105_c1106, mspm0g351x, mspm0g151x)))]
+        Id::SYSFLASHECC => Ok(SysrstFlashEccError),
+        Id::SYSCPULOCK => Ok(SysrstCpuLockupViolation),
+        Id::SYSDBG => Ok(SysrstDebugTriggered),
+        Id::SYSSW => Ok(SysrstSwTriggered),
+        Id::CPUDBG => Ok(CpurstDebugTriggered),
+        Id::CPUSW => Ok(CpurstSwTriggered),
+        other => Err(other as u8),
+    }
+}
diff --git a/embassy-mspm0/src/macros.rs b/embassy-mspm0/src/macros.rs
index 5355e7d59..3a12a528a 100644
--- a/embassy-mspm0/src/macros.rs
+++ b/embassy-mspm0/src/macros.rs
@@ -1,5 +1,6 @@
 #![macro_use]
 
+#[allow(unused)]
 macro_rules! new_pin {
     ($name: ident, $pf_type: expr) => {{
         let pin = $name;
diff --git a/embassy-mspm0/src/mathacl.rs b/embassy-mspm0/src/mathacl.rs
new file mode 100644
index 000000000..e29f4a59e
--- /dev/null
+++ b/embassy-mspm0/src/mathacl.rs
@@ -0,0 +1,255 @@
+//! MATHACL
+//!
+//! This HAL implements mathematical calculations performed by the CPU.
+
+#![macro_use]
+
+use core::f32::consts::PI;
+use core::marker::PhantomData;
+
+use embassy_hal_internal::PeripheralType;
+use micromath::F32Ext;
+
+use crate::Peri;
+use crate::pac::mathacl::{Mathacl as Regs, vals};
+
+pub enum Precision {
+    High = 31,
+    Medium = 15,
+    Low = 1,
+}
+
+/// Serial error
+#[derive(Debug, Eq, PartialEq, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum Error {
+    ValueInWrongRange,
+    NBitsTooBig,
+}
+
+pub struct Mathacl<'d> {
+    regs: &'static Regs,
+    _phantom: PhantomData<&'d mut ()>,
+}
+
+impl<'d> Mathacl<'d> {
+    /// Mathacl initialization.
+    pub fn new<T: Instance>(_instance: Peri<'d, T>) -> Self {
+        // Init power
+        T::regs().gprcm(0).rstctl().write(|w| {
+            w.set_resetstkyclr(vals::Resetstkyclr::CLR);
+            w.set_resetassert(vals::Resetassert::ASSERT);
+            w.set_key(vals::ResetKey::KEY);
+        });
+
+        // Enable power
+        T::regs().gprcm(0).pwren().write(|w| {
+            w.set_enable(true);
+            w.set_key(vals::PwrenKey::KEY);
+        });
+
+        // init delay, 16 cycles
+        cortex_m::asm::delay(16);
+
+        Self {
+            regs: T::regs(),
+            _phantom: PhantomData,
+        }
+    }
+
+    /// Internal helper SINCOS function.
+    fn sincos(&mut self, rad: f32, precision: Precision, sin: bool) -> Result<f32, Error> {
+        self.regs.ctl().write(|w| {
+            w.set_func(vals::Func::SINCOS);
+            w.set_numiter(precision as u8);
+        });
+
+        if rad > PI || rad < -PI {
+            return Err(Error::ValueInWrongRange);
+        }
+
+        // TODO: make f32 division on CPU
+        let native = rad / PI;
+
+        match signed_f32_to_register(native, 0) {
+            Ok(val) => self.regs.op1().write(|w| {
+                w.set_data(val);
+            }),
+            Err(er) => return Err(er),
+        };
+
+        // check if done
+        while self.regs.status().read().busy() == vals::Busy::NOTDONE {}
+
+        match sin {
+            true => register_to_signed_f32(self.regs.res2().read().data(), 0),
+            false => register_to_signed_f32(self.regs.res1().read().data(), 0),
+        }
+    }
+
+    /// Calsulates trigonometric sine operation in the range [-1,1) with a give precision.
+    pub fn sin(&mut self, rad: f32, precision: Precision) -> Result<f32, Error> {
+        self.sincos(rad, precision, true)
+    }
+
+    /// Calsulates trigonometric cosine operation in the range [-1,1) with a give precision.
+    pub fn cos(&mut self, rad: f32, precision: Precision) -> Result<f32, Error> {
+        self.sincos(rad, precision, false)
+    }
+}
+
+pub(crate) trait SealedInstance {
+    fn regs() -> &'static Regs;
+}
+
+/// Mathacl instance trait
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType {}
+
+macro_rules! impl_mathacl_instance {
+    ($instance: ident) => {
+        impl crate::mathacl::SealedInstance for crate::peripherals::$instance {
+            fn regs() -> &'static crate::pac::mathacl::Mathacl {
+                &crate::pac::$instance
+            }
+        }
+
+        impl crate::mathacl::Instance for crate::peripherals::$instance {}
+    };
+}
+
+/// Convert f32 data to understandable by M0 format.
+fn signed_f32_to_register(data: f32, n_bits: u8) -> Result<u32, Error> {
+    let mut res: u32 = 0;
+    // check if negative
+    let negative = data < 0.0;
+
+    // absolute value for extraction
+    let abs = data.abs();
+
+    // total integer bit count
+    let total_bits = 31;
+
+    // Validate n_bits
+    if n_bits > 31 {
+        return Err(Error::NBitsTooBig);
+    }
+
+    // number of fractional bits
+    let shift = total_bits - n_bits;
+
+    // Compute masks
+    let (n_mask, m_mask) = if n_bits == 0 {
+        (0, 0x7FFFFFFF)
+    } else if n_bits == 31 {
+        (0x7FFFFFFF, 0)
+    } else {
+        ((1u32 << n_bits) - 1, (1u32 << shift) - 1)
+    };
+
+    // calc. integer(n) & fractional(m) parts
+    let n = abs.floor() as u32;
+    let mut m = ((abs - abs.floor()) * (1u32 << shift) as f32).round() as u32;
+
+    // Handle trimming integer part
+    if n_bits == 0 && n > 0 {
+        m = 0x7FFFFFFF;
+    }
+
+    // calculate result
+    if n_bits > 0 {
+        res = n << shift & n_mask;
+    }
+    if shift > 0 {
+        res = res | m & m_mask;
+    }
+
+    // if negative, do 2’s compliment
+    if negative {
+        res = !res + 1;
+    }
+    Ok(res)
+}
+
+/// Reversely converts M0-register format to native f32.
+fn register_to_signed_f32(data: u32, n_bits: u8) -> Result<f32, Error> {
+    // Validate n_bits
+    if n_bits > 31 {
+        return Err(Error::NBitsTooBig);
+    }
+
+    // total integer bit count
+    let total_bits = 31;
+
+    let negative = (data >> 31) == 1;
+
+    // number of fractional bits
+    let shift = total_bits - n_bits;
+
+    // Compute masks
+    let (n_mask, m_mask) = if n_bits == 0 {
+        (0, 0x7FFFFFFF)
+    } else if n_bits == 31 {
+        (0x7FFFFFFF, 0)
+    } else {
+        ((1u32 << n_bits) - 1, (1u32 << shift) - 1)
+    };
+
+    // Compute n and m
+    let mut n = if n_bits == 0 {
+        0
+    } else if shift >= 32 {
+        data & n_mask
+    } else {
+        (data >> shift) & n_mask
+    };
+    let mut m = data & m_mask;
+
+    // if negative, do 2’s compliment
+    if negative {
+        n = !n & n_mask;
+        m = (!m & m_mask) + 1;
+    }
+
+    let mut value = (n as f32) + (m as f32) / (1u32 << shift) as f32;
+    if negative {
+        value = -value;
+    }
+    return Ok(value);
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn mathacl_convert_func_errors() {
+        assert_eq!(signed_f32_to_register(0.0, 32), Err(Error::NBitsTooBig));
+        assert_eq!(register_to_signed_f32(0, 32), Err(Error::NBitsTooBig));
+    }
+
+    #[test]
+    fn mathacl_signed_f32_to_register() {
+        let mut test_float = 1.0;
+        assert_eq!(signed_f32_to_register(test_float, 0).unwrap(), 0x7FFFFFFF);
+
+        test_float = 0.0;
+        assert_eq!(signed_f32_to_register(test_float, 0).unwrap(), 0x0);
+
+        test_float = -1.0;
+        assert_eq!(signed_f32_to_register(test_float, 0).unwrap(), 0x80000001);
+    }
+
+    #[test]
+    fn mathacl_register_to_signed_f32() {
+        let mut test_u32: u32 = 0x7FFFFFFF;
+        assert_eq!(register_to_signed_f32(test_u32, 0u8).unwrap(), 1.0);
+
+        test_u32 = 0x0;
+        assert_eq!(register_to_signed_f32(test_u32, 0u8).unwrap(), 0.0);
+
+        test_u32 = 0x80000001;
+        assert_eq!(register_to_signed_f32(test_u32, 0u8).unwrap(), -1.0);
+    }
+}
diff --git a/embassy-mspm0/src/time_driver.rs b/embassy-mspm0/src/time_driver.rs
index e80e89e55..b42ff61c2 100644
--- a/embassy-mspm0/src/time_driver.rs
+++ b/embassy-mspm0/src/time_driver.rs
@@ -1,5 +1,5 @@
 use core::cell::{Cell, RefCell};
-use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
+use core::sync::atomic::{AtomicU32, Ordering, compiler_fence};
 use core::task::Waker;
 
 use critical_section::{CriticalSection, Mutex};
@@ -16,6 +16,8 @@ use crate::timer::SealedTimer;
 compile_error!("TIMG12 and TIMG13 are not supported by the time driver yet");
 
 // Currently TIMG12 and TIMG13 are excluded because those are 32-bit timers.
+#[cfg(time_driver_timb0)]
+type T = peripherals::TIMB0;
 #[cfg(time_driver_timg0)]
 type T = peripherals::TIMG0;
 #[cfg(time_driver_timg1)]
@@ -333,6 +335,8 @@ pub(crate) fn init(cs: CriticalSection) {
     DRIVER.init(cs);
 }
 
+// TODO: TIMB0
+
 #[cfg(time_driver_timg0)]
 #[interrupt]
 fn TIMG0() {
diff --git a/embassy-mspm0/src/uart/buffered.rs b/embassy-mspm0/src/uart/buffered.rs
index cbc0b6c80..89e6bcc7b 100644
--- a/embassy-mspm0/src/uart/buffered.rs
+++ b/embassy-mspm0/src/uart/buffered.rs
@@ -1,4 +1,4 @@
-use core::future::{poll_fn, Future};
+use core::future::{Future, poll_fn};
 use core::marker::PhantomData;
 use core::slice;
 use core::sync::atomic::{AtomicU8, Ordering};
@@ -14,7 +14,7 @@ use crate::gpio::{AnyPin, SealedPin};
 use crate::interrupt::typelevel::Binding;
 use crate::pac::uart::Uart as Regs;
 use crate::uart::{Config, ConfigError, CtsPin, Error, Info, Instance, RtsPin, RxPin, State, TxPin};
-use crate::{interrupt, Peri};
+use crate::{Peri, interrupt};
 
 /// Interrupt handler.
 pub struct BufferedInterruptHandler<T: Instance> {
diff --git a/embassy-mspm0/src/uart/mod.rs b/embassy-mspm0/src/uart/mod.rs
index 6599cea06..03e68d297 100644
--- a/embassy-mspm0/src/uart/mod.rs
+++ b/embassy-mspm0/src/uart/mod.rs
@@ -3,17 +3,17 @@
 mod buffered;
 
 use core::marker::PhantomData;
-use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
+use core::sync::atomic::{AtomicU32, Ordering, compiler_fence};
 
 pub use buffered::*;
 use embassy_embedded_hal::SetConfig;
 use embassy_hal_internal::PeripheralType;
 
+use crate::Peri;
 use crate::gpio::{AnyPin, PfType, Pull, SealedPin};
 use crate::interrupt::{Interrupt, InterruptExt};
 use crate::mode::{Blocking, Mode};
-use crate::pac::uart::{vals, Uart as Regs};
-use crate::Peri;
+use crate::pac::uart::{Uart as Regs, vals};
 
 /// The clock source for the UART.
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
@@ -931,8 +931,7 @@ fn set_baudrate_inner(regs: Regs, clock: u32, baudrate: u32) -> Result<(), Confi
         let Some(min_clock) = baudrate.checked_mul(oversampling as u32) else {
             trace!(
                 "{}x oversampling would cause overflow for clock: {} Hz",
-                oversampling,
-                clock
+                oversampling, clock
             );
             continue;
         };
@@ -945,9 +944,7 @@ fn set_baudrate_inner(regs: Regs, clock: u32, baudrate: u32) -> Result<(), Confi
         for &(div, div_value) in &DIVS {
             trace!(
                 "Trying div: {}, oversampling {} for {} baud",
-                div,
-                oversampling,
-                baudrate
+                div, oversampling, baudrate
             );
 
             let Some((ibrd, fbrd)) = calculate_brd(clock, div, baudrate, oversampling) else {
diff --git a/embassy-mspm0/src/wwdt.rs b/embassy-mspm0/src/wwdt.rs
index e5c62c660..92aeb8b40 100644
--- a/embassy-mspm0/src/wwdt.rs
+++ b/embassy-mspm0/src/wwdt.rs
@@ -6,9 +6,9 @@
 
 use embassy_hal_internal::PeripheralType;
 
-use crate::pac::wwdt::{vals, Wwdt as Regs};
-use crate::pac::{self};
 use crate::Peri;
+use crate::pac::wwdt::{Wwdt as Regs, vals};
+use crate::pac::{self};
 
 /// Possible watchdog timeout values.
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]