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-rw-r--r--embassy-rp/src/multicore.rs6
1 files changed, 4 insertions, 2 deletions
diff --git a/embassy-rp/src/multicore.rs b/embassy-rp/src/multicore.rs
index 807fda57b..2a7e4822a 100644
--- a/embassy-rp/src/multicore.rs
+++ b/embassy-rp/src/multicore.rs
@@ -50,7 +50,7 @@
50use core::mem::ManuallyDrop; 50use core::mem::ManuallyDrop;
51use core::sync::atomic::{compiler_fence, AtomicBool, Ordering}; 51use core::sync::atomic::{compiler_fence, AtomicBool, Ordering};
52 52
53use crate::interrupt::Interrupt; 53use crate::interrupt::InterruptExt;
54use crate::peripherals::CORE1; 54use crate::peripherals::CORE1;
55use crate::{gpio, interrupt, pac}; 55use crate::{gpio, interrupt, pac};
56 56
@@ -106,6 +106,7 @@ impl<const SIZE: usize> Stack<SIZE> {
106 } 106 }
107} 107}
108 108
109#[cfg(feature = "rt")]
109#[interrupt] 110#[interrupt]
110#[link_section = ".data.ram_func"] 111#[link_section = ".data.ram_func"]
111unsafe fn SIO_IRQ_PROC1() { 112unsafe fn SIO_IRQ_PROC1() {
@@ -156,7 +157,7 @@ where
156 157
157 IS_CORE1_INIT.store(true, Ordering::Release); 158 IS_CORE1_INIT.store(true, Ordering::Release);
158 // Enable fifo interrupt on CORE1 for `pause` functionality. 159 // Enable fifo interrupt on CORE1 for `pause` functionality.
159 unsafe { interrupt::SIO_IRQ_PROC1::enable() }; 160 unsafe { interrupt::SIO_IRQ_PROC1.enable() };
160 161
161 entry() 162 entry()
162 } 163 }
@@ -297,6 +298,7 @@ fn fifo_read() -> u32 {
297 298
298// Pop a value from inter-core FIFO, `wfe` until available 299// Pop a value from inter-core FIFO, `wfe` until available
299#[inline(always)] 300#[inline(always)]
301#[allow(unused)]
300fn fifo_read_wfe() -> u32 { 302fn fifo_read_wfe() -> u32 {
301 unsafe { 303 unsafe {
302 let sio = pac::SIO; 304 let sio = pac::SIO;