8 files changed, 605 insertions, 289 deletions

diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 8eec6c0c7..484aae1d0 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -2,71 +2,70 @@
 
 use core::marker::PhantomData;
 
-use stm32_metapac::timer::vals::Ckd;
+pub use stm32_metapac::timer::vals::{Ckd, Ossi, Ossr};
 
 use super::low_level::{CountingMode, OutputPolarity, Timer};
-use super::simple_pwm::{Ch1, Ch2, Ch3, Ch4, PwmPin};
-use super::{
-    AdvancedInstance4Channel, Channel, Channel1ComplementaryPin, Channel2ComplementaryPin, Channel3ComplementaryPin,
-    Channel4ComplementaryPin,
-};
+use super::simple_pwm::PwmPin;
+use super::{AdvancedInstance4Channel, Ch1, Ch2, Ch3, Ch4, Channel, TimerComplementaryPin};
 use crate::gpio::{AnyPin, OutputType};
 use crate::time::Hertz;
 use crate::timer::low_level::OutputCompareMode;
+use crate::timer::TimerChannel;
 use crate::Peri;
 
 /// Complementary PWM pin wrapper.
 ///
 /// This wraps a pin to make it usable with PWM.
-pub struct ComplementaryPwmPin<'d, T, C> {
-    _pin: Peri<'d, AnyPin>,
-    phantom: PhantomData<(T, C)>,
+pub struct ComplementaryPwmPin<'d, T, C, #[cfg(afio)] A> {
+    #[allow(unused)]
+    pin: Peri<'d, AnyPin>,
+    phantom: PhantomData<if_afio!((T, C, A))>,
 }
 
-macro_rules! complementary_channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: AdvancedInstance4Channel> ComplementaryPwmPin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " complementary PWM pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, output_type: OutputType) -> Self {
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        crate::gpio::AfType::output(output_type, crate::gpio::Speed::VeryHigh),
-                    );
-                });
-                ComplementaryPwmPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+impl<'d, T: AdvancedInstance4Channel, C: TimerChannel, #[cfg(afio)] A> if_afio!(ComplementaryPwmPin<'d, T, C, A>) {
+    /// Create a new  complementary PWM pin instance.
+    pub fn new(pin: Peri<'d, if_afio!(impl TimerComplementaryPin<T, C, A>)>, output_type: OutputType) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            set_as_af!(
+                pin,
+                crate::gpio::AfType::output(output_type, crate::gpio::Speed::VeryHigh)
+            );
+        });
+        ComplementaryPwmPin {
+            pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
+    }
 }
 
-complementary_channel_impl!(new_ch1, Ch1, Channel1ComplementaryPin);
-complementary_channel_impl!(new_ch2, Ch2, Channel2ComplementaryPin);
-complementary_channel_impl!(new_ch3, Ch3, Channel3ComplementaryPin);
-complementary_channel_impl!(new_ch4, Ch4, Channel4ComplementaryPin);
-
 /// PWM driver with support for standard and complementary outputs.
 pub struct ComplementaryPwm<'d, T: AdvancedInstance4Channel> {
     inner: Timer<'d, T>,
 }
 
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+/// Determines which outputs are active when PWM is in idle mode
+pub enum IdlePolarity {
+    /// Normal channels are forced active and complementary channels are forced inactive
+    OisActive,
+    /// Normal channels are forced inactive and complementary channels are forced active
+    OisnActive,
+}
+
 impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Create a new complementary PWM driver.
-    #[allow(clippy::too_many_arguments)]
-    pub fn new(
+    #[allow(clippy::too_many_arguments, unused)]
+    pub fn new<#[cfg(afio)] A>(
         tim: Peri<'d, T>,
-        _ch1: Option<PwmPin<'d, T, Ch1>>,
-        _ch1n: Option<ComplementaryPwmPin<'d, T, Ch1>>,
-        _ch2: Option<PwmPin<'d, T, Ch2>>,
-        _ch2n: Option<ComplementaryPwmPin<'d, T, Ch2>>,
-        _ch3: Option<PwmPin<'d, T, Ch3>>,
-        _ch3n: Option<ComplementaryPwmPin<'d, T, Ch3>>,
-        _ch4: Option<PwmPin<'d, T, Ch4>>,
-        _ch4n: Option<ComplementaryPwmPin<'d, T, Ch4>>,
+        ch1: Option<if_afio!(PwmPin<'d, T, Ch1, A>)>,
+        ch1n: Option<if_afio!(ComplementaryPwmPin<'d, T, Ch1, A>)>,
+        ch2: Option<if_afio!(PwmPin<'d, T, Ch2, A>)>,
+        ch2n: Option<if_afio!(ComplementaryPwmPin<'d, T, Ch2, A>)>,
+        ch3: Option<if_afio!(PwmPin<'d, T, Ch3, A>)>,
+        ch3n: Option<if_afio!(ComplementaryPwmPin<'d, T, Ch3, A>)>,
+        ch4: Option<if_afio!(PwmPin<'d, T, Ch4, A>)>,
+        ch4n: Option<if_afio!(ComplementaryPwmPin<'d, T, Ch4, A>)>,
         freq: Hertz,
         counting_mode: CountingMode,
     ) -> Self {
@@ -88,10 +87,55 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
                 this.inner.set_output_compare_mode(channel, OutputCompareMode::PwmMode1);
                 this.inner.set_output_compare_preload(channel, true);
             });
+        this.inner.set_autoreload_preload(true);
 
         this
     }
 
+    /// Sets the idle output state for the given channels.
+    pub fn set_output_idle_state(&mut self, channels: &[Channel], polarity: IdlePolarity) {
+        let ois_active = matches!(polarity, IdlePolarity::OisActive);
+        for &channel in channels {
+            self.inner.set_ois(channel, ois_active);
+            self.inner.set_oisn(channel, !ois_active);
+        }
+    }
+
+    /// Set state of OSSI-bit in BDTR register
+    pub fn set_off_state_selection_idle(&mut self, val: Ossi) {
+        self.inner.set_ossi(val);
+    }
+
+    /// Get state of OSSI-bit in BDTR register
+    pub fn get_off_state_selection_idle(&self) -> Ossi {
+        self.inner.get_ossi()
+    }
+
+    /// Set state of OSSR-bit in BDTR register
+    pub fn set_off_state_selection_run(&mut self, val: Ossr) {
+        self.inner.set_ossr(val);
+    }
+
+    /// Get state of OSSR-bit in BDTR register
+    pub fn get_off_state_selection_run(&self) -> Ossr {
+        self.inner.get_ossr()
+    }
+
+    /// Trigger break input from software
+    pub fn trigger_software_break(&mut self, n: usize) {
+        self.inner.trigger_software_break(n);
+    }
+
+    /// Set Master Output Enable
+    pub fn set_master_output_enable(&mut self, enable: bool) {
+        self.inner.set_moe(enable);
+    }
+
+    /// Get Master Output Enable
+    pub fn get_master_output_enable(&self) -> bool {
+        self.inner.get_moe()
+    }
+
     /// Enable the given channel.
     pub fn enable(&mut self, channel: Channel) {
         self.inner.enable_channel(channel, true);
@@ -121,7 +165,11 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
     pub fn get_max_duty(&self) -> u16 {
-        self.inner.get_max_compare_value() as u16 + 1
+        if self.inner.get_counting_mode().is_center_aligned() {
+            self.inner.get_max_compare_value() as u16
+        } else {
+            self.inner.get_max_compare_value() as u16 + 1
+        }
     }
 
     /// Set the duty for a given channel.
@@ -138,6 +186,16 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
         self.inner.set_complementary_output_polarity(channel, polarity);
     }
 
+    /// Set the main output polarity for a given channel.
+    pub fn set_main_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+        self.inner.set_output_polarity(channel, polarity);
+    }
+
+    /// Set the complementary output polarity for a given channel.
+    pub fn set_complementary_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+        self.inner.set_complementary_output_polarity(channel, polarity);
+    }
+
     /// Set the dead time as a proportion of max_duty
     pub fn set_dead_time(&mut self, value: u16) {
         let (ckd, value) = compute_dead_time_value(value);
@@ -145,6 +203,66 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
         self.inner.set_dead_time_clock_division(ckd);
         self.inner.set_dead_time_value(value);
     }
+
+    /// Generate a sequence of PWM waveform
+    ///
+    /// Note:
+    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
+
+        let original_duty_state = self.inner.get_compare_value(channel);
+        let original_enable_state = self.inner.get_channel_enable_state(channel);
+        let original_update_dma_state = self.inner.get_update_dma_state();
+
+        if !original_update_dma_state {
+            self.inner.enable_update_dma(true);
+        }
+
+        if !original_enable_state {
+            self.inner.enable_channel(channel, true);
+        }
+
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
+
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr8,
+                ..Default::default()
+            };
+
+            Transfer::new_write(
+                dma,
+                req,
+                duty,
+                self.inner.regs_gp16().ccr(channel.index()).as_ptr() as *mut u16,
+                dma_transfer_option,
+            )
+            .await
+        };
+
+        // restore output compare state
+        if !original_enable_state {
+            self.inner.enable_channel(channel, false);
+        }
+
+        self.inner.set_compare_value(channel, original_duty_state);
+
+        // Since DMA is closed before timer update event trigger DMA is turn off,
+        // this can almost always trigger a DMA FIFO error.
+        //
+        // optional TODO:
+        // clean FEIF after disable UDE
+        if !original_update_dma_state {
+            self.inner.enable_update_dma(false);
+        }
+    }
 }
 
 impl<'d, T: AdvancedInstance4Channel> embedded_hal_02::Pwm for ComplementaryPwm<'d, T> {
@@ -171,7 +289,11 @@ impl<'d, T: AdvancedInstance4Channel> embedded_hal_02::Pwm for ComplementaryPwm<
     }
 
     fn get_max_duty(&self) -> Self::Duty {
-        self.inner.get_max_compare_value() as u16 + 1
+        if self.inner.get_counting_mode().is_center_aligned() {
+            self.inner.get_max_compare_value() as u16
+        } else {
+            self.inner.get_max_compare_value() as u16 + 1
+        }
     }
 
     fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index ec8b1ddf1..7a25e6c21 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -6,44 +6,33 @@ use core::pin::Pin;
 use core::task::{Context, Poll};
 
 use super::low_level::{CountingMode, FilterValue, InputCaptureMode, InputTISelection, Timer};
-use super::{
-    CaptureCompareInterruptHandler, Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin,
-    GeneralInstance4Channel,
-};
+use super::{CaptureCompareInterruptHandler, Channel, GeneralInstance4Channel, TimerPin};
 pub use super::{Ch1, Ch2, Ch3, Ch4};
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::time::Hertz;
+use crate::timer::TimerChannel;
 use crate::Peri;
 
 /// Capture pin wrapper.
 ///
 /// This wraps a pin to make it usable with capture.
-pub struct CapturePin<'d, T, C> {
-    _pin: Peri<'d, AnyPin>,
-    phantom: PhantomData<(T, C)>,
+pub struct CapturePin<'d, T, C, #[cfg(afio)] A> {
+    #[allow(unused)]
+    pin: Peri<'d, AnyPin>,
+    phantom: PhantomData<if_afio!((T, C, A))>,
 }
-
-macro_rules! channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: GeneralInstance4Channel> CapturePin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " capture pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, pull: Pull) -> Self {
-                pin.set_as_af(pin.af_num(), AfType::input(pull));
-                CapturePin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+impl<'d, T: GeneralInstance4Channel, C: TimerChannel, #[cfg(afio)] A> if_afio!(CapturePin<'d, T, C, A>) {
+    /// Create a new capture pin instance.
+    pub fn new(pin: Peri<'d, if_afio!(impl TimerPin<T, C, A>)>, pull: Pull) -> Self {
+        set_as_af!(pin, AfType::input(pull));
+        CapturePin {
+            pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
+    }
 }
 
-channel_impl!(new_ch1, Ch1, Channel1Pin);
-channel_impl!(new_ch2, Ch2, Channel2Pin);
-channel_impl!(new_ch3, Ch3, Channel3Pin);
-channel_impl!(new_ch4, Ch4, Channel4Pin);
-
 /// Input capture driver.
 pub struct InputCapture<'d, T: GeneralInstance4Channel> {
     inner: Timer<'d, T>,
@@ -51,12 +40,13 @@ pub struct InputCapture<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
     /// Create a new input capture driver.
-    pub fn new(
+    #[allow(unused)]
+    pub fn new<#[cfg(afio)] A>(
         tim: Peri<'d, T>,
-        _ch1: Option<CapturePin<'d, T, Ch1>>,
-        _ch2: Option<CapturePin<'d, T, Ch2>>,
-        _ch3: Option<CapturePin<'d, T, Ch3>>,
-        _ch4: Option<CapturePin<'d, T, Ch4>>,
+        ch1: Option<if_afio!(CapturePin<'d, T, Ch1, A>)>,
+        ch2: Option<if_afio!(CapturePin<'d, T, Ch2, A>)>,
+        ch3: Option<if_afio!(CapturePin<'d, T, Ch3, A>)>,
+        ch4: Option<if_afio!(CapturePin<'d, T, Ch4, A>)>,
         _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
         freq: Hertz,
         counting_mode: CountingMode,
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index dc8ceb725..ac039bb0d 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -686,10 +686,35 @@ impl<'d, T: AdvancedInstance1Channel> Timer<'d, T> {
         self.regs_1ch_cmp().bdtr().modify(|w| w.set_dtg(value));
     }
 
+    /// Set state of OSSI-bit in BDTR register
+    pub fn set_ossi(&self, val: vals::Ossi) {
+        self.regs_1ch_cmp().bdtr().modify(|w| w.set_ossi(val));
+    }
+
+    /// Get state of OSSI-bit in BDTR register
+    pub fn get_ossi(&self) -> vals::Ossi {
+        self.regs_1ch_cmp().bdtr().read().ossi()
+    }
+
+    /// Set state of OSSR-bit in BDTR register
+    pub fn set_ossr(&self, val: vals::Ossr) {
+        self.regs_1ch_cmp().bdtr().modify(|w| w.set_ossr(val));
+    }
+
+    /// Get state of OSSR-bit in BDTR register
+    pub fn get_ossr(&self) -> vals::Ossr {
+        self.regs_1ch_cmp().bdtr().read().ossr()
+    }
+
     /// Set state of MOE-bit in BDTR register to en-/disable output
     pub fn set_moe(&self, enable: bool) {
         self.regs_1ch_cmp().bdtr().modify(|w| w.set_moe(enable));
     }
+
+    /// Get state of MOE-bit in BDTR register
+    pub fn get_moe(&self) -> bool {
+        self.regs_1ch_cmp().bdtr().read().moe()
+    }
 }
 
 #[cfg(not(stm32l0))]
@@ -725,4 +750,19 @@ impl<'d, T: AdvancedInstance4Channel> Timer<'d, T> {
             .ccer()
             .modify(|w| w.set_ccne(channel.index(), enable));
     }
+
+    /// Set Output Idle State
+    pub fn set_ois(&self, channel: Channel, val: bool) {
+        self.regs_advanced().cr2().modify(|w| w.set_ois(channel.index(), val));
+    }
+    /// Set Output Idle State Complementary Channel
+    pub fn set_oisn(&self, channel: Channel, val: bool) {
+        self.regs_advanced().cr2().modify(|w| w.set_oisn(channel.index(), val));
+    }
+
+    /// Trigger software break 1 or 2
+    /// Setting this bit generates a break event. This bit is automatically cleared by the hardware.
+    pub fn trigger_software_break(&self, n: usize) {
+        self.regs_advanced().egr().write(|r| r.set_bg(n, true));
+    }
 }
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index b29382fc8..b09bc7166 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -51,6 +51,80 @@ pub enum Ch3 {}
 /// Channel 4 marker type.
 pub enum Ch4 {}
 
+/// Timer channel trait.
+#[allow(private_bounds)]
+pub trait TimerChannel: SealedTimerChannel {
+    /// The runtime channel.
+    const CHANNEL: Channel;
+}
+
+trait SealedTimerChannel {}
+
+impl TimerChannel for Ch1 {
+    const CHANNEL: Channel = Channel::Ch1;
+}
+
+impl TimerChannel for Ch2 {
+    const CHANNEL: Channel = Channel::Ch2;
+}
+
+impl TimerChannel for Ch3 {
+    const CHANNEL: Channel = Channel::Ch3;
+}
+
+impl TimerChannel for Ch4 {
+    const CHANNEL: Channel = Channel::Ch4;
+}
+
+impl SealedTimerChannel for Ch1 {}
+impl SealedTimerChannel for Ch2 {}
+impl SealedTimerChannel for Ch3 {}
+impl SealedTimerChannel for Ch4 {}
+
+/// Timer break input.
+#[derive(Clone, Copy)]
+pub enum BkIn {
+    /// Break input 1.
+    BkIn1,
+    /// Break input 2.
+    BkIn2,
+}
+
+impl BkIn {
+    /// Get the channel index (0..3)
+    pub fn index(&self) -> usize {
+        match self {
+            BkIn::BkIn1 => 0,
+            BkIn::BkIn2 => 1,
+        }
+    }
+}
+
+/// Break input 1 marker type.
+pub enum BkIn1 {}
+/// Break input 2 marker type.
+pub enum BkIn2 {}
+
+/// Timer channel trait.
+#[allow(private_bounds)]
+pub trait BreakInput: SealedBreakInput {
+    /// The runtim timer channel.
+    const INPUT: BkIn;
+}
+
+trait SealedBreakInput {}
+
+impl BreakInput for BkIn1 {
+    const INPUT: BkIn = BkIn::BkIn1;
+}
+
+impl BreakInput for BkIn2 {
+    const INPUT: BkIn = BkIn::BkIn2;
+}
+
+impl SealedBreakInput for BkIn1 {}
+impl SealedBreakInput for BkIn2 {}
+
 /// Amount of bits of a timer.
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -149,33 +223,20 @@ pub trait AdvancedInstance2Channel: BasicInstance + GeneralInstance2Channel + Ad
 /// Advanced 16-bit timer with 4 channels instance.
 pub trait AdvancedInstance4Channel: AdvancedInstance2Channel + GeneralInstance4Channel {}
 
-pin_trait!(Channel1Pin, GeneralInstance4Channel);
-pin_trait!(Channel2Pin, GeneralInstance4Channel);
-pin_trait!(Channel3Pin, GeneralInstance4Channel);
-pin_trait!(Channel4Pin, GeneralInstance4Channel);
-pin_trait!(ExternalTriggerPin, GeneralInstance4Channel);
-
-pin_trait!(Channel1ComplementaryPin, AdvancedInstance4Channel);
-pin_trait!(Channel2ComplementaryPin, AdvancedInstance4Channel);
-pin_trait!(Channel3ComplementaryPin, AdvancedInstance4Channel);
-pin_trait!(Channel4ComplementaryPin, AdvancedInstance4Channel);
+pin_trait!(TimerPin, GeneralInstance4Channel, TimerChannel, @A);
+pin_trait!(ExternalTriggerPin, GeneralInstance4Channel, @A);
 
-pin_trait!(BreakInputPin, AdvancedInstance4Channel);
-pin_trait!(BreakInput2Pin, AdvancedInstance4Channel);
+pin_trait!(TimerComplementaryPin, AdvancedInstance4Channel, TimerChannel, @A);
 
-pin_trait!(BreakInputComparator1Pin, AdvancedInstance4Channel);
-pin_trait!(BreakInputComparator2Pin, AdvancedInstance4Channel);
+pin_trait!(BreakInputPin, AdvancedInstance4Channel, BreakInput, @A);
 
-pin_trait!(BreakInput2Comparator1Pin, AdvancedInstance4Channel);
-pin_trait!(BreakInput2Comparator2Pin, AdvancedInstance4Channel);
+pin_trait!(BreakInputComparator1Pin, AdvancedInstance4Channel, BreakInput, @A);
+pin_trait!(BreakInputComparator2Pin, AdvancedInstance4Channel, BreakInput, @A);
 
 // Update Event trigger DMA for every timer
 dma_trait!(UpDma, BasicInstance);
 
-dma_trait!(Ch1Dma, GeneralInstance4Channel);
-dma_trait!(Ch2Dma, GeneralInstance4Channel);
-dma_trait!(Ch3Dma, GeneralInstance4Channel);
-dma_trait!(Ch4Dma, GeneralInstance4Channel);
+dma_trait!(Dma, GeneralInstance4Channel, TimerChannel);
 
 #[allow(unused)]
 macro_rules! impl_core_timer {
diff --git a/embassy-stm32/src/timer/one_pulse.rs b/embassy-stm32/src/timer/one_pulse.rs
index 933165ef9..a75b41bd7 100644
--- a/embassy-stm32/src/timer/one_pulse.rs
+++ b/embassy-stm32/src/timer/one_pulse.rs
@@ -7,16 +7,15 @@ use core::pin::Pin;
 use core::task::{Context, Poll};
 
 use super::low_level::{
-    CountingMode, FilterValue, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource,
-};
-use super::{
-    CaptureCompareInterruptHandler, Channel, Channel1Pin, Channel2Pin, ExternalTriggerPin, GeneralInstance4Channel,
+    CountingMode, FilterValue, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource as Ts,
 };
+use super::{CaptureCompareInterruptHandler, Channel, ExternalTriggerPin, GeneralInstance4Channel, TimerPin};
 pub use super::{Ch1, Ch2};
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::pac::timer::vals::Etp;
 use crate::time::Hertz;
+use crate::timer::TimerChannel;
 use crate::Peri;
 
 /// External input marker type.
@@ -44,28 +43,46 @@ impl From<ExternalTriggerPolarity> for Etp {
 ///
 /// This wraps a pin to make it usable as a timer trigger.
 pub struct TriggerPin<'d, T, C> {
-    _pin: Peri<'d, AnyPin>,
+    #[allow(unused)]
+    pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
 
-macro_rules! channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: GeneralInstance4Channel> TriggerPin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " trigger pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, pull: Pull) -> Self {
-                pin.set_as_af(pin.af_num(), AfType::input(pull));
-                TriggerPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+trait SealedTriggerSource {}
+
+/// Marker trait for a trigger source.
+#[expect(private_bounds)]
+pub trait TriggerSource: SealedTriggerSource {}
+
+impl TriggerSource for Ch1 {}
+impl TriggerSource for Ch2 {}
+impl TriggerSource for Ext {}
+
+impl SealedTriggerSource for Ch1 {}
+impl SealedTriggerSource for Ch2 {}
+impl SealedTriggerSource for Ext {}
+
+impl<'d, T: GeneralInstance4Channel, C: TriggerSource + TimerChannel> TriggerPin<'d, T, C> {
+    /// Create a new Channel trigger pin instance.
+    pub fn new<#[cfg(afio)] A>(pin: Peri<'d, if_afio!(impl TimerPin<T, C, A>)>, pull: Pull) -> Self {
+        set_as_af!(pin, AfType::input(pull));
+        TriggerPin {
+            pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
+    }
 }
 
-channel_impl!(new_ch1, Ch1, Channel1Pin);
-channel_impl!(new_ch2, Ch2, Channel2Pin);
-channel_impl!(new_ext, Ext, ExternalTriggerPin);
+impl<'d, T: GeneralInstance4Channel> TriggerPin<'d, T, Ext> {
+    /// Create a new external trigger pin instance.
+    pub fn new_external<#[cfg(afio)] A>(pin: Peri<'d, if_afio!(impl ExternalTriggerPin<T, A>)>, pull: Pull) -> Self {
+        set_as_af!(pin, AfType::input(pull));
+        TriggerPin {
+            pin: pin.into(),
+            phantom: PhantomData,
+        }
+    }
+}
 
 /// One pulse driver.
 ///
@@ -79,9 +96,10 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     ///
     /// The pulse is triggered by a channel 1 input pin on both rising and
     /// falling edges. Channel 1 will unusable as an output.
+    #[allow(unused)]
     pub fn new_ch1_edge_detect(
         tim: Peri<'d, T>,
-        _pin: TriggerPin<'d, T, Ch1>,
+        pin: TriggerPin<'d, T, Ch1>,
         _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
         freq: Hertz,
         pulse_end: u32,
@@ -89,7 +107,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     ) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
-        this.inner.set_trigger_source(TriggerSource::TI1F_ED);
+        this.inner.set_trigger_source(Ts::TI1F_ED);
         this.inner
             .set_input_ti_selection(Channel::Ch1, InputTISelection::Normal);
         this.inner
@@ -114,7 +132,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     ) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
-        this.inner.set_trigger_source(TriggerSource::TI1FP1);
+        this.inner.set_trigger_source(Ts::TI1FP1);
         this.inner
             .set_input_ti_selection(Channel::Ch1, InputTISelection::Normal);
         this.inner
@@ -131,7 +149,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     /// as an output.
     pub fn new_ch2(
         tim: Peri<'d, T>,
-        _pin: TriggerPin<'d, T, Ch1>,
+        _pin: TriggerPin<'d, T, Ch2>,
         _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
         freq: Hertz,
         pulse_end: u32,
@@ -140,7 +158,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     ) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
-        this.inner.set_trigger_source(TriggerSource::TI2FP2);
+        this.inner.set_trigger_source(Ts::TI2FP2);
         this.inner
             .set_input_ti_selection(Channel::Ch2, InputTISelection::Normal);
         this.inner
@@ -172,7 +190,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
             // No filtering
             r.set_etf(FilterValue::NO_FILTER);
         });
-        this.inner.set_trigger_source(TriggerSource::ETRF);
+        this.inner.set_trigger_source(Ts::ETRF);
         this.new_inner(freq, pulse_end, counting_mode);
 
         this
diff --git a/embassy-stm32/src/timer/pwm_input.rs b/embassy-stm32/src/timer/pwm_input.rs
index 98b798634..159b5a177 100644
--- a/embassy-stm32/src/timer/pwm_input.rs
+++ b/embassy-stm32/src/timer/pwm_input.rs
@@ -1,12 +1,16 @@
 //! PWM Input driver.
 
 use super::low_level::{CountingMode, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource};
-use super::{Channel, Channel1Pin, Channel2Pin, GeneralInstance4Channel};
+use super::{Ch1, Ch2, Channel, GeneralInstance4Channel, TimerPin};
 use crate::gpio::{AfType, Pull};
 use crate::time::Hertz;
 use crate::Peri;
 
 /// PWM Input driver.
+///
+/// Only works with CH1 or CH2
+/// Note: Not all timer peripherals are supported
+/// Double check your chips reference manual
 pub struct PwmInput<'d, T: GeneralInstance4Channel> {
     channel: Channel,
     inner: Timer<'d, T>,
@@ -14,15 +18,25 @@ pub struct PwmInput<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
     /// Create a new PWM input driver.
-    pub fn new(tim: Peri<'d, T>, pin: Peri<'d, impl Channel1Pin<T>>, pull: Pull, freq: Hertz) -> Self {
-        pin.set_as_af(pin.af_num(), AfType::input(pull));
+    pub fn new_ch1<#[cfg(afio)] A>(
+        tim: Peri<'d, T>,
+        pin: Peri<'d, if_afio!(impl TimerPin<T, Ch1, A>)>,
+        pull: Pull,
+        freq: Hertz,
+    ) -> Self {
+        set_as_af!(pin, AfType::input(pull));
 
         Self::new_inner(tim, freq, Channel::Ch1, Channel::Ch2)
     }
 
     /// Create a new PWM input driver.
-    pub fn new_alt(tim: Peri<'d, T>, pin: Peri<'d, impl Channel2Pin<T>>, pull: Pull, freq: Hertz) -> Self {
-        pin.set_as_af(pin.af_num(), AfType::input(pull));
+    pub fn new_ch2<#[cfg(afio)] A>(
+        tim: Peri<'d, T>,
+        pin: Peri<'d, if_afio!(impl TimerPin<T, Ch2, A>)>,
+        pull: Pull,
+        freq: Hertz,
+    ) -> Self {
+        set_as_af!(pin, AfType::input(pull));
 
         Self::new_inner(tim, freq, Channel::Ch2, Channel::Ch1)
     }
@@ -37,6 +51,7 @@ impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
 
         // Configuration steps from ST RM0390 (STM32F446) chapter 17.3.6
         // or ST RM0008 (STM32F103) chapter 15.3.6 Input capture mode
+        // or ST RM0440 (STM32G4) chapter 30.4.8 PWM input mode
         inner.set_input_ti_selection(ch1, InputTISelection::Normal);
         inner.set_input_capture_mode(ch1, InputCaptureMode::Rising);
 
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index f3c81667c..82b5968b0 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -6,8 +6,9 @@ use stm32_metapac::timer::vals;
 
 use super::low_level::Timer;
 pub use super::{Ch1, Ch2};
-use super::{Channel1Pin, Channel2Pin, GeneralInstance4Channel};
+use super::{GeneralInstance4Channel, TimerPin};
 use crate::gpio::{AfType, AnyPin, Pull};
+use crate::timer::TimerChannel;
 use crate::Peri;
 
 /// Counting direction
@@ -19,31 +20,37 @@ pub enum Direction {
 }
 
 /// Wrapper for using a pin with QEI.
-pub struct QeiPin<'d, T, Channel> {
-    _pin: Peri<'d, AnyPin>,
-    phantom: PhantomData<(T, Channel)>,
+pub struct QeiPin<'d, T, Channel, #[cfg(afio)] A> {
+    #[allow(unused)]
+    pin: Peri<'d, AnyPin>,
+    phantom: PhantomData<if_afio!((T, Channel, A))>,
 }
 
-macro_rules! channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: GeneralInstance4Channel> QeiPin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " QEI pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(pin.af_num(), AfType::input(Pull::None));
-                });
-                QeiPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+impl<'d, T: GeneralInstance4Channel, C: QeiChannel, #[cfg(afio)] A> if_afio!(QeiPin<'d, T, C, A>) {
+    /// Create a new QEI pin instance.
+    pub fn new(pin: Peri<'d, if_afio!(impl TimerPin<T, C, A>)>) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            set_as_af!(pin, AfType::input(Pull::None));
+        });
+        QeiPin {
+            pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
+    }
 }
 
-channel_impl!(new_ch1, Ch1, Channel1Pin);
-channel_impl!(new_ch2, Ch2, Channel2Pin);
+trait SealedQeiChannel: TimerChannel {}
+
+/// Marker trait for a timer channel eligible for use with QEI.
+#[expect(private_bounds)]
+pub trait QeiChannel: SealedQeiChannel {}
+
+impl QeiChannel for Ch1 {}
+impl QeiChannel for Ch2 {}
+
+impl SealedQeiChannel for Ch1 {}
+impl SealedQeiChannel for Ch2 {}
 
 /// Quadrature decoder driver.
 pub struct Qei<'d, T: GeneralInstance4Channel> {
@@ -52,7 +59,12 @@ pub struct Qei<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> Qei<'d, T> {
     /// Create a new quadrature decoder driver.
-    pub fn new(tim: Peri<'d, T>, _ch1: QeiPin<'d, T, Ch1>, _ch2: QeiPin<'d, T, Ch2>) -> Self {
+    #[allow(unused)]
+    pub fn new<#[cfg(afio)] A>(
+        tim: Peri<'d, T>,
+        ch1: if_afio!(QeiPin<'d, T, Ch1, A>),
+        ch2: if_afio!(QeiPin<'d, T, Ch2, A>),
+    ) -> Self {
         Self::new_inner(tim)
     }
 
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 8fd7e8df4..e6165e42b 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -4,28 +4,20 @@ use core::marker::PhantomData;
 use core::mem::ManuallyDrop;
 
 use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer};
-use super::{Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin, GeneralInstance4Channel, TimerBits};
+use super::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance4Channel, TimerBits, TimerChannel, TimerPin};
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::time::Hertz;
 use crate::Peri;
 
-/// Channel 1 marker type.
-pub enum Ch1 {}
-/// Channel 2 marker type.
-pub enum Ch2 {}
-/// Channel 3 marker type.
-pub enum Ch3 {}
-/// Channel 4 marker type.
-pub enum Ch4 {}
-
 /// PWM pin wrapper.
 ///
 /// This wraps a pin to make it usable with PWM.
-pub struct PwmPin<'d, T, C> {
-    _pin: Peri<'d, AnyPin>,
-    phantom: PhantomData<(T, C)>,
+pub struct PwmPin<'d, T, C, #[cfg(afio)] A> {
+    #[allow(unused)]
+    pub(crate) pin: Peri<'d, AnyPin>,
+    phantom: PhantomData<if_afio!((T, C, A))>,
 }
 
 /// PWM pin config
@@ -43,46 +35,37 @@ pub struct PwmPinConfig {
     pub pull: Pull,
 }
 
-macro_rules! channel_impl {
-    ($new_chx:ident, $new_chx_with_config:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: GeneralInstance4Channel> PwmPin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, output_type: OutputType) -> Self {
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(pin.af_num(), AfType::output(output_type, Speed::VeryHigh));
-                });
-                PwmPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
-
-            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance with config.")]
-            pub fn $new_chx_with_config(pin: Peri<'d, impl $pin_trait<T>>, pin_config: PwmPinConfig) -> Self {
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        #[cfg(gpio_v1)]
-                        AfType::output(pin_config.output_type, pin_config.speed),
-                        #[cfg(gpio_v2)]
-                        AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull),
-                    );
-                });
-                PwmPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+impl<'d, T: GeneralInstance4Channel, C: TimerChannel, #[cfg(afio)] A> if_afio!(PwmPin<'d, T, C, A>) {
+    /// Create a new PWM pin instance.
+    pub fn new(pin: Peri<'d, if_afio!(impl TimerPin<T, C, A>)>, output_type: OutputType) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            set_as_af!(pin, AfType::output(output_type, Speed::VeryHigh));
+        });
+        PwmPin {
+            pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
-}
+    }
 
-channel_impl!(new_ch1, new_ch1_with_config, Ch1, Channel1Pin);
-channel_impl!(new_ch2, new_ch2_with_config, Ch2, Channel2Pin);
-channel_impl!(new_ch3, new_ch3_with_config, Ch3, Channel3Pin);
-channel_impl!(new_ch4, new_ch4_with_config, Ch4, Channel4Pin);
+    /// Create a new PWM pin instance with a specific configuration.
+    pub fn new_with_config(pin: Peri<'d, if_afio!(impl TimerPin<T, C, A>)>, pin_config: PwmPinConfig) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            #[cfg(gpio_v1)]
+            set_as_af!(pin, AfType::output(pin_config.output_type, pin_config.speed));
+            #[cfg(gpio_v2)]
+            set_as_af!(
+                pin,
+                AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull)
+            );
+        });
+        PwmPin {
+            pin: pin.into(),
+            phantom: PhantomData,
+        }
+    }
+}
 
 /// A single channel of a pwm, obtained from [`SimplePwm::split`],
 /// [`SimplePwm::channel`], [`SimplePwm::ch1`], etc.
@@ -196,12 +179,13 @@ pub struct SimplePwm<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Create a new simple PWM driver.
-    pub fn new(
+    #[allow(unused)]
+    pub fn new<#[cfg(afio)] A>(
         tim: Peri<'d, T>,
-        _ch1: Option<PwmPin<'d, T, Ch1>>,
-        _ch2: Option<PwmPin<'d, T, Ch2>>,
-        _ch3: Option<PwmPin<'d, T, Ch3>>,
-        _ch4: Option<PwmPin<'d, T, Ch4>>,
+        ch1: Option<if_afio!(PwmPin<'d, T, Ch1, A>)>,
+        ch2: Option<if_afio!(PwmPin<'d, T, Ch2, A>)>,
+        ch3: Option<if_afio!(PwmPin<'d, T, Ch3, A>)>,
+        ch4: Option<if_afio!(PwmPin<'d, T, Ch4, A>)>,
         freq: Hertz,
         counting_mode: CountingMode,
     ) -> Self {
@@ -381,109 +365,183 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
             self.inner.enable_update_dma(false);
         }
     }
+
+    /// Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.
+    ///
+    /// This method utilizes the timer's DMA burst transfer capability to update multiple CCRx registers
+    /// in sequence on each update event (UEV). The data is written via the DMAR register using the
+    /// DMA base address (DBA) and burst length (DBL) configured in the DCR register.
+    ///
+    /// The `duty` buffer must be structured as a flattened 2D array in row-major order, where each row
+    /// represents a single update event and each column corresponds to a specific timer channel (starting
+    /// from `starting_channel` up to and including `ending_channel`).
+    ///
+    /// For example, if using channels 1 through 4, a buffer of 4 update steps might look like:
+    ///
+    /// let dma_buf: [u16; 16] = [
+    ///     ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
+    ///     ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
+    ///     ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
+    ///     ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
+    /// ];
+    ///
+    /// Each group of N values (where N = number of channels) is transferred on one update event,
+    /// updating the duty cycles of all selected channels simultaneously.
+    ///
+    /// Note:
+    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    pub async fn waveform_up_multi_channel(
+        &mut self,
+        dma: Peri<'_, impl super::UpDma<T>>,
+        starting_channel: Channel,
+        ending_channel: Channel,
+        duty: &[u16],
+    ) {
+        let cr1_addr = self.inner.regs_gp16().cr1().as_ptr() as u32;
+        let start_ch_index = starting_channel.index();
+        let end_ch_index = ending_channel.index();
+
+        assert!(start_ch_index <= end_ch_index);
+
+        let ccrx_addr = self.inner.regs_gp16().ccr(start_ch_index).as_ptr() as u32;
+        self.inner
+            .regs_gp16()
+            .dcr()
+            .modify(|w| w.set_dba(((ccrx_addr - cr1_addr) / 4) as u8));
+        self.inner
+            .regs_gp16()
+            .dcr()
+            .modify(|w| w.set_dbl((end_ch_index - start_ch_index) as u8));
+
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
+
+        let original_update_dma_state = self.inner.get_update_dma_state();
+        if !original_update_dma_state {
+            self.inner.enable_update_dma(true);
+        }
+
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
+
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr4,
+                ..Default::default()
+            };
+
+            Transfer::new_write(
+                dma,
+                req,
+                duty,
+                self.inner.regs_gp16().dmar().as_ptr() as *mut u16,
+                dma_transfer_option,
+            )
+            .await
+        };
+
+        if !original_update_dma_state {
+            self.inner.enable_update_dma(false);
+        }
+    }
 }
 
-macro_rules! impl_waveform_chx {
-    ($fn_name:ident, $dma_ch:ident, $cc_ch:ident) => {
-        impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
-            /// Generate a sequence of PWM waveform
-            pub async fn $fn_name(&mut self, dma: Peri<'_, impl super::$dma_ch<T>>, duty: &[u16]) {
-                use crate::pac::timer::vals::Ccds;
+impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
+    /// Generate a sequence of PWM waveform
+    pub async fn waveform<C: TimerChannel>(&mut self, dma: Peri<'_, impl super::Dma<T, C>>, duty: &[u16]) {
+        use crate::pac::timer::vals::Ccds;
 
-                #[allow(clippy::let_unit_value)] // eg. stm32f334
-                let req = dma.request();
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
 
-                let cc_channel = Channel::$cc_ch;
+        let cc_channel = C::CHANNEL;
 
-                let original_duty_state = self.channel(cc_channel).current_duty_cycle();
-                let original_enable_state = self.channel(cc_channel).is_enabled();
-                let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ON_UPDATE;
-                let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel);
+        let original_duty_state = self.channel(cc_channel).current_duty_cycle();
+        let original_enable_state = self.channel(cc_channel).is_enabled();
+        let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ON_UPDATE;
+        let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel);
 
-                // redirect CC DMA request onto Update Event
-                if !original_cc_dma_on_update {
-                    self.inner.set_cc_dma_selection(Ccds::ON_UPDATE)
-                }
+        // redirect CC DMA request onto Update Event
+        if !original_cc_dma_on_update {
+            self.inner.set_cc_dma_selection(Ccds::ON_UPDATE)
+        }
 
-                if !original_cc_dma_enabled {
-                    self.inner.set_cc_dma_enable_state(cc_channel, true);
-                }
+        if !original_cc_dma_enabled {
+            self.inner.set_cc_dma_enable_state(cc_channel, true);
+        }
 
-                if !original_enable_state {
-                    self.channel(cc_channel).enable();
-                }
+        if !original_enable_state {
+            self.channel(cc_channel).enable();
+        }
 
-                unsafe {
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
+
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr8,
+                ..Default::default()
+            };
+
+            match self.inner.bits() {
+                TimerBits::Bits16 => {
+                    Transfer::new_write(
+                        dma,
+                        req,
+                        duty,
+                        self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16,
+                        dma_transfer_option,
+                    )
+                    .await
+                }
+                #[cfg(not(any(stm32l0)))]
+                TimerBits::Bits32 => {
                     #[cfg(not(any(bdma, gpdma)))]
-                    use crate::dma::{Burst, FifoThreshold};
-                    use crate::dma::{Transfer, TransferOptions};
-
-                    let dma_transfer_option = TransferOptions {
-                        #[cfg(not(any(bdma, gpdma)))]
-                        fifo_threshold: Some(FifoThreshold::Full),
-                        #[cfg(not(any(bdma, gpdma)))]
-                        mburst: Burst::Incr8,
-                        ..Default::default()
-                    };
-
-                    match self.inner.bits() {
-                        TimerBits::Bits16 => {
-                            Transfer::new_write(
-                                dma,
-                                req,
-                                duty,
-                                self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16,
-                                dma_transfer_option,
-                            )
-                            .await
-                        }
-                        #[cfg(not(any(stm32l0)))]
-                        TimerBits::Bits32 => {
-                            #[cfg(not(any(bdma, gpdma)))]
-                            panic!("unsupported timer bits");
-
-                            #[cfg(any(bdma, gpdma))]
-                            Transfer::new_write(
-                                dma,
-                                req,
-                                duty,
-                                self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32,
-                                dma_transfer_option,
-                            )
-                            .await
-                        }
-                    };
-                };
-
-                // restore output compare state
-                if !original_enable_state {
-                    self.channel(cc_channel).disable();
+                    panic!("unsupported timer bits");
+
+                    #[cfg(any(bdma, gpdma))]
+                    Transfer::new_write(
+                        dma,
+                        req,
+                        duty,
+                        self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32,
+                        dma_transfer_option,
+                    )
+                    .await
                 }
+            };
+        };
+
+        // restore output compare state
+        if !original_enable_state {
+            self.channel(cc_channel).disable();
+        }
 
-                self.channel(cc_channel).set_duty_cycle(original_duty_state);
+        self.channel(cc_channel).set_duty_cycle(original_duty_state);
 
-                // Since DMA is closed before timer Capture Compare Event trigger DMA is turn off,
-                // this can almost always trigger a DMA FIFO error.
-                //
-                // optional TODO:
-                // clean FEIF after disable UDE
-                if !original_cc_dma_enabled {
-                    self.inner.set_cc_dma_enable_state(cc_channel, false);
-                }
+        // Since DMA is closed before timer Capture Compare Event trigger DMA is turn off,
+        // this can almost always trigger a DMA FIFO error.
+        //
+        // optional TODO:
+        // clean FEIF after disable UDE
+        if !original_cc_dma_enabled {
+            self.inner.set_cc_dma_enable_state(cc_channel, false);
+        }
 
-                if !original_cc_dma_on_update {
-                    self.inner.set_cc_dma_selection(Ccds::ON_COMPARE)
-                }
-            }
+        if !original_cc_dma_on_update {
+            self.inner.set_cc_dma_selection(Ccds::ON_COMPARE)
         }
-    };
+    }
 }
 
-impl_waveform_chx!(waveform_ch1, Ch1Dma, Ch1);
-impl_waveform_chx!(waveform_ch2, Ch2Dma, Ch2);
-impl_waveform_chx!(waveform_ch3, Ch3Dma, Ch3);
-impl_waveform_chx!(waveform_ch4, Ch4Dma, Ch4);
-
 impl<'d, T: GeneralInstance4Channel> embedded_hal_1::pwm::ErrorType for SimplePwmChannel<'d, T> {
     type Error = core::convert::Infallible;
 }