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-rw-r--r--examples/stm32h7/src/bin/dac.rs7
1 files changed, 4 insertions, 3 deletions
diff --git a/examples/stm32h7/src/bin/dac.rs b/examples/stm32h7/src/bin/dac.rs
index 821221897..35fd6550f 100644
--- a/examples/stm32h7/src/bin/dac.rs
+++ b/examples/stm32h7/src/bin/dac.rs
@@ -16,10 +16,10 @@ fn main() -> ! {
16 let mut config = Config::default(); 16 let mut config = Config::default();
17 { 17 {
18 use embassy_stm32::rcc::*; 18 use embassy_stm32::rcc::*;
19 config.rcc.hsi = Some(Hsi::Mhz64); 19 config.rcc.hsi = Some(HSIPrescaler::DIV1);
20 config.rcc.csi = true; 20 config.rcc.csi = true;
21 config.rcc.pll_src = PllSource::Hsi;
22 config.rcc.pll1 = Some(Pll { 21 config.rcc.pll1 = Some(Pll {
22 source: PllSource::HSI,
23 prediv: PllPreDiv::DIV4, 23 prediv: PllPreDiv::DIV4,
24 mul: PllMul::MUL50, 24 mul: PllMul::MUL50,
25 divp: Some(PllDiv::DIV2), 25 divp: Some(PllDiv::DIV2),
@@ -27,13 +27,14 @@ fn main() -> ! {
27 divr: None, 27 divr: None,
28 }); 28 });
29 config.rcc.pll2 = Some(Pll { 29 config.rcc.pll2 = Some(Pll {
30 source: PllSource::HSI,
30 prediv: PllPreDiv::DIV4, 31 prediv: PllPreDiv::DIV4,
31 mul: PllMul::MUL50, 32 mul: PllMul::MUL50,
32 divp: Some(PllDiv::DIV8), // 100mhz 33 divp: Some(PllDiv::DIV8), // 100mhz
33 divq: None, 34 divq: None,
34 divr: None, 35 divr: None,
35 }); 36 });
36 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 37 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
37 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 38 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
38 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 39 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
39 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 40 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz