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-rw-r--r--examples/stm32h5/src/bin/eth.rs4
-rw-r--r--examples/stm32h5/src/bin/usb_serial.rs4
-rw-r--r--examples/stm32h7/src/bin/adc.rs7
-rw-r--r--examples/stm32h7/src/bin/camera.rs6
-rw-r--r--examples/stm32h7/src/bin/dac.rs7
-rw-r--r--examples/stm32h7/src/bin/dac_dma.rs7
-rw-r--r--examples/stm32h7/src/bin/eth.rs6
-rw-r--r--examples/stm32h7/src/bin/eth_client.rs6
-rw-r--r--examples/stm32h7/src/bin/fmc.rs6
-rw-r--r--examples/stm32h7/src/bin/low_level_timer_api.rs6
-rw-r--r--examples/stm32h7/src/bin/pwm.rs6
-rw-r--r--examples/stm32h7/src/bin/sdmmc.rs6
-rw-r--r--examples/stm32h7/src/bin/spi.rs6
-rw-r--r--examples/stm32h7/src/bin/spi_dma.rs6
-rw-r--r--examples/stm32h7/src/bin/usb_serial.rs6
15 files changed, 46 insertions, 43 deletions
diff --git a/examples/stm32h5/src/bin/eth.rs b/examples/stm32h5/src/bin/eth.rs
index 6e40f0ac0..5bec9d447 100644
--- a/examples/stm32h5/src/bin/eth.rs
+++ b/examples/stm32h5/src/bin/eth.rs
@@ -43,7 +43,7 @@ async fn main(spawner: Spawner) -> ! {
43 mode: HseMode::BypassDigital, 43 mode: HseMode::BypassDigital,
44 }); 44 });
45 config.rcc.pll1 = Some(Pll { 45 config.rcc.pll1 = Some(Pll {
46 source: PllSource::Hse, 46 source: PllSource::HSE,
47 prediv: PllPreDiv::DIV2, 47 prediv: PllPreDiv::DIV2,
48 mul: PllMul::MUL125, 48 mul: PllMul::MUL125,
49 divp: Some(PllDiv::DIV2), 49 divp: Some(PllDiv::DIV2),
@@ -54,7 +54,7 @@ async fn main(spawner: Spawner) -> ! {
54 config.rcc.apb1_pre = APBPrescaler::DIV1; 54 config.rcc.apb1_pre = APBPrescaler::DIV1;
55 config.rcc.apb2_pre = APBPrescaler::DIV1; 55 config.rcc.apb2_pre = APBPrescaler::DIV1;
56 config.rcc.apb3_pre = APBPrescaler::DIV1; 56 config.rcc.apb3_pre = APBPrescaler::DIV1;
57 config.rcc.sys = Sysclk::Pll1P; 57 config.rcc.sys = Sysclk::PLL1_P;
58 config.rcc.voltage_scale = VoltageScale::Scale0; 58 config.rcc.voltage_scale = VoltageScale::Scale0;
59 let p = embassy_stm32::init(config); 59 let p = embassy_stm32::init(config);
60 info!("Hello World!"); 60 info!("Hello World!");
diff --git a/examples/stm32h5/src/bin/usb_serial.rs b/examples/stm32h5/src/bin/usb_serial.rs
index 3b3c38e17..735826a69 100644
--- a/examples/stm32h5/src/bin/usb_serial.rs
+++ b/examples/stm32h5/src/bin/usb_serial.rs
@@ -30,7 +30,7 @@ async fn main(_spawner: Spawner) {
30 mode: HseMode::BypassDigital, 30 mode: HseMode::BypassDigital,
31 }); 31 });
32 config.rcc.pll1 = Some(Pll { 32 config.rcc.pll1 = Some(Pll {
33 source: PllSource::Hse, 33 source: PllSource::HSE,
34 prediv: PllPreDiv::DIV2, 34 prediv: PllPreDiv::DIV2,
35 mul: PllMul::MUL125, 35 mul: PllMul::MUL125,
36 divp: Some(PllDiv::DIV2), // 250mhz 36 divp: Some(PllDiv::DIV2), // 250mhz
@@ -41,7 +41,7 @@ async fn main(_spawner: Spawner) {
41 config.rcc.apb1_pre = APBPrescaler::DIV4; 41 config.rcc.apb1_pre = APBPrescaler::DIV4;
42 config.rcc.apb2_pre = APBPrescaler::DIV2; 42 config.rcc.apb2_pre = APBPrescaler::DIV2;
43 config.rcc.apb3_pre = APBPrescaler::DIV4; 43 config.rcc.apb3_pre = APBPrescaler::DIV4;
44 config.rcc.sys = Sysclk::Pll1P; 44 config.rcc.sys = Sysclk::PLL1_P;
45 config.rcc.voltage_scale = VoltageScale::Scale0; 45 config.rcc.voltage_scale = VoltageScale::Scale0;
46 let p = embassy_stm32::init(config); 46 let p = embassy_stm32::init(config);
47 47
diff --git a/examples/stm32h7/src/bin/adc.rs b/examples/stm32h7/src/bin/adc.rs
index 4a358a35f..e367827e9 100644
--- a/examples/stm32h7/src/bin/adc.rs
+++ b/examples/stm32h7/src/bin/adc.rs
@@ -14,10 +14,10 @@ async fn main(_spawner: Spawner) {
14 let mut config = Config::default(); 14 let mut config = Config::default();
15 { 15 {
16 use embassy_stm32::rcc::*; 16 use embassy_stm32::rcc::*;
17 config.rcc.hsi = Some(Hsi::Mhz64); 17 config.rcc.hsi = Some(HSIPrescaler::DIV1);
18 config.rcc.csi = true; 18 config.rcc.csi = true;
19 config.rcc.pll_src = PllSource::Hsi;
20 config.rcc.pll1 = Some(Pll { 19 config.rcc.pll1 = Some(Pll {
20 source: PllSource::HSI,
21 prediv: PllPreDiv::DIV4, 21 prediv: PllPreDiv::DIV4,
22 mul: PllMul::MUL50, 22 mul: PllMul::MUL50,
23 divp: Some(PllDiv::DIV2), 23 divp: Some(PllDiv::DIV2),
@@ -25,13 +25,14 @@ async fn main(_spawner: Spawner) {
25 divr: None, 25 divr: None,
26 }); 26 });
27 config.rcc.pll2 = Some(Pll { 27 config.rcc.pll2 = Some(Pll {
28 source: PllSource::HSI,
28 prediv: PllPreDiv::DIV4, 29 prediv: PllPreDiv::DIV4,
29 mul: PllMul::MUL50, 30 mul: PllMul::MUL50,
30 divp: Some(PllDiv::DIV8), // 100mhz 31 divp: Some(PllDiv::DIV8), // 100mhz
31 divq: None, 32 divq: None,
32 divr: None, 33 divr: None,
33 }); 34 });
34 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 35 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
35 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 36 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
36 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 37 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
37 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 38 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
diff --git a/examples/stm32h7/src/bin/camera.rs b/examples/stm32h7/src/bin/camera.rs
index 8195430b2..23ece1c38 100644
--- a/examples/stm32h7/src/bin/camera.rs
+++ b/examples/stm32h7/src/bin/camera.rs
@@ -28,17 +28,17 @@ async fn main(_spawner: Spawner) {
28 let mut config = Config::default(); 28 let mut config = Config::default();
29 { 29 {
30 use embassy_stm32::rcc::*; 30 use embassy_stm32::rcc::*;
31 config.rcc.hsi = Some(Hsi::Mhz64); 31 config.rcc.hsi = Some(HSIPrescaler::DIV1);
32 config.rcc.csi = true; 32 config.rcc.csi = true;
33 config.rcc.pll_src = PllSource::Hsi;
34 config.rcc.pll1 = Some(Pll { 33 config.rcc.pll1 = Some(Pll {
34 source: PllSource::HSI,
35 prediv: PllPreDiv::DIV4, 35 prediv: PllPreDiv::DIV4,
36 mul: PllMul::MUL50, 36 mul: PllMul::MUL50,
37 divp: Some(PllDiv::DIV2), 37 divp: Some(PllDiv::DIV2),
38 divq: Some(PllDiv::DIV8), // 100mhz 38 divq: Some(PllDiv::DIV8), // 100mhz
39 divr: None, 39 divr: None,
40 }); 40 });
41 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 41 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
42 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 42 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
43 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 43 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
44 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 44 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
diff --git a/examples/stm32h7/src/bin/dac.rs b/examples/stm32h7/src/bin/dac.rs
index 821221897..35fd6550f 100644
--- a/examples/stm32h7/src/bin/dac.rs
+++ b/examples/stm32h7/src/bin/dac.rs
@@ -16,10 +16,10 @@ fn main() -> ! {
16 let mut config = Config::default(); 16 let mut config = Config::default();
17 { 17 {
18 use embassy_stm32::rcc::*; 18 use embassy_stm32::rcc::*;
19 config.rcc.hsi = Some(Hsi::Mhz64); 19 config.rcc.hsi = Some(HSIPrescaler::DIV1);
20 config.rcc.csi = true; 20 config.rcc.csi = true;
21 config.rcc.pll_src = PllSource::Hsi;
22 config.rcc.pll1 = Some(Pll { 21 config.rcc.pll1 = Some(Pll {
22 source: PllSource::HSI,
23 prediv: PllPreDiv::DIV4, 23 prediv: PllPreDiv::DIV4,
24 mul: PllMul::MUL50, 24 mul: PllMul::MUL50,
25 divp: Some(PllDiv::DIV2), 25 divp: Some(PllDiv::DIV2),
@@ -27,13 +27,14 @@ fn main() -> ! {
27 divr: None, 27 divr: None,
28 }); 28 });
29 config.rcc.pll2 = Some(Pll { 29 config.rcc.pll2 = Some(Pll {
30 source: PllSource::HSI,
30 prediv: PllPreDiv::DIV4, 31 prediv: PllPreDiv::DIV4,
31 mul: PllMul::MUL50, 32 mul: PllMul::MUL50,
32 divp: Some(PllDiv::DIV8), // 100mhz 33 divp: Some(PllDiv::DIV8), // 100mhz
33 divq: None, 34 divq: None,
34 divr: None, 35 divr: None,
35 }); 36 });
36 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 37 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
37 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 38 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
38 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 39 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
39 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 40 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
diff --git a/examples/stm32h7/src/bin/dac_dma.rs b/examples/stm32h7/src/bin/dac_dma.rs
index 334986a05..e141fc484 100644
--- a/examples/stm32h7/src/bin/dac_dma.rs
+++ b/examples/stm32h7/src/bin/dac_dma.rs
@@ -24,10 +24,10 @@ async fn main(spawner: Spawner) {
24 let mut config = embassy_stm32::Config::default(); 24 let mut config = embassy_stm32::Config::default();
25 { 25 {
26 use embassy_stm32::rcc::*; 26 use embassy_stm32::rcc::*;
27 config.rcc.hsi = Some(Hsi::Mhz64); 27 config.rcc.hsi = Some(HSIPrescaler::DIV1);
28 config.rcc.csi = true; 28 config.rcc.csi = true;
29 config.rcc.pll_src = PllSource::Hsi;
30 config.rcc.pll1 = Some(Pll { 29 config.rcc.pll1 = Some(Pll {
30 source: PllSource::HSI,
31 prediv: PllPreDiv::DIV4, 31 prediv: PllPreDiv::DIV4,
32 mul: PllMul::MUL50, 32 mul: PllMul::MUL50,
33 divp: Some(PllDiv::DIV2), 33 divp: Some(PllDiv::DIV2),
@@ -35,13 +35,14 @@ async fn main(spawner: Spawner) {
35 divr: None, 35 divr: None,
36 }); 36 });
37 config.rcc.pll2 = Some(Pll { 37 config.rcc.pll2 = Some(Pll {
38 source: PllSource::HSI,
38 prediv: PllPreDiv::DIV4, 39 prediv: PllPreDiv::DIV4,
39 mul: PllMul::MUL50, 40 mul: PllMul::MUL50,
40 divp: Some(PllDiv::DIV8), // 100mhz 41 divp: Some(PllDiv::DIV8), // 100mhz
41 divq: None, 42 divq: None,
42 divr: None, 43 divr: None,
43 }); 44 });
44 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 45 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
45 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 46 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
46 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 47 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
47 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 48 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
diff --git a/examples/stm32h7/src/bin/eth.rs b/examples/stm32h7/src/bin/eth.rs
index 81d9c7347..e37d8797b 100644
--- a/examples/stm32h7/src/bin/eth.rs
+++ b/examples/stm32h7/src/bin/eth.rs
@@ -34,18 +34,18 @@ async fn main(spawner: Spawner) -> ! {
34 let mut config = Config::default(); 34 let mut config = Config::default();
35 { 35 {
36 use embassy_stm32::rcc::*; 36 use embassy_stm32::rcc::*;
37 config.rcc.hsi = Some(Hsi::Mhz64); 37 config.rcc.hsi = Some(HSIPrescaler::DIV1);
38 config.rcc.csi = true; 38 config.rcc.csi = true;
39 config.rcc.hsi48 = true; // needed for RNG 39 config.rcc.hsi48 = true; // needed for RNG
40 config.rcc.pll_src = PllSource::Hsi;
41 config.rcc.pll1 = Some(Pll { 40 config.rcc.pll1 = Some(Pll {
41 source: PllSource::HSI,
42 prediv: PllPreDiv::DIV4, 42 prediv: PllPreDiv::DIV4,
43 mul: PllMul::MUL50, 43 mul: PllMul::MUL50,
44 divp: Some(PllDiv::DIV2), 44 divp: Some(PllDiv::DIV2),
45 divq: None, 45 divq: None,
46 divr: None, 46 divr: None,
47 }); 47 });
48 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 48 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
49 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 49 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
50 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 50 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
51 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 51 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
diff --git a/examples/stm32h7/src/bin/eth_client.rs b/examples/stm32h7/src/bin/eth_client.rs
index 338137069..88df53f01 100644
--- a/examples/stm32h7/src/bin/eth_client.rs
+++ b/examples/stm32h7/src/bin/eth_client.rs
@@ -35,18 +35,18 @@ async fn main(spawner: Spawner) -> ! {
35 let mut config = Config::default(); 35 let mut config = Config::default();
36 { 36 {
37 use embassy_stm32::rcc::*; 37 use embassy_stm32::rcc::*;
38 config.rcc.hsi = Some(Hsi::Mhz64); 38 config.rcc.hsi = Some(HSIPrescaler::DIV1);
39 config.rcc.csi = true; 39 config.rcc.csi = true;
40 config.rcc.hsi48 = true; // needed for RNG 40 config.rcc.hsi48 = true; // needed for RNG
41 config.rcc.pll_src = PllSource::Hsi;
42 config.rcc.pll1 = Some(Pll { 41 config.rcc.pll1 = Some(Pll {
42 source: PllSource::HSI,
43 prediv: PllPreDiv::DIV4, 43 prediv: PllPreDiv::DIV4,
44 mul: PllMul::MUL50, 44 mul: PllMul::MUL50,
45 divp: Some(PllDiv::DIV2), 45 divp: Some(PllDiv::DIV2),
46 divq: None, 46 divq: None,
47 divr: None, 47 divr: None,
48 }); 48 });
49 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 49 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
50 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 50 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
51 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 51 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
52 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 52 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
diff --git a/examples/stm32h7/src/bin/fmc.rs b/examples/stm32h7/src/bin/fmc.rs
index cffd47093..54e2c3629 100644
--- a/examples/stm32h7/src/bin/fmc.rs
+++ b/examples/stm32h7/src/bin/fmc.rs
@@ -14,17 +14,17 @@ async fn main(_spawner: Spawner) {
14 let mut config = Config::default(); 14 let mut config = Config::default();
15 { 15 {
16 use embassy_stm32::rcc::*; 16 use embassy_stm32::rcc::*;
17 config.rcc.hsi = Some(Hsi::Mhz64); 17 config.rcc.hsi = Some(HSIPrescaler::DIV1);
18 config.rcc.csi = true; 18 config.rcc.csi = true;
19 config.rcc.pll_src = PllSource::Hsi;
20 config.rcc.pll1 = Some(Pll { 19 config.rcc.pll1 = Some(Pll {
20 source: PllSource::HSI,
21 prediv: PllPreDiv::DIV4, 21 prediv: PllPreDiv::DIV4,
22 mul: PllMul::MUL50, 22 mul: PllMul::MUL50,
23 divp: Some(PllDiv::DIV2), 23 divp: Some(PllDiv::DIV2),
24 divq: Some(PllDiv::DIV8), // 100mhz 24 divq: Some(PllDiv::DIV8), // 100mhz
25 divr: None, 25 divr: None,
26 }); 26 });
27 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 27 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
28 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 28 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
29 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 29 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
30 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 30 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs
index 0355ac073..e4bac8a5a 100644
--- a/examples/stm32h7/src/bin/low_level_timer_api.rs
+++ b/examples/stm32h7/src/bin/low_level_timer_api.rs
@@ -17,18 +17,18 @@ async fn main(_spawner: Spawner) {
17 let mut config = Config::default(); 17 let mut config = Config::default();
18 { 18 {
19 use embassy_stm32::rcc::*; 19 use embassy_stm32::rcc::*;
20 config.rcc.hsi = Some(Hsi::Mhz64); 20 config.rcc.hsi = Some(HSIPrescaler::DIV1);
21 config.rcc.csi = true; 21 config.rcc.csi = true;
22 config.rcc.hsi48 = true; // needed for RNG 22 config.rcc.hsi48 = true; // needed for RNG
23 config.rcc.pll_src = PllSource::Hsi;
24 config.rcc.pll1 = Some(Pll { 23 config.rcc.pll1 = Some(Pll {
24 source: PllSource::HSI,
25 prediv: PllPreDiv::DIV4, 25 prediv: PllPreDiv::DIV4,
26 mul: PllMul::MUL50, 26 mul: PllMul::MUL50,
27 divp: Some(PllDiv::DIV2), 27 divp: Some(PllDiv::DIV2),
28 divq: Some(PllDiv::DIV8), // 100mhz 28 divq: Some(PllDiv::DIV8), // 100mhz
29 divr: None, 29 divr: None,
30 }); 30 });
31 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 31 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
32 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 32 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
33 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 33 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
34 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 34 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
diff --git a/examples/stm32h7/src/bin/pwm.rs b/examples/stm32h7/src/bin/pwm.rs
index 973a10cdd..c55d780a0 100644
--- a/examples/stm32h7/src/bin/pwm.rs
+++ b/examples/stm32h7/src/bin/pwm.rs
@@ -17,17 +17,17 @@ async fn main(_spawner: Spawner) {
17 let mut config = Config::default(); 17 let mut config = Config::default();
18 { 18 {
19 use embassy_stm32::rcc::*; 19 use embassy_stm32::rcc::*;
20 config.rcc.hsi = Some(Hsi::Mhz64); 20 config.rcc.hsi = Some(HSIPrescaler::DIV1);
21 config.rcc.csi = true; 21 config.rcc.csi = true;
22 config.rcc.pll_src = PllSource::Hsi;
23 config.rcc.pll1 = Some(Pll { 22 config.rcc.pll1 = Some(Pll {
23 source: PllSource::HSI,
24 prediv: PllPreDiv::DIV4, 24 prediv: PllPreDiv::DIV4,
25 mul: PllMul::MUL50, 25 mul: PllMul::MUL50,
26 divp: Some(PllDiv::DIV2), 26 divp: Some(PllDiv::DIV2),
27 divq: None, 27 divq: None,
28 divr: None, 28 divr: None,
29 }); 29 });
30 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 30 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
31 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 31 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
32 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 32 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
33 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 33 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
diff --git a/examples/stm32h7/src/bin/sdmmc.rs b/examples/stm32h7/src/bin/sdmmc.rs
index ecb8d6542..be968ff77 100644
--- a/examples/stm32h7/src/bin/sdmmc.rs
+++ b/examples/stm32h7/src/bin/sdmmc.rs
@@ -18,17 +18,17 @@ async fn main(_spawner: Spawner) -> ! {
18 let mut config = Config::default(); 18 let mut config = Config::default();
19 { 19 {
20 use embassy_stm32::rcc::*; 20 use embassy_stm32::rcc::*;
21 config.rcc.hsi = Some(Hsi::Mhz64); 21 config.rcc.hsi = Some(HSIPrescaler::DIV1);
22 config.rcc.csi = true; 22 config.rcc.csi = true;
23 config.rcc.pll_src = PllSource::Hsi;
24 config.rcc.pll1 = Some(Pll { 23 config.rcc.pll1 = Some(Pll {
24 source: PllSource::HSI,
25 prediv: PllPreDiv::DIV4, 25 prediv: PllPreDiv::DIV4,
26 mul: PllMul::MUL50, 26 mul: PllMul::MUL50,
27 divp: Some(PllDiv::DIV2), 27 divp: Some(PllDiv::DIV2),
28 divq: Some(PllDiv::DIV4), // default clock chosen by SDMMCSEL. 200 Mhz 28 divq: Some(PllDiv::DIV4), // default clock chosen by SDMMCSEL. 200 Mhz
29 divr: None, 29 divr: None,
30 }); 30 });
31 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 31 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
32 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 32 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
33 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 33 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
34 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 34 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
diff --git a/examples/stm32h7/src/bin/spi.rs b/examples/stm32h7/src/bin/spi.rs
index f128d4a56..a8db0ff77 100644
--- a/examples/stm32h7/src/bin/spi.rs
+++ b/examples/stm32h7/src/bin/spi.rs
@@ -40,17 +40,17 @@ fn main() -> ! {
40 let mut config = Config::default(); 40 let mut config = Config::default();
41 { 41 {
42 use embassy_stm32::rcc::*; 42 use embassy_stm32::rcc::*;
43 config.rcc.hsi = Some(Hsi::Mhz64); 43 config.rcc.hsi = Some(HSIPrescaler::DIV1);
44 config.rcc.csi = true; 44 config.rcc.csi = true;
45 config.rcc.pll_src = PllSource::Hsi;
46 config.rcc.pll1 = Some(Pll { 45 config.rcc.pll1 = Some(Pll {
46 source: PllSource::HSI,
47 prediv: PllPreDiv::DIV4, 47 prediv: PllPreDiv::DIV4,
48 mul: PllMul::MUL50, 48 mul: PllMul::MUL50,
49 divp: Some(PllDiv::DIV2), 49 divp: Some(PllDiv::DIV2),
50 divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz. 50 divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
51 divr: None, 51 divr: None,
52 }); 52 });
53 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 53 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
54 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 54 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
55 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 55 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
56 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 56 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
diff --git a/examples/stm32h7/src/bin/spi_dma.rs b/examples/stm32h7/src/bin/spi_dma.rs
index d4c0bcdbd..561052e48 100644
--- a/examples/stm32h7/src/bin/spi_dma.rs
+++ b/examples/stm32h7/src/bin/spi_dma.rs
@@ -36,17 +36,17 @@ fn main() -> ! {
36 let mut config = Config::default(); 36 let mut config = Config::default();
37 { 37 {
38 use embassy_stm32::rcc::*; 38 use embassy_stm32::rcc::*;
39 config.rcc.hsi = Some(Hsi::Mhz64); 39 config.rcc.hsi = Some(HSIPrescaler::DIV1);
40 config.rcc.csi = true; 40 config.rcc.csi = true;
41 config.rcc.pll_src = PllSource::Hsi;
42 config.rcc.pll1 = Some(Pll { 41 config.rcc.pll1 = Some(Pll {
42 source: PllSource::HSI,
43 prediv: PllPreDiv::DIV4, 43 prediv: PllPreDiv::DIV4,
44 mul: PllMul::MUL50, 44 mul: PllMul::MUL50,
45 divp: Some(PllDiv::DIV2), 45 divp: Some(PllDiv::DIV2),
46 divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz. 46 divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
47 divr: None, 47 divr: None,
48 }); 48 });
49 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 49 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
50 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 50 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
51 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 51 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
52 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 52 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
diff --git a/examples/stm32h7/src/bin/usb_serial.rs b/examples/stm32h7/src/bin/usb_serial.rs
index c1e5144be..19d77183b 100644
--- a/examples/stm32h7/src/bin/usb_serial.rs
+++ b/examples/stm32h7/src/bin/usb_serial.rs
@@ -23,18 +23,18 @@ async fn main(_spawner: Spawner) {
23 let mut config = Config::default(); 23 let mut config = Config::default();
24 { 24 {
25 use embassy_stm32::rcc::*; 25 use embassy_stm32::rcc::*;
26 config.rcc.hsi = Some(Hsi::Mhz64); 26 config.rcc.hsi = Some(HSIPrescaler::DIV1);
27 config.rcc.csi = true; 27 config.rcc.csi = true;
28 config.rcc.hsi48 = true; // needed for USB 28 config.rcc.hsi48 = true; // needed for USB
29 config.rcc.pll_src = PllSource::Hsi;
30 config.rcc.pll1 = Some(Pll { 29 config.rcc.pll1 = Some(Pll {
30 source: PllSource::HSI,
31 prediv: PllPreDiv::DIV4, 31 prediv: PllPreDiv::DIV4,
32 mul: PllMul::MUL50, 32 mul: PllMul::MUL50,
33 divp: Some(PllDiv::DIV2), 33 divp: Some(PllDiv::DIV2),
34 divq: None, 34 divq: None,
35 divr: None, 35 divr: None,
36 }); 36 });
37 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 37 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
38 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 38 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
39 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 39 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
40 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 40 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
generated by cgit (git 2.34.1) at 2026-04-05 21:18:46 +0000