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-rw-r--r--examples/stm32h7/src/bin/dac_dma.rs7
1 files changed, 4 insertions, 3 deletions
diff --git a/examples/stm32h7/src/bin/dac_dma.rs b/examples/stm32h7/src/bin/dac_dma.rs
index 334986a05..e141fc484 100644
--- a/examples/stm32h7/src/bin/dac_dma.rs
+++ b/examples/stm32h7/src/bin/dac_dma.rs
@@ -24,10 +24,10 @@ async fn main(spawner: Spawner) {
24 let mut config = embassy_stm32::Config::default(); 24 let mut config = embassy_stm32::Config::default();
25 { 25 {
26 use embassy_stm32::rcc::*; 26 use embassy_stm32::rcc::*;
27 config.rcc.hsi = Some(Hsi::Mhz64); 27 config.rcc.hsi = Some(HSIPrescaler::DIV1);
28 config.rcc.csi = true; 28 config.rcc.csi = true;
29 config.rcc.pll_src = PllSource::Hsi;
30 config.rcc.pll1 = Some(Pll { 29 config.rcc.pll1 = Some(Pll {
30 source: PllSource::HSI,
31 prediv: PllPreDiv::DIV4, 31 prediv: PllPreDiv::DIV4,
32 mul: PllMul::MUL50, 32 mul: PllMul::MUL50,
33 divp: Some(PllDiv::DIV2), 33 divp: Some(PllDiv::DIV2),
@@ -35,13 +35,14 @@ async fn main(spawner: Spawner) {
35 divr: None, 35 divr: None,
36 }); 36 });
37 config.rcc.pll2 = Some(Pll { 37 config.rcc.pll2 = Some(Pll {
38 source: PllSource::HSI,
38 prediv: PllPreDiv::DIV4, 39 prediv: PllPreDiv::DIV4,
39 mul: PllMul::MUL50, 40 mul: PllMul::MUL50,
40 divp: Some(PllDiv::DIV8), // 100mhz 41 divp: Some(PllDiv::DIV8), // 100mhz
41 divq: None, 42 divq: None,
42 divr: None, 43 divr: None,
43 }); 44 });
44 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 45 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
45 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 46 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
46 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 47 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
47 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 48 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz