diff options
Diffstat (limited to 'examples/stm32h7/src/bin/pwm.rs')
| -rw-r--r-- | examples/stm32h7/src/bin/pwm.rs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/examples/stm32h7/src/bin/pwm.rs b/examples/stm32h7/src/bin/pwm.rs index 973a10cdd..c55d780a0 100644 --- a/examples/stm32h7/src/bin/pwm.rs +++ b/examples/stm32h7/src/bin/pwm.rs | |||
| @@ -17,17 +17,17 @@ async fn main(_spawner: Spawner) { | |||
| 17 | let mut config = Config::default(); | 17 | let mut config = Config::default(); |
| 18 | { | 18 | { |
| 19 | use embassy_stm32::rcc::*; | 19 | use embassy_stm32::rcc::*; |
| 20 | config.rcc.hsi = Some(Hsi::Mhz64); | 20 | config.rcc.hsi = Some(HSIPrescaler::DIV1); |
| 21 | config.rcc.csi = true; | 21 | config.rcc.csi = true; |
| 22 | config.rcc.pll_src = PllSource::Hsi; | ||
| 23 | config.rcc.pll1 = Some(Pll { | 22 | config.rcc.pll1 = Some(Pll { |
| 23 | source: PllSource::HSI, | ||
| 24 | prediv: PllPreDiv::DIV4, | 24 | prediv: PllPreDiv::DIV4, |
| 25 | mul: PllMul::MUL50, | 25 | mul: PllMul::MUL50, |
| 26 | divp: Some(PllDiv::DIV2), | 26 | divp: Some(PllDiv::DIV2), |
| 27 | divq: None, | 27 | divq: None, |
| 28 | divr: None, | 28 | divr: None, |
| 29 | }); | 29 | }); |
| 30 | config.rcc.sys = Sysclk::Pll1P; // 400 Mhz | 30 | config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz |
| 31 | config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz | 31 | config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz |
| 32 | config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz | 32 | config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz |
| 33 | config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz | 33 | config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz |
