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-rw-r--r--tests/stm32/src/common.rs15
1 files changed, 12 insertions, 3 deletions
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 0a70e6a7e..cb1738154 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -402,9 +402,18 @@ pub fn config() -> Config {
402 #[cfg(feature = "stm32wl55jc")] 402 #[cfg(feature = "stm32wl55jc")]
403 { 403 {
404 use embassy_stm32::rcc::*; 404 use embassy_stm32::rcc::*;
405 config.rcc.mux = ClockSrc::MSI(MSIRange::RANGE32M); 405 config.rcc.hse = Some(Hse {
406 embassy_stm32::pac::RCC.ccipr().modify(|w| { 406 freq: Hertz(32_000_000),
407 w.set_rngsel(0b11); // msi 407 mode: HseMode::Bypass,
408 });
409 config.rcc.mux = ClockSrc::PLL1_R;
410 config.rcc.pll = Some(Pll {
411 source: PLLSource::HSE,
412 prediv: PllPreDiv::DIV2,
413 mul: PllMul::MUL6,
414 divp: None,
415 divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG
416 divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2)
408 }); 417 });
409 } 418 }
410 419