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path: root/tests/stm32/src/common.rs
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* adc: add test for wbaxoviat2025-11-211-0/+1
* tests: disable rtc for h563 on non-stopxoviat2025-11-051-0/+2
* Rustfmt for edition 2024.Dario Nieuwenhuis2025-10-061-1/+1
* Add STM32F1 AFIO remapFabian Wolter2025-09-051-1/+1
* address ci test failureRick Rogers2025-07-251-0/+2
* Updated version of stm32-data and added c071 and c051 into ci.shChris Storah2025-07-231-1/+9
* tests/stm32: fix test for g0 hsi sys_divMarkus Kasten2025-01-171-1/+3
* Add H7 dual core to common and run fmtDion Dokter2024-08-051-2/+2
* Fix testsDion Dokter2024-08-051-0/+18
* stm32/tests: add stm32u0 hil.Dario Nieuwenhuis2024-05-131-0/+24
* stm32: add support for STM32H7[RS] "bootflash line", add HIL tests.Dario Nieuwenhuis2024-05-011-1/+32
* stm32: update metapac. Adds U5 LPDMA, fixes ADC_COMMONs.Dario Nieuwenhuis2024-04-291-3/+3
* Remove ad-hoc fixes for setting the IOSV bit to trueEmilie Burgun2024-03-261-7/+0
* Add async CRYP to test.Caleb Garrett2024-03-121-0/+1
* stm32/rcc: port c0 to new api. Add c0 HSIKER/HSISYS support.Dario Nieuwenhuis2024-03-041-0/+11
* stm32/rcc: port g0 to new api.Dario Nieuwenhuis2024-03-041-0/+13
* stm32/rcc: g4: consistent PllSource, add pll pqr limits, simplify a bit.Dario Nieuwenhuis2024-03-041-1/+1
* stm32: autogenerate mux config for all chips.Dario Nieuwenhuis2024-03-011-24/+23
* stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.Dario Nieuwenhuis2024-02-261-7/+7
* stm32/rcc: port U5 to new API, add all PLLs, all HSE modes.Dario Nieuwenhuis2024-02-231-1/+12
* tests/stm32: add stm32f091rc, stm32h503rb.Dario Nieuwenhuis2024-02-171-1/+57
* stm32/rcc: port F1 to new API.Dario Nieuwenhuis2024-02-131-0/+18
* stm32/rcc: port F3 RCC to new APIDario Nieuwenhuis2024-02-121-0/+18
* tests/stm32: fix h7 wrong smps config.Dario Nieuwenhuis2024-01-201-0/+4
* tests/stm32: add L1 DAC/ADC test.Dario Nieuwenhuis2023-12-081-4/+5
* stm32/test: add stm32f446 (board not in HIL rig yet)Dario Nieuwenhuis2023-11-271-0/+35
* stm32/rcc: unify f2 into f4/f7.Dario Nieuwenhuis2023-11-131-10/+11
* stm32/rcc: fix pll enum naming on f4, f7.Dario Nieuwenhuis2023-11-131-2/+2
* stm32/rcc: unify l0l1 and l4l5.Dario Nieuwenhuis2023-11-131-2/+2
* stm32/rcc: consistent casing and naming for PLL enums.Dario Nieuwenhuis2023-11-131-15/+15
* stm32/rcc: add shared code for hsi48 with crs support.Dario Nieuwenhuis2023-11-051-3/+3
* stm32/rcc: switch to modern api for l0, l1.Dario Nieuwenhuis2023-11-051-12/+14
* stm32/rcc: misc cleanups.Dario Nieuwenhuis2023-10-231-8/+10
* stm32/rcc: merge wb into l4/l5.Dario Nieuwenhuis2023-10-231-0/+6
* stm32/rcc: merge wl into l4/l5.Dario Nieuwenhuis2023-10-231-3/+12
* stm32/tests: add stm32wba52cg, stm32u5a9zjDario Nieuwenhuis2023-10-221-1/+34
* stm32: rename HSI16 -> HSIDario Nieuwenhuis2023-10-221-4/+4
* Merge pull request #2097 from embassy-rs/rcc-no-spaghettiDario Nieuwenhuis2023-10-211-2/+43
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| * stm32/tests: add stm32h753zi, stm32h7a3zi.Dario Nieuwenhuis2023-10-211-2/+43
* | stm32: update metapacxoviat2023-10-201-8/+1
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* stm32/rcc: refactor and unify f4 into f7.Dario Nieuwenhuis2023-10-181-5/+17
* stm32/rcc: refactor f7.Dario Nieuwenhuis2023-10-181-1/+17
* stm32: update metapacxoviat2023-10-171-3/+10
* stm32/tests: add stm32wl hil.Dario Nieuwenhuis2023-10-171-0/+17
* stm32: update metapacxoviat2023-10-161-1/+1
* stm32/rcc: unify L4 and L5.Dario Nieuwenhuis2023-10-161-7/+10
* stm32/rcc: add better support for L4/L4+ differences.Dario Nieuwenhuis2023-10-161-1/+1
* stm32/rcc: port L4 to the "flattened" API like h5/h7.Dario Nieuwenhuis2023-10-151-9/+11
* stm32/rcc: unify L0 and L1.Dario Nieuwenhuis2023-10-111-1/+1
* stm32/rcc: use more PLL etc enums from PAC.Dario Nieuwenhuis2023-10-111-4/+4