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* stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.Dario Nieuwenhuis2024-02-2620-74/+74
* Merge pull request #2583 from OroArmor/tim_pll_clkDario Nieuwenhuis2024-02-254-9/+84
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| * Fix report with the same nameEli Orona2024-02-241-1/+1
| * Move to internal mod and re-export the enumsEli Orona2024-02-244-25/+30
| * Rust fmtEli Orona2024-02-203-7/+5
| * Move compile test to the STM32F334 example.Eli Orona2024-02-202-3/+2
| * Move to a single Mux Struct.Eli Orona2024-02-203-22/+18
| * Move to auto-generated based system.Eli Orona2024-02-163-216/+78
| * Update f013.rsEli Orona2024-02-161-5/+5
| * Fix buildEli Orona2024-02-161-5/+5
| * RustfmtEli Orona2024-02-161-9/+45
| * Update f013.rsEli Orona2024-02-161-18/+27
| * Remove extraneous , in cfgEli Orona2024-02-151-8/+8
| * rustfmtEli Orona2024-02-151-14/+21
| * Clean up register settingEli Orona2024-02-151-95/+23
| * Fix cfg linesEli Orona2024-02-151-2/+3
| * Rust fmt and fix build.Eli Orona2024-02-151-52/+45
| * I believe that this enables the PLL clock input to different TIMs for the STM...Eli Orona2024-02-151-0/+241
* | Merge pull request #2623 from cschuhen/feature/fdcan_pac_cleanupDario Nieuwenhuis2024-02-255-58/+86
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| * | FDCAN: Remove history from comments.Corey Schuhen2024-02-252-2/+2
| * | FDCAN: Don't require internal module for public API.Corey Schuhen2024-02-253-9/+10
| * | FDCAN: Fix some indenting in macrosCorey Schuhen2024-02-251-15/+15
| * | FDCAN: Allow access to buffered senders and receivers.Corey Schuhen2024-02-251-0/+32
| * | FDCAN: Expose some pub types in APICorey Schuhen2024-02-251-4/+8
| * | FDCAN: Remove extra traits from.Corey Schuhen2024-02-251-29/+20
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* | Merge pull request #2606 from embassy-rs/dma-refactorDario Nieuwenhuis2024-02-2412-2150/+1208
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| * | stm32/dma: add AnyChannel, add support for BDMA on H7.Dario Nieuwenhuis2024-02-2412-2150/+1208
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* | Merge pull request #2618 from barnabywalters/g4rccDario Nieuwenhuis2024-02-231-17/+35
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| * | [embassy-stm32] G4 RCC refactor amendments and additionsBarnaby Walters2024-02-231-17/+35
* | | Merge pull request #2597 from fe1es/stm32l0-reset-rtcDario Nieuwenhuis2024-02-231-1/+1
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| * \ \ Merge branch 'main' into stm32l0-reset-rtcDario Nieuwenhuis2024-02-2351-1958/+6622
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* | | | Merge pull request #2617 from embassy-rs/u5-rccDario Nieuwenhuis2024-02-235-359/+311
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| * | | stm32/tests: run stm32u5a5zj from flash due to wrong RAM size in stm32-data.Dario Nieuwenhuis2024-02-232-1/+2
| * | | stm32/rcc: port U5 to new API, add all PLLs, all HSE modes.Dario Nieuwenhuis2024-02-233-358/+309
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* | | Merge pull request #2616 from embassy-rs/h5-stupid-errataDario Nieuwenhuis2024-02-231-5/+12
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| * | | stm32/rcc: workaround nonsense RAM suicide errata on backup domain reset.Dario Nieuwenhuis2024-02-231-5/+12
* | | | Merge pull request #2588 from cschuhen/feature/fdcan_bufferedDario Nieuwenhuis2024-02-2322-1026/+5084
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| * | | Add dep for static_cell to example.Corey Schuhen2024-02-191-0/+1
| * | | Remove the OperatingMode typestatesCorey Schuhen2024-02-186-162/+133
| * | | Add a buffered mode.Corey Schuhen2024-02-172-7/+323
| * | | Clean up and prep for buffered IRQ mode.Corey Schuhen2024-02-171-159/+188
| * | | Move error conversion to peripheral.rsCorey Schuhen2024-02-173-45/+43
| * | | Don't use word Standard for frame format because it can be confused with ID f...Corey Schuhen2024-02-174-17/+17
| * | | Port FDCAN HAL to use PAC directly instead of fdcan crate.Corey Schuhen2024-02-1723-905/+4648
* | | | Merge pull request #2611 from CBJamo/rp2040_i2c_improvementsJames Munns2024-02-224-117/+177
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| * | | | fixup another display -> debugCaleb Jamison2024-02-221-1/+1
| * | | | Fixup comments from JamesCaleb Jamison2024-02-222-6/+4
| * | | | Fixup display -> debugCaleb Jamison2024-02-221-1/+1
| * | | | rp2040 i2c_slave improvementsCaleb Jamison2024-02-221-51/+66
| * | | | Add SetConfig impl to rp2040 i2cCaleb Jamison2024-02-223-67/+114