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	Commit message (Collapse)	Author	Age	Files	Lines
*	stm32: extract busychannel into common api	xoviat	2025-11-25	1	-7/+8
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*	low power: store stop mode for dma channels	xoviat	2025-11-21	1	-7/+9
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*	Rustfmt for edition 2024.	Dario Nieuwenhuis	2025-10-06	1	-2/+2
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*	refactor: make dma implementations match in interface	elagil	2025-09-05	1	-44/+58
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*	stm32/dma: fix packing/unpacking not working.	Dario Nieuwenhuis	2025-07-04	1	-23/+40
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*	stm32/dma: add missing fence on BDMA start.	Dario Nieuwenhuis	2025-07-04	1	-3/+3
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*	Remove Peripheral trait, rename PeripheralRef->Peri.	Dario Nieuwenhuis	2025-03-27	1	-26/+18
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*	Reset complete count global variable on Dma configure	noracarmig	2025-01-26	1	-0/+2
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*	Merge pull request #3704 from CNLHC/pwm_support_gp32	Dario Nieuwenhuis	2025-01-21	1	-15/+29
\|\ \| \| \| \| \| \|	feat: Add 32-bit timer support for waveform function
\| *	refactor: update write DMA transfer function to use separate memory word type	Liu Hancheng	2025-01-05	1	-5/+5
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\| *	refactor: update DMA transfer functions to use separate memory and ↵	Liu Hancheng	2025-01-04	1	-12/+26
\| \| \| \| \| \| \| \|	peripheral sizes
* \|	chore: fix build	elagil	2025-01-03	1	-7/+7
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*	refactor: naming of wait functions	elagil	2024-11-17	1	-2/+2
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*	feat: SAI/ringbuffer add function to wait for any write error	elagil	2024-11-17	1	-0/+7
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*	fix(SAI): disallow start without initial write	elagil	2024-11-16	1	-3/+0
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*	stm32: Automatically clear on WritableRingBuffer start	Alexandros Liarokapis	2024-10-15	1	-1/+2
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*	stm32: fix ringbugger overrun errors due to bad dma wrap-around behavior	Alexandros Liarokapis	2024-10-15	1	-10/+20
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*	overrun at invalid diffs, rename clear to reset, simplify dma_sync method	Alexandros Liarokapis	2024-10-15	1	-2/+2
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*	stm32: initial support for alternative ringbuffer implementation	Alexandros Liarokapis	2024-10-15	1	-4/+0
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*	stm32: Moved comment to match request_stop	Peter Krull	2024-09-19	1	-2/+2
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*	stm32: Added request_pause to DMA, and use it for RingBufferedUartRx	Peter Krull	2024-09-19	1	-2/+52
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*	fix(stm32): enable dma half transfer interrupt for buffereduart	Badr Bouslikhin	2024-09-06	1	-0/+1
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*	Fix dma nvic issues on dual core lines	Alexandros Liarokapis	2024-08-17	1	-0/+9
\| \| \| \| \| \|	This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup. Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration. This ensures that each core will only handle the interrupts of the DMA channels that it uses.
*	Enables half transfer ir when constructing a ReadableDmaRingBuffer	Alexandros Liarokapis	2024-06-23	1	-0/+1
\| \| \| \| \| \| \| \| \| \| \| \| \|	The half transfer irq needs to be enabled in order for the hardware to notify the waker when the transfer is at half. This is needed to ensure no overuns occur when using `ReadableDmaRingBuffer`'s `read_exact`. Otherwise we are only notified when the DMA has completed its cycle and is on its way to start overwriting the data. The docs in the dma_bdma buf module also seem to imply that the half transfer irq must be enabled for proper operation. The only consumers of the `ReadableDmaRingBuffer` api are the sai module and the `RingBufferedUartRx`. The former enables the irq manually when constructing the transfer options while the latter does not. This may also be the cause for #1441.
*	Use raw slices .len() method instead of unsafe hacks.	Dario Nieuwenhuis	2024-06-13	1	-10/+6
\| \| \| \|	Stabilized in 1.79.
*	Add async stop() function to stm32 bdma_dma	Tyler Gilbert	2024-03-31	1	-1/+62
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*	Fixed DMA CI build issues.	Caleb Garrett	2024-03-10	1	-52/+39
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*	Add DMA request priority as transfer option.	Caleb Garrett	2024-03-10	1	-5/+58
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*	stm32/dma: add AnyChannel, add support for BDMA on H7.	Dario Nieuwenhuis	2024-02-24	1	-0/+913