| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Enable STM32N6 DMA and I2C clock sources | Lambert Sartory | 2025-12-11 | 1 | -1/+0 |
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| * | GPDMA suspend channel before reset if already enabled | Albin Hedman | 2025-12-03 | 1 | -0/+5 |
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| * | stm32: extract busychannel into common api | xoviat | 2025-11-25 | 2 | -10/+11 |
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| * | low power: store stop mode for dma channels | xoviat | 2025-11-21 | 2 | -9/+14 |
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| * | cfg out unused items | everdrone | 2025-11-11 | 1 | -0/+1 |
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| * | Rustfmt for edition 2024. | Dario Nieuwenhuis | 2025-10-06 | 2 | -3/+3 |
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| * | fix: ping-pong helper DMA direction | Adrian Figueroa | 2025-09-05 | 2 | -8/+21 |
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| * | refactor: make dma implementations match in interface | elagil | 2025-09-05 | 2 | -17/+11 |
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| * | fix: consolidate naming | elagil | 2025-09-05 | 2 | -15/+15 |
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| * | fix: build | elagil | 2025-09-05 | 2 | -86/+29 |
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| * | fix: renamed simple table as per ST nomenclature | etiennecollin | 2025-09-05 | 1 | -4/+4 |
| | | | | | Co-authored-by: elagil <[email protected]> | ||||
| * | fix: removed unnecessary mut reference | etiennecollin | 2025-09-05 | 1 | -3/+3 |
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| * | feat: use register wrappers instead of u32 for LinearItem | etiennecollin | 2025-09-05 | 1 | -15/+12 |
| | | | | | | | | Since the register structs are no-field structs with `repr(transparent)`, we can use them in the LinearItem with `repr(C)`. This allows the user to call the convenient named setter functions for the registers instead of manually changing the bits of the u32. | ||||
| * | feat: add new_with_table() initializer for ring-buffers and removal of ↵ | etiennecollin | 2025-09-05 | 3 | -71/+84 |
| | | | | | | | | | | | | | | | | | RegisterUpdaters - It is now possible to pass a linked-list table to the ring-buffer with the `new_with_table()` function or use the `new()` function for a basic ring-buffer setup. - A `simple_ring_buffer_table()` function was added to the read and write ring-buffers to generate the same table as the one created by `new()` in case the user only wants to customize the default table options. - RegisterUpdaters have been removed as the user now has direct access to the table and its items if needed. See: https://github.com/elagil/embassy/pull/1#issuecomment-2891997294 | ||||
| * | fix: moved channel configuration from new() to start() | etiennecollin | 2025-09-05 | 1 | -6/+4 |
| | | | | | | | See this PR comment explaining why configuration in `new()` is a bad idea: https://github.com/embassy-rs/embassy/pull/3923#issuecomment-2889193736 | ||||
| * | fix: removed functions exposing channel registers | etiennecollin | 2025-09-05 | 2 | -21/+0 |
| | | | | | These functions could be used to cause UB. | ||||
| * | feat: custom dma configuration using RegisterUpdaters struct | etiennecollin | 2025-09-05 | 3 | -7/+51 |
| | | | | | | See this PR comment: https://github.com/embassy-rs/embassy/pull/3923#issuecomment-2889283939 | ||||
| * | fix: suspend before reset | etiennecollin | 2025-09-05 | 1 | -0/+3 |
| | | | | | | This follows the procedure outlined in the STM32U5 reference manual at page 696. | ||||
| * | feat: use provided TransferOptions instead of defaults | etiennecollin | 2025-09-05 | 1 | -4/+4 |
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| * | feat: custom DMA channel configuration | etiennecollin | 2025-09-05 | 2 | -6/+27 |
| | | | | | | | | | | | See https://github.com/embassy-rs/embassy/pull/3923#issuecomment-2888810087 The default configuration of the channel which was done in `start()` is now done in `new()` this allows overriding some settings through the new `get_dma_channel` function. Only ringbuffers support this; `LinkedListTransfer` and `Transfer` do not support that yet. | ||||
| * | fix: writing reserved bits | etiennecollin | 2025-09-05 | 1 | -2/+20 |
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| * | fix: modified dma channel state management | etiennecollin | 2025-09-05 | 2 | -43/+77 |
| | | | | | | See https://github.com/embassy-rs/embassy/pull/3923#discussion_r2094570176 | ||||
| * | fix: docstring | elagil | 2025-09-05 | 1 | -1/+1 |
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| * | fix: simplify | elagil | 2025-09-05 | 1 | -18/+5 |
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| * | fix: build issues | elagil | 2025-09-05 | 2 | -17/+13 |
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| * | feat: wip, write buffer in halves | elagil | 2025-09-05 | 1 | -73/+11 |
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| * | chore: change naming | elagil | 2025-09-05 | 2 | -53/+45 |
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| * | fix: wip gpdma | elagil | 2025-09-05 | 2 | -15/+16 |
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| * | fix: load/store ordering | elagil | 2025-09-05 | 2 | -6/+6 |
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| * | fix: read transfer options | elagil | 2025-09-05 | 1 | -12/+7 |
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| * | chore: clean up transfer options | elagil | 2025-09-05 | 3 | -36/+6 |
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| * | fix: transfer options | elagil | 2025-09-05 | 2 | -1/+8 |
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| * | fix: disable half-complete interrupt | elagil | 2025-09-05 | 1 | -2/+2 |
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| * | style: formatting | elagil | 2025-09-05 | 2 | -17/+11 |
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| * | feat: ping-pong buffers | elagil | 2025-09-05 | 3 | -16/+92 |
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| * | feat: gpdma support (wip) | elagil | 2025-09-05 | 3 | -91/+285 |
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| * | feat: GPDAM linked-list + ringbuffer support | elagil | 2025-09-05 | 3 | -0/+1091 |
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