aboutsummaryrefslogtreecommitdiff
path: root/embassy-stm32/src/gpio.rs
Commit message (Collapse)AuthorAgeFilesLines
* fix: stm32l47*/stm32l48* adc analog pin setupRiccardo Arena2025-11-301-1/+5
|
* Reverted adding AnyBinding, removed AnyChannel, removed ability for ↵WillaWillNot2025-11-221-9/+12
| | | | ExtiInput to accept AnyPin and AnyChannel arguments, added ExtiPin trait for all pins which is lost on converstion to AnyPin and contains type-level ExtiChannel information
* add docs for PinNumbereverdrone2025-11-111-0/+5
|
* Merge branch main into n6everdrone2025-11-111-1/+1
|\
| * Rustfmt for edition 2024.Dario Nieuwenhuis2025-10-061-1/+1
| |
* | Calculate RCC frequencieseverdrone2025-09-281-1/+5
| |
* | Use `PinNumber` to accomodate chips with more than 256 pinseverdrone2025-09-211-16/+21
|/
* stm32/afio: make af_num() unavailable in afio chips.Dario Nieuwenhuis2025-09-061-5/+14
|
* stm32/afio: make the A generic param only appear in chips with AFIO.Dario Nieuwenhuis2025-09-051-0/+1
|
* Add STM32F1 AFIO remapFabian Wolter2025-09-051-0/+11
|
* Remove Peripheral trait, rename PeripheralRef->Peri.Dario Nieuwenhuis2025-03-271-27/+16
|
* Update stm32-metapac.Dario Nieuwenhuis2025-01-061-3/+3
|
* chore: fix buildelagil2025-01-031-19/+19
|
* consistently cfg-gate `set_speed`Anatol Ulrich2024-12-191-0/+1
|
* embassy-stm32: make SPI slew rate/speed configurable and change default to ↵Anatol Ulrich2024-12-191-0/+15
| | | | `Medium`
* docs(gpio): fix a typo regarding GPIO speedROMemories2024-06-201-1/+1
|
* stm32/gpio: refactor AfTypeJan Špaček2024-06-161-227/+265
|
* Merge pull request #3002 from honzasp/rcc-infoDario Nieuwenhuis2024-05-301-1/+1
|\ | | | | | | stm32/rcc: replace generated enable/disable code with runtime info
| * stm32/rcc: replace generated enable/disable code with runtime infoJan Špaček2024-05-251-1/+1
| |
* | add set_as_analog to stm32 gpio FlexLucas Granberg2024-05-291-0/+9
|/
* Merge pull request #2943 from joelsa/add-miso-pullupDario Nieuwenhuis2024-05-241-0/+32
|\ | | | | | | Add miso pullup to spi configuration
| * Remove wrong moduloJoël Schulz-Andres2024-05-241-2/+2
| |
| * Remove Speed::Input in order to move it into separate PRJoël Schulz-Ansres2024-05-221-3/+0
| |
| * Cargo formatJoël Schulz-Ansres2024-05-221-11/+7
| |
| * Use ODR register for Pull::Up or DownJoël Schulz-Ansres2024-05-221-10/+12
| |
| * Cargo formatJoël Schulz-Ansres2024-05-151-7/+8
| |
| * Add miso pullup to spi configuration, add input as field for speedJoël Schulz-Ansres2024-05-151-0/+36
| |
* | gpiov1: Do not call set_speed for AFType::InputJoël Schulz-Andres2024-05-241-0/+5
|/ | | | Co-authored-by: Toby Fleming <[email protected]>
* Remove ad-hoc fixes for setting the IOSV bit to trueEmilie Burgun2024-03-261-7/+0
|
* stm32: use private_bounds for sealed traits.Dario Nieuwenhuis2024-03-231-149/+150
|
* stm32/gpio: add missing eh02 InputPin for OutputOpenDrain.Dario Nieuwenhuis2024-03-201-0/+12
|
* FIX: Correct typo in stm32 gpioMichael de Silva2024-02-141-1/+1
|
* stm32/gpio: remove generics.Dario Nieuwenhuis2024-01-221-98/+43
|
* Change GPIO inherent methods back to `&self`.Dario Nieuwenhuis2024-01-101-52/+42
| | | | | | | With the embedded-hal rc3 update I changed them to require `&mut self`, but in retrospect I think `&self` is better, for extra flexibility. This PR reverts the changes from the rc3 update to inherent methods.
* Update embedded-hal to v1.0Dario Nieuwenhuis2024-01-091-21/+0
|
* stm32: more docs.Dario Nieuwenhuis2023-12-181-0/+2
|
* stm32: add some docs.Dario Nieuwenhuis2023-12-181-9/+72
|
* Update embedded-hal to 1.0.0-rc.3Dario Nieuwenhuis2023-12-141-42/+52
|
* Remove nightly and unstable-traits features in preparation for 1.75.Dario Nieuwenhuis2023-11-291-226/+213
|
* stm32/gpio: make port G work on U5.Dario Nieuwenhuis2023-10-231-0/+7
|
* stm32: avoid creating many tiny critical sections in init.Dario Nieuwenhuis2023-10-121-2/+3
| | | | Saves 292 bytes on stm32f0 bilnky with max optimizations (from 3132 to 2840).
* enable clock firstpbert2023-10-121-1/+1
|
* STM32: combine RccPeripherals reset() and enable() to reset_and_enable()pbert2023-10-121-1/+1
|
* stm32/gpio: Implement `eh1::digital::InputPin` for `OutputOpenDrain`Gabriel Górski2023-10-041-0/+12
| | | | Pins in open-drain mode are outputs and inputs simultaneously.
* stm32: centralize enabling pwr, syscfg, flash.Dario Nieuwenhuis2023-09-251-0/+3
|
* Merge pull request #1751 from oro-os/add-pin-drop-docsxoviat2023-08-081-0/+8
|\ | | | | | | stm32: add note about Output/OutputOpenDrain drop behavior
| * stm32: add note about Output/OutputOpenDrain drop behaviorJosh Junon2023-08-061-0/+8
| |
* | embassy-stm32: Misc clippy fixesGrant Miller2023-08-061-9/+18
|/
* rustfmtxoviat2023-07-291-1/+0
|
* stm32/pwm: add output type controlxoviat2023-07-291-0/+15
|
generated by cgit (git 2.34.1) at 2026-04-05 20:19:38 +0000