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path: root/embassy-stm32/src/i2c/v2.rs
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* Merge branch 'main' into mainxoviat2025-12-111-1/+9
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| * low-power: use scoped block stopxoviat2025-12-081-0/+8
| | | | | | | | Co-authored-by: hjeldin <[email protected]>
| * low-power: improve debug logicxoviat2025-12-061-1/+1
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* | stm32/i2c: Add blocking_listenTrAyZeN2025-12-011-16/+49
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* | stm32/i2c: Restrict listen to async I2c modeTrAyZeN2025-12-011-16/+16
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* fix i2c slave RX early termination handlingElias Hanelt2025-11-261-1/+2
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* low_power: remove device busys for wlexoviat2025-11-221-11/+0
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* stm32: Run cargo fmtHybridChild2025-11-131-7/+11
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* stm32/i2c: Implement async DMA for transaction write groupsHybridChild2025-11-131-3/+47
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* stm32/i2c: Fix async write_vectored and restore DMA implementationHybridChild2025-11-131-7/+34
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* stm32/i2c: Run cargo fmtHybridChild2025-11-131-22/+69
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* stm32/i2c: Add comprehensive v2 Master API tests and fix async issuesHybridChild2025-11-131-21/+7
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* stm32/i2c: Fix v2 async transaction implementationHybridChild2025-11-121-108/+153
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* stm32/i2c_v2: Refactor transaction implementationHybridChild2025-11-121-54/+33
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* stm32/i2c_v2: Add initial transaction implementationHybridChild2025-11-121-28/+474
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* Added TXDR flush via TXE set to the drop guard for write_dma_internal_slave; ↵WillaWillNot2025-11-101-1/+8
| | | | factored in remaining DMA transfers for the return values for write_dma_internal_slave and read_dma_internal_slave
* Pause DMA before awaiting DMA not-running at end of I2C target DMA read/write.WillaWillNot2025-11-051-1/+3
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* stm32/stop: move stop_with_rtc into initxoviat2025-11-041-1/+1
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* stm32/low-power: cleanup and improvexoviat2025-11-041-5/+5
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* use DeviceBusy to mark when stop1 or stop2 is unavailable.liebman2025-11-031-0/+10
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* low_power: i2c wakeupliebman2025-11-031-0/+5
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* Rustfmt for edition 2024.Dario Nieuwenhuis2025-10-061-1/+1
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* refactor: make dma implementations match in interfaceelagil2025-09-051-1/+1
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* stm32/i2c: fix failure of subsequent transmissions after NACKFabian Wolter2025-09-021-4/+11
| | | | | | | | | | When a slave responds with a NACK in blocking I²C master mode, all subsequent transmissions send only the address followed immediately by a STOP. This happens because the current implementation sets I2C_CR2.STOP = 1 whenever any error (including a NACK) occurs. As a result, the STOP bit is already set when the next transmission starts. According to the reference manual: "If a NACK is received: […] a STOP condition is automatically sent […]" This bug was not triggered until #4454 was merged.
* wait for STOP flag in blocking_write_vectored as wellMalte Brieske2025-08-131-2/+4
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* wait for STOP flag when writing tooMalte Brieske2025-08-131-2/+4
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* wait for STOPF in blocking readMalte Brieske2025-08-131-0/+1
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* stm32 i2c v2: rename freq to frequencySüha Ünüvar2025-08-081-5/+5
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* i2cSüha Ünüvar2025-08-081-2/+2
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* fix: stm32 i2c slave blocking r/wKnaifhogg2025-07-241-58/+220
| | | | | | | | | | | | | | This fixes an issue where the slave interface would time out when the master goes from a short write to a read (e.g. when accessing memory registers) with a START signal between. The previous implementation would expect the full buffer length to be written before starting to listen to new commands. This also adds debug trace printing which helped during implemention and testing. Places error checking into a function inspired from a C implementation of HAL.
* fix name changejrmoulton2025-06-101-3/+2
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* fmtjrmoulton2025-06-101-1/+1
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* merge new embassy changesjrmoulton2025-06-101-23/+87
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| * fix: Fix for #3888 async I2C read bug for introduced in #3887 in STM32 I2C ↵Fredrik Reinholdsen2025-04-011-3/+9
| | | | | | | | | | | | | | | | | | | | v2 driver In fixing a different timing related bug, #3887, a new bug was introduced causing I2C reads longer than 255 bytes to timeout for some I2C devices, #3888. The issue was caused by incorrect branch order, and poll function being called unnecessarily. Async I2C read poll function now only looks for I2C transfer complete reload (TCR) interrupts, intead of TCR and transfer complete (TC) interrupts, since TC interrupts are not raised when AUTOEND bit is set.
| * stm32/i2c: disable peripheral when changing timingsAaron Griffith2025-02-271-0/+9
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| * Merge pull request #3878 from showier-drastic/i2c-v2-add-nackDario Nieuwenhuis2025-02-171-7/+60
| |\ | | | | | | stm32: i2c-v2: Add error handling
| | * stm32: i2c-v2: Add error handlingShaw Drastin2025-02-121-7/+60
| | | | | | | | | | | | | | | | | | Currently when error occurres, we have to wait for timeout, which is less than ideal. Enable related interrupts, and return Err when error occurres.
| * | fix: Fix for async I2C v2 driver sequential read/write reads. Fixes #3887Fredrik Reinholdsen2025-02-151-12/+10
| |/ | | | | | | | | | | | | | | For I2C devices that support variable length reads, sending chunks of data as long as the master keeps ACK:ing after each received byte, sequential reads will sometimes get out of sync, causing additional reads to return invalid data. This was caused by a delay between awaiting the DMA read and sending the software STOP signal, which may result in the slave to have time to send a byte of data in between, causing potential miss-alignment. This would then cause subsequent reads to return invalid data. Async write-reads now no longer send STOP after the initial write, matching the behaviour of the blocking version.
| * chore: fix buildelagil2025-01-031-3/+3
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* | add stm32 i2c slave examplejrmoulton2024-08-131-13/+13
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* | remove 10 bit supportjrmoulton2024-08-131-110/+22
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* | fix cijrmoulton2024-08-131-1/+1
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* | add drop guard, clear interrupts, fix len returnjrmoulton2024-08-131-3/+8
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* | remove dead code when v1jrmoulton2024-08-131-0/+9
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* | move addr mask impl to be v2 onlyjrmoulton2024-08-131-1/+16
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* | move embedded hal impl to version modules to allow for 10bit addr on v2jrmoulton2024-08-131-0/+88
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* | Add more docsjrmoulton2024-08-131-1/+1
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* | Move slave constructor to v2 modulejrmoulton2024-08-131-0/+21
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* | stm32 i2c slavejrmoulton2024-08-131-38/+404
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* Fix Formatting IssuesJamie Bird2024-06-211-2/+2
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