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path: root/embassy-stm32/src/rcc/bd.rs
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* rcc: ahb/apb -> hclk/pclkxoviat2023-10-151-4/+4
* stm32/rcc: LSE xtal is 32768hz, not 32000hz.Dario Nieuwenhuis2023-10-111-1/+1
* stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.Dario Nieuwenhuis2023-10-111-86/+131
* stm32/rcc: unify L0 and L1.Dario Nieuwenhuis2023-10-111-1/+1
* h7: implement RTC and LSE clock configurationMatt Ickstadt2023-10-061-14/+33
* wpan: re-enable HIL testsxoviat2023-10-031-0/+4
* stm32/rcc: reset backup domain before enabling LSE.Dario Nieuwenhuis2023-10-021-46/+47
* stm32/rtc: use rccperi enablexoviat2023-09-251-5/+0
* stm32: fix bd lsixoviat2023-09-241-6/+7
* fix low-power: APB1 needed for LSEChristian Enderle2023-09-211-0/+5
* stm32: update configure_ls as agreedxoviat2023-09-171-28/+30
* stm32: add stm32wba support.Dario Nieuwenhuis2023-09-161-68/+42
* stm32: add lp to l0xoviat2023-09-141-2/+2
* rcc: more cleanupxoviat2023-09-081-41/+42
* stm32: extract lse/lsi into bd modxoviat2023-09-061-3/+3
* stm32/rcc: add lsi and lse bd abstractionxoviat2023-09-061-2/+74
* stm32/bd: consolidate enable_rtcxoviat2023-08-281-32/+7
* stm32/bd: fix errorsxoviat2023-08-271-4/+12
* rcc/bd: consolidate modxoviat2023-08-271-70/+37
* stm32/bd: allow dead codexoviat2023-08-271-0/+8
* stm32: extract backupdomain into modxoviat2023-08-271-0/+168
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