embassy - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Collapse)	Author	Age	Files	Lines
*	cfg out unused items	everdrone	2025-11-11	1	-2/+6
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*	Merge branch main into n6	everdrone	2025-11-11	1	-7/+33
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\| *	stm32: add backup sram mod	xoviat	2025-11-06	1	-0/+26
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\| *	Rustfmt for edition 2024.	Dario Nieuwenhuis	2025-10-06	1	-2/+2
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\| *	stm32: update metapac, add L4+ to CI.	Dario Nieuwenhuis	2025-09-26	1	-5/+5
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* \|	Add `cfg`s for N6 family in BD	everdrone	2025-09-21	1	-20/+82
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*	fixup! feat(stm32-l): provide a `const` constructor on `rcc::Config`	ROMemories	2025-05-26	1	-0/+1
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*	feat(stm32-l): provide a `const` constructor on `rcc::Config`	ROMemories	2025-05-21	1	-7/+11
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*	chore: fix build	elagil	2025-01-03	1	-2/+2
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*	rcc: enable lse for stm32u0	Christian Enderle	2024-11-22	1	-2/+5
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*	fixed hanging when lse_sysen disabled	Christian Enderle	2024-11-18	1	-1/+3
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*	Enable user to choose to pass lse clock to peripherals	Christian Enderle	2024-11-18	1	-0/+24
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*	Fix dma nvic issues on dual core lines	Alexandros Liarokapis	2024-08-17	1	-0/+2
\| \| \| \| \| \|	This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup. Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration. This ensures that each core will only handle the interrupts of the DMA channels that it uses.
*	Emit cargo:rustc-check-cfg instructions from build.rs	Jan Špaček	2024-05-30	1	-3/+3
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*	stm32: add support for STM32H7[RS] "bootflash line", add HIL tests.	Dario Nieuwenhuis	2024-05-01	1	-6/+7
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*	stm32 H5: LSE low drive mode is not functional	eZio Pan	2024-03-27	1	-0/+2
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*	Merge branch 'main' into stm32l0-reset-rtc	Dario Nieuwenhuis	2024-02-23	1	-5/+12
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\| *	stm32/rcc: workaround nonsense RAM suicide errata on backup domain reset.	Dario Nieuwenhuis	2024-02-23	1	-5/+12
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* \|	stm32/rcc: reset RTC on stm32l0	fe1es	2024-02-19	1	-1/+1
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*	rcc: ahb/apb -> hclk/pclk	xoviat	2023-10-15	1	-4/+4
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*	stm32/rcc: LSE xtal is 32768hz, not 32000hz.	Dario Nieuwenhuis	2023-10-11	1	-1/+1
\| \| \| \|	Fixes #2043
*	stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.	Dario Nieuwenhuis	2023-10-11	1	-86/+131
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*	stm32/rcc: unify L0 and L1.	Dario Nieuwenhuis	2023-10-11	1	-1/+1
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*	h7: implement RTC and LSE clock configuration	Matt Ickstadt	2023-10-06	1	-14/+33
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*	wpan: re-enable HIL tests	xoviat	2023-10-03	1	-0/+4
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*	stm32/rcc: reset backup domain before enabling LSE.	Dario Nieuwenhuis	2023-10-02	1	-46/+47
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*	stm32/rtc: use rccperi enable	xoviat	2023-09-25	1	-5/+0
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*	stm32: fix bd lsi	xoviat	2023-09-24	1	-6/+7
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*	fix low-power: APB1 needed for LSE	Christian Enderle	2023-09-21	1	-0/+5
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*	stm32: update configure_ls as agreed	xoviat	2023-09-17	1	-28/+30
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*	stm32: add stm32wba support.	Dario Nieuwenhuis	2023-09-16	1	-68/+42
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*	stm32: add lp to l0	xoviat	2023-09-14	1	-2/+2
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*	rcc: more cleanup	xoviat	2023-09-08	1	-41/+42
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*	stm32: extract lse/lsi into bd mod	xoviat	2023-09-06	1	-3/+3
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*	stm32/rcc: add lsi and lse bd abstraction	xoviat	2023-09-06	1	-2/+74
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*	stm32/bd: consolidate enable_rtc	xoviat	2023-08-28	1	-32/+7
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*	stm32/bd: fix errors	xoviat	2023-08-27	1	-4/+12
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*	rcc/bd: consolidate mod	xoviat	2023-08-27	1	-70/+37
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*	stm32/bd: allow dead code	xoviat	2023-08-27	1	-0/+8
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*	stm32: extract backupdomain into mod	xoviat	2023-08-27	1	-0/+168