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path: root/embassy-stm32/src/rcc/f013.rs
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* stm32: disable HSI48 if not in useBernát Süli2025-12-191-0/+6
* feat(stm32-f013): provide a `const` constructor on `rcc::Config`ROMemories2025-05-211-5/+11
* stm32: update metapac, cleanup clocks a bit.Dario Nieuwenhuis2025-04-181-6/+0
* Move PLL2/3 config to before PLLMartin Algesten2025-01-241-29/+31
* Fix init order of set_prediv1srcMartin Algesten2025-01-241-10/+9
* Review fixesMartin Algesten2025-01-241-49/+28
* Full RCC support for STM32F107Martin Algesten2025-01-161-3/+109
* chore: fix buildelagil2025-01-031-6/+6
* STM32F0 fix using HSI48 as SYSCLK on devices with CRSFabian Wolter2024-12-141-0/+3
* Fix & RevertBing Wen2024-11-271-0/+1
* Add newBing Wen2024-11-271-18/+11
* Add new feature to enable overclockingBing Wen2024-11-261-6/+12
* Fix dma nvic issues on dual core linesAlexandros Liarokapis2024-08-171-0/+1
* Emit cargo:rustc-check-cfg instructions from build.rsJan Špaček2024-05-301-4/+4
* stm32: remove pointer-to-pointer-to-registers.Dario Nieuwenhuis2024-05-301-1/+1
* stm32: ensure the core runs on HSI clock while setting up rccAurélien Jacobs2024-05-271-9/+15
* stm32: update metapac. Adds U5 LPDMA, fixes ADC_COMMONs.Dario Nieuwenhuis2024-04-291-36/+48
* stm32: autogenerate mux config for all chips.Dario Nieuwenhuis2024-03-011-4/+2
* stm32: update metapac.Dario Nieuwenhuis2024-02-261-0/+1
* :facepalm:Eli Orona2024-02-251-1/+1
* Rust FMTEli Orona2024-02-251-1/+1
* Add `pll1_p_mul_2` clock.Eli Orona2024-02-251-0/+5
* Move to internal mod and re-export the enumsEli Orona2024-02-241-8/+6
* Move to a single Mux Struct.Eli Orona2024-02-201-6/+6
* Move to auto-generated based system.Eli Orona2024-02-161-215/+6
* Update f013.rsEli Orona2024-02-161-5/+5
* Fix buildEli Orona2024-02-161-5/+5
* RustfmtEli Orona2024-02-161-9/+45
* Update f013.rsEli Orona2024-02-161-18/+27
* Remove extraneous , in cfgEli Orona2024-02-151-8/+8
* rustfmtEli Orona2024-02-151-14/+21
* Clean up register settingEli Orona2024-02-151-95/+23
* Fix cfg linesEli Orona2024-02-151-2/+3
* Rust fmt and fix build.Eli Orona2024-02-151-52/+45
* I believe that this enables the PLL clock input to different TIMs for the STM...Eli Orona2024-02-151-0/+241
* stm32/rcc: unify f0, f1, f3.Dario Nieuwenhuis2024-02-141-0/+448