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path: root/embassy-stm32/src/rcc/f247.rs
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* Rustfmt for edition 2024.Dario Nieuwenhuis2025-10-061-2/+2
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* feat(stm32-f247): provide a `const` constructor on `rcc::Config`ROMemories2025-05-211-4/+10
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* stm32: update metapac, cleanup clocks a bit.Dario Nieuwenhuis2025-04-181-1/+0
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* cargo fmtantonello.contini2025-02-251-3/+2
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* simpler configurationantonello.contini2025-02-251-7/+3
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* let user set external i2s clock frequencyantonello.contini2025-02-251-1/+22
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* do not use pllsrc for i2s; added field for plli2ssrc selectionantonello.contini2025-02-251-1/+8
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* set PLLI2SM and plli2s_src f423vinsynth2025-02-021-2/+2
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* set PLLI2S M and SRC for f4 chips which support itvinsynth2025-02-021-0/+5
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* Add newBing Wen2024-11-271-14/+8
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* Add new feature to enable overclockingBing Wen2024-11-261-4/+10
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* Fix dma nvic issues on dual core linesAlexandros Liarokapis2024-08-171-0/+2
| | | | | | This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup. Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration. This ensures that each core will only handle the interrupts of the DMA channels that it uses.
* Merge pull request #2829 from aurelj/stm32-rcc-hsiDario Nieuwenhuis2024-05-211-9/+15
|\ | | | | | | stm32: ensure the core runs on HSI clock while setting up rcc
| * stm32: ensure the core runs on HSI clock while setting up rccAurélien Jacobs2024-04-161-9/+15
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* | Remove redundant dsi_phy: None from rccJoël Schulz-Ansres2024-05-021-2/+0
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* | Add stm32 dsihost driverJoël Schulz-Ansres2024-05-021-1/+4
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* | low power for h5eZio Pan2024-04-281-0/+3
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* stm32: autogenerate mux config for all chips.Dario Nieuwenhuis2024-03-011-1/+9
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* stm32: update metapac.Dario Nieuwenhuis2024-02-261-0/+1
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* stm32/rcc: unify f0, f1, f3.Dario Nieuwenhuis2024-02-141-0/+482