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* | Added ADC support for STM32C0.Timofei Korostelev2025-03-201-0/+3
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* set PLLI2SM and plli2s_src f423vinsynth2025-02-021-2/+2
* set PLLI2S M and SRC for f4 chips which support itvinsynth2025-02-021-0/+5
* Merge pull request #3779 from algesten/fix/f107-rccDario Nieuwenhuis2025-01-241-4/+90
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| * Move PLL2/3 config to before PLLMartin Algesten2025-01-241-29/+31
| * Fix init order of set_prediv1srcMartin Algesten2025-01-241-10/+9
| * Review fixesMartin Algesten2025-01-241-49/+28
| * Full RCC support for STM32F107Martin Algesten2025-01-161-3/+109
* | stm32/rcc: add HSISYS support for g0Markus Kasten2025-01-171-11/+24
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* chore: fix buildelagil2025-01-033-12/+12
* STM32F0 fix using HSI48 as SYSCLK on devices with CRSFabian Wolter2024-12-141-0/+3
* Update STM32U5 OTG HS clock handlingMarvin Drees2024-12-101-0/+29
* Merge pull request #3582 from itswenb/mainDario Nieuwenhuis2024-11-271-0/+1
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| * Add missing clock checkBing Wen2024-11-271-0/+1
* | Merge pull request #3574 from itswenb/mainUlf Lilleengen2024-11-275-41/+39
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| * Fix & RevertBing Wen2024-11-273-1/+4
| * Add newBing Wen2024-11-275-88/+47
| * Add new feature to enable overclockingBing Wen2024-11-265-23/+59
* | rcc: enable lse for stm32u0Christian Enderle2024-11-221-2/+5
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* compute lse and lsi frequency for STM32L and STM32U0 seriesChristian Enderle2024-11-211-2/+6
* fixed hanging when lse_sysen disabledChristian Enderle2024-11-181-1/+3
* Enable user to choose to pass lse clock to peripheralsChristian Enderle2024-11-181-0/+24
* Fix wrong unitJunfeng Liu2024-11-121-1/+1
* RCC: add lsi and lse clock frequency for STM32U5Christian Enderle2024-11-071-2/+6
* RCC: added msik for stm32u5Christian Enderle2024-11-071-6/+36
* fix: STM32U5 RCC fieldselagil2024-11-061-0/+2
* Update nighlty, fix warnings.Dario Nieuwenhuis2024-10-141-3/+7
* Add presence check for OTG_HS peripheral on STM32H7R/S seriesKevin2024-09-221-7/+7
* Add USBPHYC clock configuration for H7RS seriesKevin2024-09-221-1/+31
* Add OTG_HS support for STM32H7R/SKevin2024-09-221-2/+2
* Fix dma nvic issues on dual core linesAlexandros Liarokapis2024-08-1710-1/+15
* Improve shared data placement, require less atomic support and use unsafecell...Dion Dokter2024-08-051-2/+2
* fmtDion Dokter2024-07-091-1/+3
* Make clocks repr C.Dion Dokter2024-07-081-0/+27
* Panic on index-out-of-bounds when releasing RCC nodeDavid Flemström2024-06-291-0/+2
* Avoid accidental copy of static var before creating mut refDavid Flemström2024-06-291-2/+2
* Remove implicit bounds checking from rcc moduleDavid Flemström2024-06-281-10/+20
* stm32/gpio: refactor AfTypeJan Špaček2024-06-161-3/+2
* Emit cargo:rustc-check-cfg instructions from build.rsJan Špaček2024-05-302-7/+7
* Merge pull request #3002 from honzasp/rcc-infoDario Nieuwenhuis2024-05-302-59/+197
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| * stm32/rcc: replace generated enable/disable code with runtime infoJan Špaček2024-05-252-59/+197
* | stm32: remove pointer-to-pointer-to-registers.Dario Nieuwenhuis2024-05-301-1/+1
* | stm32: ensure the core runs on HSI clock while setting up rccAurélien Jacobs2024-05-275-56/+95
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* Merge pull request #2786 from andelf/fix/stm32wl-msi-crashDario Nieuwenhuis2024-05-211-0/+7
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| * Fix crash caused by using higher MSI on STM32WLAndelf2024-04-081-0/+7
* | Merge pull request #2829 from aurelj/stm32-rcc-hsiDario Nieuwenhuis2024-05-211-9/+15
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| * | stm32: ensure the core runs on HSI clock while setting up rccAurélien Jacobs2024-04-161-9/+15
* | | stm32: use funcs for info/state, const for ENABLE_BIT.Dario Nieuwenhuis2024-05-211-2/+3
* | | stm32/rcc: add ClockEnableBit struct.Dario Nieuwenhuis2024-05-201-1/+49
* | | Remove redundant dsi_phy: None from rccJoël Schulz-Ansres2024-05-024-7/+0
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