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* | | Add stm32 dsihost driverJoël Schulz-Ansres2024-05-024-1/+13
* | | stm32: add support for STM32H7[RS] "bootflash line", add HIL tests.Dario Nieuwenhuis2024-05-015-66/+194
* | | stm32: update metapac. Adds U5 LPDMA, fixes ADC_COMMONs.Dario Nieuwenhuis2024-04-291-36/+48
* | | low power for h5eZio Pan2024-04-284-0/+8
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* | Add stm32u0 support.Dario Nieuwenhuis2024-04-143-6/+26
* | Expose RCC enable and disable methodschemicstry2024-04-121-0/+18
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* Fix 'clocok' typo in RCC docsDillon McEwan2024-04-051-1/+1
* stm32 H5: LSE low drive mode is not functionaleZio Pan2024-03-271-0/+2
* stm32: use private_bounds for sealed traits.Dario Nieuwenhuis2024-03-233-34/+36
* Check for CPU_FREQ_BOOSTDominic2024-03-091-1/+8
* Fix incorrect D1CPRE max for STM32H7 RM0468Dominic2024-03-091-1/+1
* update stm32c0 HSI frequencyTomas Barton2024-03-071-1/+1
* stm32/rcc: port c0 to new api. Add c0 HSIKER/HSISYS support.Dario Nieuwenhuis2024-03-041-95/+129
* stm32/rcc: port g0 to new api.Dario Nieuwenhuis2024-03-041-254/+228
* stm32/rcc: g4: consistent PllSource, add pll pqr limits, simplify a bit.Dario Nieuwenhuis2024-03-041-107/+111
* stm32: autogenerate mux config for all chips.Dario Nieuwenhuis2024-03-0110-246/+97
* added FDCANSEL logic for H7Maia2024-02-271-0/+3
* stm32: update metapac.Dario Nieuwenhuis2024-02-265-0/+6
* :facepalm:Eli Orona2024-02-251-1/+1
* Rust FMTEli Orona2024-02-251-1/+1
* Add `pll1_p_mul_2` clock.Eli Orona2024-02-251-0/+5
* stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.Dario Nieuwenhuis2024-02-265-50/+50
* Merge pull request #2583 from OroArmor/tim_pll_clkDario Nieuwenhuis2024-02-252-8/+14
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| * Fix report with the same nameEli Orona2024-02-241-1/+1
| * Move to internal mod and re-export the enumsEli Orona2024-02-242-9/+7
| * Rust fmtEli Orona2024-02-201-1/+1
| * Move to a single Mux Struct.Eli Orona2024-02-202-6/+8
| * Move to auto-generated based system.Eli Orona2024-02-161-215/+6
| * Update f013.rsEli Orona2024-02-161-5/+5
| * Fix buildEli Orona2024-02-161-5/+5
| * RustfmtEli Orona2024-02-161-9/+45
| * Update f013.rsEli Orona2024-02-161-18/+27
| * Remove extraneous , in cfgEli Orona2024-02-151-8/+8
| * rustfmtEli Orona2024-02-151-14/+21
| * Clean up register settingEli Orona2024-02-151-95/+23
| * Fix cfg linesEli Orona2024-02-151-2/+3
| * Rust fmt and fix build.Eli Orona2024-02-151-52/+45
| * I believe that this enables the PLL clock input to different TIMs for the STM...Eli Orona2024-02-151-0/+241
* | Merge pull request #2618 from barnabywalters/g4rccDario Nieuwenhuis2024-02-231-17/+35
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| * | [embassy-stm32] G4 RCC refactor amendments and additionsBarnaby Walters2024-02-231-17/+35
* | | Merge branch 'main' into stm32l0-reset-rtcDario Nieuwenhuis2024-02-232-351/+293
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| * | | stm32/rcc: port U5 to new API, add all PLLs, all HSE modes.Dario Nieuwenhuis2024-02-231-346/+281
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| * | stm32/rcc: workaround nonsense RAM suicide errata on backup domain reset.Dario Nieuwenhuis2024-02-231-5/+12
* | | stm32/rcc: reset RTC on stm32l0fe1es2024-02-191-1/+1
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* | Merge pull request #2579 from barnabywalters/g4rccDario Nieuwenhuis2024-02-161-151/+203
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| * RefinementsBarnaby Walters2024-02-171-35/+32
| * Configured SYSCLK after boost mode, added commentsBarnaby Walters2024-02-161-7/+12
| * Added documentation, fixed and refined boost and flash read latency configBarnaby Walters2024-02-161-30/+39
| * Configured HSI48 if enabled, assert is enabled if chosen as clk48 sourceBarnaby Walters2024-02-161-2/+11
| * Removed redundant HSI48 configurationBarnaby Walters2024-02-161-22/+10