aboutsummaryrefslogtreecommitdiff
path: root/embassy-stm32/src/rcc
Commit message (Expand)AuthorAgeFilesLines
...
| * Removed dangling doc commentsBarnaby Walters2024-02-161-2/+2
| * Commented out currently unused constantsBarnaby Walters2024-02-161-5/+5
| * [embassy-stm32]: started stm32g4 RCC refactorBarnaby Walters2024-02-151-80/+124
* | stm32: update metapac.Dario Nieuwenhuis2024-02-161-1/+1
* | stm32/rcc: unify f0, f1, f3.Dario Nieuwenhuis2024-02-145-523/+135
* | stm32/rcc: port F0 to new API.Dario Nieuwenhuis2024-02-133-159/+195
* | stm32/rcc: port F1 to new API.Dario Nieuwenhuis2024-02-131-153/+219
* | stm32/rcc: some f3 fixes.Dario Nieuwenhuis2024-02-131-2/+3
|/
* stm32/rcc: use h7 sdlevel enum from pac.Dario Nieuwenhuis2024-02-121-21/+6
* stm32/rcc: port F3 RCC to new APIDario Nieuwenhuis2024-02-122-374/+259
* stm32: update metapac.Dario Nieuwenhuis2024-02-102-0/+2
* fix(stm32/h7): use correct unit in vco clock checkBadr Bouslikhin2024-02-061-1/+1
* stm32/rcc: fix more build failures.Dario Nieuwenhuis2024-02-042-1/+5
* stm32/rcc: fix build for some f0 and l4 chips.Dario Nieuwenhuis2024-02-042-12/+39
* stm32: autogenerate clocks struct, enable mux for all chips.Dario Nieuwenhuis2024-02-0212-335/+212
* Migrate STM32WBA to RCCv3Romain Goyet2024-02-021-90/+103
* STM32WBA's high speed external clock has to run at 32 MHzRomain Goyet2024-02-011-6/+8
* Initial FDCAN driver implementation.Corey Schuhen2024-01-311-4/+3
* Add FDCAN clock registers to G4 RCC.Tomasz bla Fortuna2024-01-312-3/+12
* stm32: Add G0 USB RCCDerek Hageman2024-01-051-1/+50
* Fix formatting of commentsTyler Gilbert2024-01-031-4/+4
* Update u5.rsTyler2024-01-031-10/+8
* Update STM32 RCC U5 to support P and Q dividersTyler Gilbert2024-01-031-0/+18
* additional chip variants required more clocksAdin Ackerman2024-01-022-2/+9
* fix g0 being left out of some clock controlsAdin Ackerman2024-01-022-9/+28
* stm32: more docs.Dario Nieuwenhuis2023-12-181-0/+3
* STM32H7: adjust flash latency and programming delay for series in RM0468Oliver Rockstedt2023-12-151-1/+25
* STM32H7: limit max frequency to 520MHz until cpu frequency boost option is im...Oliver Rockstedt2023-12-151-1/+1
* STM32H7: adjust frequency limits for series in RM0468Oliver Rockstedt2023-12-151-1/+8
* STM32H7: Allow PLL1 DIVP of 1 for certain seriesOliver Rockstedt2023-12-151-2/+7
* stm32: update stm32-metapac. Fixes USB on STM32WB.Dario Nieuwenhuis2023-12-082-0/+2
* Merge pull request #2246 from CaptainMaso/adc_f3_v1_1Dario Nieuwenhuis2023-12-082-2/+4
|\
| * Update stm32-metapac.Dario Nieuwenhuis2023-12-082-2/+4
* | stm32/rcc: Add support for HSE Oscillator in stm32g0Carlos Barrales Ruiz2023-12-041-7/+21
* | stm32/rcc: add missing h7 power configBadr Bouslikhin2023-12-021-0/+12
* | stm32/rcc: refactor h7 rm0455,rm0468 and rm0468 power managementBadr Bouslikhin2023-12-021-58/+29
* | stm32/rcc: enable power supply configurability for rm0455 and rm0468Badr Bouslikhin2023-12-021-13/+5
* | stm32/rcc: make h7 rm0399 power supply configurableBadr Bouslikhin2023-12-011-1/+147
|/
* STM32: Remove vestigal build.rs cfgs, add new flashsize_X and package_X cfgs,...Adam Greig2023-11-251-4/+1
* PR feedbackRobertTDowling2023-11-191-2/+2
* stm32h7 ADC: Fix stalled clock in default h7 configRobertTDowling2023-11-151-1/+6
* stm32/rcc: unify f2 into f4/f7.Dario Nieuwenhuis2023-11-133-353/+119
* stm32/rcc: fix pll enum naming on f4, f7.Dario Nieuwenhuis2023-11-131-5/+5
* stm32/rcc: unify l0l1 and l4l5.Dario Nieuwenhuis2023-11-133-324/+250
* stm32/rcc: consistent casing and naming for PLL enums.Dario Nieuwenhuis2023-11-137-64/+64
* check PLL settings before set VOSeZio Pan2023-11-061-10/+8
* stm32/rcc: set highest VOS on some F4s with no overdrive.Dario Nieuwenhuis2023-11-061-0/+8
* stm32/rcc: add shared code for hsi48 with crs support.Dario Nieuwenhuis2023-11-057-113/+93
* stm32/rcc: switch to modern api for l0, l1.Dario Nieuwenhuis2023-11-052-91/+101
* Merge branch 'main' of github.com:embassy-rs/embassy into low-powerxoviat2023-11-041-17/+6
|\
generated by cgit (git 2.34.1) at 2026-04-07 15:20:07 +0000