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path: root/embassy-stm32/src/timer/complementary_pwm.rs
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* refactor with clippyeZio Pan2024-01-061-1/+2
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* stm32/timer: docs.Dario Nieuwenhuis2023-12-191-6/+25
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* stm32: more docs.Dario Nieuwenhuis2023-12-181-0/+2
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* Merge branch 'master' into center-alignDion Dokter2023-10-201-3/+42
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| * STM32: timer enable_output does not take bool, but just enables the outputRalf2023-10-131-1/+1
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| * enable clock firstpbert2023-10-121-1/+1
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| * STM32: combine RccPeripherals reset() and enable() to reset_and_enable()pbert2023-10-121-2/+1
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| * Implemented Pwm trait for complementary pwm from embedded_halrandi2023-10-071-0/+40
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* | Do affect the frequencyDion Dokter2023-10-021-2/+7
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* | stm32: Add the ability to center-align timersDion Dokter2023-10-011-2/+4
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* stm32: allow setting the PWM output polarityAurelien Jacobs2023-08-181-0/+5
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* stm32: allow setting PWM duty cycle to 100%Aurélien Jacobs2023-08-181-2/+2
| | | | | | | | Setting the compare_value to max_compare_value make the PWM output go low when the timer reach the max_compare_value and go high again on the next timer clock, when the value roll back to 0. So to allow a 100% PWM that never goes low, the compare_value must be set to max_compare_value + 1.
* embassy-stm32: Misc clippy fixesGrant Miller2023-08-061-3/+2
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* stm32/pwm: add output type controlxoviat2023-07-291-8/+8
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* stm32/timer: merge pwm module into timer. (#1703)Dario Nieuwenhuis2023-07-281-0/+250
The traits there are applicable to timer use cases other than PWM. It doesn't make sense to keep them separated.