| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rustfmt for edition 2024. | Dario Nieuwenhuis | 2025-10-06 | 1 | -2/+2 |
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| * | Remove manual settings of `composite_with_iads=true` | Eekle | 2024-12-24 | 1 | -7/+0 |
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| * | Update chip from stm32u585ai to stm32u5g9zj and fix pinout | William | 2024-10-28 | 1 | -2/+2 |
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| * | examples/stm32: do not enable vbus detect by default, it doesn't work on all ↵ | Dario Nieuwenhuis | 2024-05-13 | 1 | -0/+4 |
| | | | | | boards. | ||||
| * | Reduce use of the full `futures` crate. | Dario Nieuwenhuis | 2024-04-26 | 1 | -1/+1 |
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| * | usb: remove device_descriptor buffer, store bytes in UsbDevice.inner instead | Adam Greig | 2024-03-23 | 1 | -2/+0 |
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| * | stm32/usb: ensure mux is configured in examples. | Dario Nieuwenhuis | 2024-03-19 | 1 | -0/+1 |
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| * | stm32/usb: merge usb and usb_otg into single module. | Dario Nieuwenhuis | 2024-03-19 | 1 | -4/+4 |
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| * | stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`. | Dario Nieuwenhuis | 2024-02-26 | 1 | -1/+1 |
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| * | stm32/rcc: port U5 to new API, add all PLLs, all HSE modes. | Dario Nieuwenhuis | 2024-02-23 | 1 | -11/+16 |
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| * | Update STM32 RCC U5 to support P and Q dividers | Tyler Gilbert | 2024-01-03 | 1 | -0/+2 |
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| * | ci: use beta, add secondary nightly ci. | Dario Nieuwenhuis | 2023-12-21 | 1 | -1/+0 |
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| * | stm32/rcc: consistent casing and naming for PLL enums. | Dario Nieuwenhuis | 2023-11-13 | 1 | -1/+1 |
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| * | usb: remove msos-descriptor feature. | Dario Nieuwenhuis | 2023-11-08 | 1 | -0/+1 |
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| * | stm32/rcc: add shared code for hsi48 with crs support. | Dario Nieuwenhuis | 2023-11-05 | 1 | -2/+1 |
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| * | stm32: rename HSI16 -> HSI | Dario Nieuwenhuis | 2023-10-22 | 1 | -2/+2 |
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| * | stm32/rcc: use PLL enums from PAC. | Dario Nieuwenhuis | 2023-10-09 | 1 | -3/+3 |
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| * | stm32: u5: implement >55 MHz clock speeds | Will Glynn | 2023-10-05 | 1 | -1/+6 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit allows STM32U5 devices to operate at 160 MHz. On STM32U5, MSIS can run at 48 MHz and HSE can reach 50 MHz. Faster clocks require using PLL1's R output, though PLL1 can serve other functions besides using the R output for the system clock. This commit extracts a public `PllConfig` struct, primarily to place associated constructors on that type, but also with an eye towards enabling the P and Q outputs in a later commit. STM32U5 PLLs have various frequency requirements on each stage: after the `m` prescaler, after the `n` multiplier, and after the `r` divider. This commit implements the associated checks as assertions. This commit fixes clock calculation and PLL register configuration errors in PLL initialization. STM32U5 has a PWR peripheral which can be configured to push Vcore into different voltage ranges. System clocks exceeding 55 MHz require range 2, and system clocks exceeding 110 MHz require range 1. This commit adds `voltage_range` to `Config` and configures PWR as directed. The voltage range implies different performance limits on various clock signals, including inside a PLL. This commit implements voltage range <-> frequency range checks as assertions, and extracts the otherwise-repeated MSIS, HSI16, and HSE initialization into private methods on `Config`. STM32U5 frequencies above 55 MHz require using the PWR EPOD booster. The EPOD booster requires configuring a second `m` term for PLL1, `mboost`, such that it falls in a particular range. (Recall that >50 MHz cannot be reached without PLL1, so there is no scenario where EPOD is needed but PLL1 is not.) This commit configures and enables the EPOD booster automatically as required. | ||||
| * | stm32/otg: add VBUS detection. | Dario Nieuwenhuis | 2023-06-27 | 1 | -1/+3 |
| | | | | | Fixes #1442. | ||||
| * | stm32: move to bind_interrupts | xoviat | 2023-05-24 | 1 | -3/+6 |
| | | | | | disable lora functionality for now | ||||
| * | Fix some typos | Dirk Stolle | 2023-05-08 | 1 | -1/+1 |
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| * | usb: unify ControlHandler+DeviceStateHandler, route all control requests to ↵ | Dario Nieuwenhuis | 2023-02-08 | 1 | -1/+0 |
| | | | | | | | | | all handlers. - Allows classes to handle vendor requests. - Allows classes to use a single handler for multiple interfaces. - Allows classes to access the other events (previously only `reset` was available). | ||||
| * | stm32 otg: add examples. | chemicstry | 2023-01-11 | 1 | -0/+108 |
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