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* adc: allow usage of anyadcchannel for adc4xoviat2025-11-201-1/+1
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* stm32: extract adc4xoviat2025-11-121-9/+12
| | | | extract adc4 into common adc system and add anyInstance trait to cover adc4 and not adc4
* stm32/adc: extract into commonxoviat2025-11-121-7/+9
| | | | add common low-level interface for adc
* adc: remove sample_time from structxoviat2025-11-101-11/+7
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* Rustfmt for edition 2024.Dario Nieuwenhuis2025-10-064-8/+8
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* executor: return error when creating the spawntoken, not when spawning.Dario Nieuwenhuis2025-08-291-1/+1
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* i2c examplesSüha Ünüvar2025-08-081-2/+1
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* Remove Peripheral trait, rename PeripheralRef->Peri.Dario Nieuwenhuis2025-03-271-2/+2
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* stm32u5: Add HSPI example using a flash in memory mapped modeWilliam Spinelli2025-01-071-0/+455
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* stm32: generate singletons only for pins that actually exist.Dario Nieuwenhuis2025-01-071-1/+2
| | | | | | | Before we'd generate all pins Px0..Px15 for each GPIOx port. This changes codegen to only generate singletons for actually-existing pins. (AFs were already previously filtered, so these non-existing pins were already mostly useless)
* fix formattingklownfish2024-12-311-18/+12
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* cleanupklownfish2024-12-271-19/+0
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* Merge branch 'embassy-rs:main' into u5_adcOlof2024-12-272-14/+0
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| * Remove manual settings of `composite_with_iads=true`Eekle2024-12-242-14/+0
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* | add async read for u5 ADC4klownfish2024-12-271-29/+73
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* | Merge branch 'embassy-rs:main' into u5_adcOlof2024-12-186-46/+625
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| * Add support for stm32u595/5a5 OTG_HS in client modeDave Marples2024-12-101-0/+129
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| * Refactor TSC module: Remove redundant 'Tsc' prefixes for improved naming ↵michel2024-11-291-5/+5
| | | | | | | | consistency
| * STM32-TSC: enable discriminating between pins within same TSC group and ↵michel2024-11-291-43/+32
| | | | | | | | improve TSC library in general
| * Update chip from stm32u585ai to stm32u5g9zj and fix pinoutWilliam2024-10-282-3/+3
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| * Fix formatWilliam2024-10-281-2/+1
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| * Add LTDC example for STM32U5G9J-DK2 demo boardWilliam2024-10-252-0/+462
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* | better u5 adc exampleklownfish2024-12-181-23/+44
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* | add example for u5 ADCklownfish2024-09-241-0/+69
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* Update exampleEekle2024-06-301-2/+2
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* fmtEekle2024-06-231-4/+2
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* Add async wait to TSCEekle2024-06-231-2/+10
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* Add example for touch sensitive controllerKarun2024-06-131-0/+89
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* examples/stm32: do not enable vbus detect by default, it doesn't work on all ↵Dario Nieuwenhuis2024-05-131-0/+4
| | | | boards.
* Reduce use of the full `futures` crate.Dario Nieuwenhuis2024-04-261-1/+1
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* stm32/i2c: remove DMA generic params.Dario Nieuwenhuis2024-04-151-17/+1
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* usb: remove device_descriptor buffer, store bytes in UsbDevice.inner insteadAdam Greig2024-03-231-2/+0
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* stm32/usb: ensure mux is configured in examples.Dario Nieuwenhuis2024-03-191-0/+1
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* stm32/usb: merge usb and usb_otg into single module.Dario Nieuwenhuis2024-03-191-4/+4
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* stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.Dario Nieuwenhuis2024-02-261-1/+1
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* stm32/rcc: port U5 to new API, add all PLLs, all HSE modes.Dario Nieuwenhuis2024-02-231-11/+16
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* Merge pull request #2594 from exzachlyvv/zvv/u5-i2cDario Nieuwenhuis2024-02-181-0/+41
|\ | | | | | | Add simple i2c example for u5
| * Add simple i2c example for u5Zach2024-02-181-0/+41
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* | Merge pull request #2591 from exzachlyvv/zvv/u5-flashDario Nieuwenhuis2024-02-181-0/+55
|\ \ | | | | | | | | | support u5 flash
| * | support u5 flashZach2024-02-171-0/+55
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* / u5 - add working rng exampleZach2024-02-171-0/+25
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* Update STM32 RCC U5 to support P and Q dividersTyler Gilbert2024-01-031-0/+2
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* ci: use beta, add secondary nightly ci.Dario Nieuwenhuis2023-12-213-3/+0
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* stm32/rcc: consistent casing and naming for PLL enums.Dario Nieuwenhuis2023-11-131-1/+1
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* usb: remove msos-descriptor feature.Dario Nieuwenhuis2023-11-081-0/+1
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* stm32/rcc: add shared code for hsi48 with crs support.Dario Nieuwenhuis2023-11-051-2/+1
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* stm32: rename HSI16 -> HSIDario Nieuwenhuis2023-10-221-2/+2
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* time: Update examples, tests, and other code to use new Timer::after_x ↵Adam Greig2023-10-151-3/+3
| | | | convenience methods
* stm32/rcc: use PLL enums from PAC.Dario Nieuwenhuis2023-10-091-3/+3
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* stm32: u5: implement >55 MHz clock speedsWill Glynn2023-10-051-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit allows STM32U5 devices to operate at 160 MHz. On STM32U5, MSIS can run at 48 MHz and HSE can reach 50 MHz. Faster clocks require using PLL1's R output, though PLL1 can serve other functions besides using the R output for the system clock. This commit extracts a public `PllConfig` struct, primarily to place associated constructors on that type, but also with an eye towards enabling the P and Q outputs in a later commit. STM32U5 PLLs have various frequency requirements on each stage: after the `m` prescaler, after the `n` multiplier, and after the `r` divider. This commit implements the associated checks as assertions. This commit fixes clock calculation and PLL register configuration errors in PLL initialization. STM32U5 has a PWR peripheral which can be configured to push Vcore into different voltage ranges. System clocks exceeding 55 MHz require range 2, and system clocks exceeding 110 MHz require range 1. This commit adds `voltage_range` to `Config` and configures PWR as directed. The voltage range implies different performance limits on various clock signals, including inside a PLL. This commit implements voltage range <-> frequency range checks as assertions, and extracts the otherwise-repeated MSIS, HSI16, and HSE initialization into private methods on `Config`. STM32U5 frequencies above 55 MHz require using the PWR EPOD booster. The EPOD booster requires configuring a second `m` term for PLL1, `mboost`, such that it falls in a particular range. (Recall that >50 MHz cannot be reached without PLL1, so there is no scenario where EPOD is needed but PLL1 is not.) This commit configures and enables the EPOD booster automatically as required.
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