aboutsummaryrefslogtreecommitdiff
path: root/examples/stm32wl/src
Commit message (Collapse)AuthorAgeFilesLines
* stm32/gpio: remove generics.Dario Nieuwenhuis2024-01-221-3/+2
|
* Change GPIO inherent methods back to `&self`.Dario Nieuwenhuis2024-01-101-1/+1
| | | | | | | With the embedded-hal rc3 update I changed them to require `&mut self`, but in retrospect I think `&self` is better, for extra flexibility. This PR reverts the changes from the rc3 update to inherent methods.
* ci: use beta, add secondary nightly ci.Dario Nieuwenhuis2023-12-217-7/+0
|
* Update embedded-hal to 1.0.0-rc.3Dario Nieuwenhuis2023-12-141-1/+1
|
* Move embassy-lora, lora examples to lora-phy repo.Dario Nieuwenhuis2023-11-293-344/+0
|
* stm32/rcc: consistent casing and naming for PLL enums.Dario Nieuwenhuis2023-11-135-5/+5
|
* Update Rust nightly.Dario Nieuwenhuis2023-11-013-0/+3
|
* stm32/rcc: merge wb into l4/l5.Dario Nieuwenhuis2023-10-235-8/+58
|
* stm32/rcc: merge wl into l4/l5.Dario Nieuwenhuis2023-10-232-9/+36
|
* fix clocks in stm32wl rng example.Dario Nieuwenhuis2023-10-171-5/+4
|
* time: Update examples, tests, and other code to use new Timer::after_x ↵Adam Greig2023-10-153-8/+8
| | | | convenience methods
* stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.Dario Nieuwenhuis2023-10-113-7/+3
|
* stm32/rcc: rename HSE32 to HSEDario Nieuwenhuis2023-10-116-6/+6
|
* stm32/rtc: enable lse in examples.Dario Nieuwenhuis2023-09-301-0/+2
|
* stm32/usart: return error instead of panicking on bad baudrate.Dario Nieuwenhuis2023-09-261-2/+2
|
* Update for rust-lorawan and lora-phy version 2.ceekdee2023-09-243-14/+9
|
* rcc: more cleanupxoviat2023-09-083-3/+2
|
* stm32: fix wl re-exportxoviat2023-08-271-3/+3
|
* stm32/rtc: remove generics and segregate clock selxoviat2023-08-081-4/+1
|
* stm32: fix rtc and examplesxoviat2023-08-061-1/+1
|
* stm32/rng: use bind_interrupts!.Dario Nieuwenhuis2023-07-312-6/+11
|
* Enable RTC on STM32WL chips (#1645)Phil Markgraf2023-07-151-0/+43
| | | | | | | | | | | | | * Add clippy allow to not report if same then branch * Support enabling RTC clock on STM32WL * Add clippy allow to not report if same then branch * Support enabling RTC clock on STM32WL * Add rtc example for stm32wl * Address code review feedback
* stm32: update stm32-metapac.Dario Nieuwenhuis2023-06-192-6/+4
|
* Fix examplesRasmus Melchior Jacobsen2023-05-251-5/+5
|
* Let Flash<Async/Blocking> be a thingRasmus Melchior Jacobsen2023-05-251-1/+1
|
* Align with new bind_interruptRasmus Melchior Jacobsen2023-05-251-2/+2
|
* Align examplesRasmus Melchior Jacobsen2023-05-251-6/+6
|
* Align examplesRasmus Melchior Jacobsen2023-05-251-3/+2
|
* stm32: move lora to bind_interruptsxoviat2023-05-244-21/+30
|
* Update Rust nightly.Dario Nieuwenhuis2023-05-193-3/+0
|
* Fix some typosDirk Stolle2023-05-081-1/+1
|
* Simplify SUBGHZSPI configuration.ceekdee2023-05-043-12/+3
|
* Handle SUBGHZSPI as async.ceekdee2023-05-033-35/+11
|
* Deprecate original LoRa drivers. Update rust-lorawan releases.ceekdee2023-04-251-119/+0
|
* Add lora-phy examples.ceekdee2023-04-234-107/+139
|
* Add external LoRa physical layer functionality.ceekdee2023-04-212-0/+191
|
* Update to rust-lorawan with afit supportUlf Lilleengen2023-04-151-1/+1
|
* Align flash examplesRasmus Melchior Jacobsen2023-04-051-1/+1
|
* Add random examplemiathedev2022-12-041-0/+33
|
* Add uart async examplemiathedev2022-11-011-0/+60
|
* Remove flash lock/unlock public API from stm32 flash, and perform the ↵Mathias2022-09-301-1/+1
| | | | unlocking and locking automatically on erase and write operations
* Remove default, reorder generic paramsivmarkov2022-09-251-1/+2
|
* Update Rust nightly.Dario Nieuwenhuis2022-09-222-2/+0
| | | | Removes feature(generic_associated_types)
* Use LP as defaultUlf Lilleengen2022-08-261-2/+2
|
* lora: Make some options configurableTimo Kröger2022-08-261-1/+3
| | | | | | Call `config()` only once at construction not with every RX and TX operation. The Lora-E5 only supports HP mode, use that instead. The nucleo board supports both HP and LP and should continue to work.
* lora: Use a trait for RF frontend switchingTimo Kröger2022-08-261-1/+27
| | | | | | The Seeed Studio Lora-E5 module only has two control pins. With the `RadioSwitch` trait the user can implement any method required by the module/board to control the TX/RX direction of the radio frontend.
* lora: Improve IRQ handlingTimo Kröger2022-08-261-3/+2
| | | | | | | * Interrupt handler only triggers a waker: Do the actual interrupt processing which involves SUBGHZ SPI coms in the task. * Do not require a static state for the constructor. * Remove unsafe from construcor.
* stm32wl: Do not require external SPI pins for SUBGHZTimo Kröger2022-08-262-2/+2
| | | | For the Seeed Studio Lora-E5 those pins conflict with the radio frontend control GPIOS (PA4 and PA5).
* sync: flatten module structure.Dario Nieuwenhuis2022-08-221-1/+1
|
* split `embassy-util` into `embassy-futures`, `embassy-sync`.Dario Nieuwenhuis2022-08-221-1/+1
|