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* stm32/test: fix race condition in uart_dma.Dario Nieuwenhuis2023-05-011-9/+18
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* stm32/test: cleanup ringbuffer test, exit on success (transferring 100kb)Dario Nieuwenhuis2023-05-011-39/+38
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* stm32/test: add real defmt timestampDario Nieuwenhuis2023-05-012-12/+2
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* stm32/uart: feature-gate ringbuffer out when using gpdma, not supported yet.Dario Nieuwenhuis2023-05-012-7/+15
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* Support overflow detection for more than one ring-periodRasmus Melchior Jacobsen2023-05-012-11/+23
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* Ring-buffered uart rx with one-period overrun detectionRasmus Melchior Jacobsen2023-05-014-0/+252
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* Merge #1376bors[bot]2023-05-012-1/+61
|\ | | | | | | | | | | | | | | 1376: rtc: cleanup and consolidate r=Dirbaio a=xoviat This removes an extra file that I left in, adds an example, and consolidates the files into one 'v2' file. Co-authored-by: xoviat <[email protected]>
| * stm32/rtc: fix datetime and add f4 testxoviat2023-04-252-1/+61
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* | rp/uart: report errors from dma receivepennae2023-05-011-10/+228
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* | rp/uart: report errors from buffered uartpennae2023-05-011-20/+229
| | | | | | | | | | | | | | | | | | this reports errors at the same location the blocking uart would, which works out to being mostly exact (except in the case of overruns, where one extra character is dropped). this is actually easier than going nuclear in the case of errors and nuking both the buffer contents and the rx fifo, both of which are things we'd have to do in addition to what's added here, and neither are needed for correctness.
* | tests/rp: test error conditions for uartpennae2023-05-011-11/+148
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* | tests/rp: fix buffered uart testpennae2023-05-011-3/+3
| | | | | | | | | | | | the rp uart receive fifo is 32 entries deep, so the 31 byte test data fits into it without needing any buffering. extend to 48 bytes to fill the entire fifo and the 16 byte test buffer.
* | Bump versions preparing for -macros and -executor releaseUlf Lilleengen2023-04-274-4/+4
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* | rp: add PWM apipennae2023-04-231-0/+142
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* | rp: hook up softfloat rom intrinsicspennae2023-04-193-3/+58
|/ | | | | | rp-hal has done this very well already, so we'll just copy their entire impl again. only div.rs needed some massaging because our sio access works a little differently, everything else worked as is.
* stm32/sdmmc: add hil test for f4.Dario Nieuwenhuis2023-04-173-1/+234
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* Release embassy-sync v0.2.0Dario Nieuwenhuis2023-04-134-4/+4
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* Move linker flags to build script.Roy Buitenhuis2023-04-112-4/+8
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* RustfmtRoy Buitenhuis2023-04-111-1/+1
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* Add empty test binary for riscvRoy Buitenhuis2023-04-114-0/+85
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* stm32/test: add C0 hil tests.Dario Nieuwenhuis2023-04-117-2/+20
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* stm32/test: add h5 hil tests.Dario Nieuwenhuis2023-04-106-16/+35
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* Update embedded-hal crates.Dario Nieuwenhuis2023-04-062-4/+4
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* Merge #1321bors[bot]2023-04-043-3/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | 1321: executor: add Pender, rework Cargo features. r=Dirbaio a=Dirbaio This introduces a `Pender` struct with enum cases for thread-mode, interrupt-mode and custom callback executors. This avoids calls through function pointers when using only the thread or interrupt executors. Faster, and friendlier to `cargo-call-stack`. `embassy-executor` now has `arch-xxx` Cargo features to select the arch and to enable the builtin executors (thread and interrupt). Co-authored-by: Dario Nieuwenhuis <[email protected]>
| * executor: add Pender, rework Cargo features.Dario Nieuwenhuis2023-04-033-3/+3
| | | | | | | | | | | | | | | | | | This introduces a `Pender` struct with enum cases for thread-mode, interrupt-mode and custom callback executors. This avoids calls through function pointers when using only the thread or interrupt executors. Faster, and friendlier to `cargo-call-stack`. `embassy-executor` now has `arch-xxx` Cargo features to select the arch and to enable the builtin executors (thread and interrupt).
* | Add HIL test for timer on nrfUlf Lilleengen2023-04-031-0/+25
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* fix: spi transfer bug and additions to testLachezar Lechev2023-03-261-3/+23
| | | | Signed-off-by: Lachezar Lechev <[email protected]>
* chore: add spi_async tests for uneven buffersLachezar Lechev2023-03-241-4/+40
| | | | Signed-off-by: Lachezar Lechev <[email protected]>
* Add HIL test for into_buffered uart on embassy-rpMathias2023-03-141-0/+54
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* nrf/uart: switch to new interrupt binding.Dario Nieuwenhuis2023-03-062-7/+16
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* nrf/buffered_uarte: add HIL tests.Dario Nieuwenhuis2023-03-047-0/+464
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* Refactor after reviewkalkyl2022-12-131-0/+47
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* Feature gate critical-section-implkalkyl2022-12-101-1/+1
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* Select critical-section in testskalkyl2022-12-101-1/+1
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* rp: add OutputOpenDrain input test.Dario Nieuwenhuis2022-12-061-3/+25
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* Bump defmt-rtt to 0.4Dario Nieuwenhuis2022-11-292-2/+2
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* rp/uart: use lockfree ringbuffer.Dario Nieuwenhuis2022-11-251-8/+5
| | | | This gets rid of another PeripheralMutex usage.
* Switch to async-fn-in-traitDario Nieuwenhuis2022-11-252-3/+3
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* Add delay to flash test to allow time to parse RTT headerMathias2022-10-271-0/+7
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* Remove unused imports from testMathias2022-10-271-1/+0
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* Rebase on masterMathias2022-10-274-19/+52
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| * stm32: Add support for read_until_idle on UARTGuillaume MICHEL2022-10-262-16/+49
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| * Update Rust nightly.Dario Nieuwenhuis2022-10-262-3/+3
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* | Add flash example & flash HIL testMathias2022-10-262-0/+49
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* all Cargo.toml: Add license to all crate Cargo.toml fileschrysn2022-10-072-0/+2
| | | | Closes: https://github.com/embassy-rs/embassy/issues/1002
* Update embedded-hal versions and explicitly pinUlf Lilleengen2022-09-292-4/+4
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* Fix bufferedUart read and write testsMathias2022-09-271-4/+5
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* Extend buffered-uart test to transmit 32 bytesMathias2022-09-271-2/+8
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* rp: set correct teleprobe target for rpi-pico tests.Dario Nieuwenhuis2022-09-261-1/+1
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* Add HIL test for bufferedUartMathias2022-09-262-0/+38
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