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authorDario Nieuwenhuis <[email protected]>2022-11-21 23:31:31 +0100
committerDario Nieuwenhuis <[email protected]>2022-11-25 21:02:06 +0100
commit1e2fb0459d8546ba658bb9fe150be5f1f537b48e (patch)
treeeb40a5027581896c7b78db58f509431ed6b11892 /embassy-embedded-hal/src/shared_bus/asynch
parent758f5d7ea29f1df14d5ef59c82e4b7f22545d775 (diff)
Switch to async-fn-in-trait
Diffstat (limited to 'embassy-embedded-hal/src/shared_bus/asynch')
-rw-r--r--embassy-embedded-hal/src/shared_bus/asynch/i2c.rs107
-rw-r--r--embassy-embedded-hal/src/shared_bus/asynch/spi.rs70
2 files changed, 66 insertions, 111 deletions
diff --git a/embassy-embedded-hal/src/shared_bus/asynch/i2c.rs b/embassy-embedded-hal/src/shared_bus/asynch/i2c.rs
index 0bc6afd98..c5e1fd415 100644
--- a/embassy-embedded-hal/src/shared_bus/asynch/i2c.rs
+++ b/embassy-embedded-hal/src/shared_bus/asynch/i2c.rs
@@ -22,7 +22,6 @@
22//! let i2c_dev2 = I2cDevice::new(i2c_bus); 22//! let i2c_dev2 = I2cDevice::new(i2c_bus);
23//! let mpu = Mpu6050::new(i2c_dev2); 23//! let mpu = Mpu6050::new(i2c_dev2);
24//! ``` 24//! ```
25use core::future::Future;
26 25
27use embassy_sync::blocking_mutex::raw::RawMutex; 26use embassy_sync::blocking_mutex::raw::RawMutex;
28use embassy_sync::mutex::Mutex; 27use embassy_sync::mutex::Mutex;
@@ -55,53 +54,39 @@ where
55 M: RawMutex + 'static, 54 M: RawMutex + 'static,
56 BUS: i2c::I2c + 'static, 55 BUS: i2c::I2c + 'static,
57{ 56{
58 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 57 async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
59 58 let mut bus = self.bus.lock().await;
60 fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> { 59 bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
61 async move { 60 Ok(())
62 let mut bus = self.bus.lock().await;
63 bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
64 Ok(())
65 }
66 } 61 }
67 62
68 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 63 async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
69 64 let mut bus = self.bus.lock().await;
70 fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Self::WriteFuture<'a> { 65 bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
71 async move { 66 Ok(())
72 let mut bus = self.bus.lock().await;
73 bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
74 Ok(())
75 }
76 } 67 }
77 68
78 type WriteReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 69 async fn write_read<'a>(
79
80 fn write_read<'a>(
81 &'a mut self, 70 &'a mut self,
82 address: u8, 71 address: u8,
83 wr_buffer: &'a [u8], 72 wr_buffer: &'a [u8],
84 rd_buffer: &'a mut [u8], 73 rd_buffer: &'a mut [u8],
85 ) -> Self::WriteReadFuture<'a> { 74 ) -> Result<(), I2cDeviceError<BUS::Error>> {
86 async move { 75 let mut bus = self.bus.lock().await;
87 let mut bus = self.bus.lock().await; 76 bus.write_read(address, wr_buffer, rd_buffer)
88 bus.write_read(address, wr_buffer, rd_buffer) 77 .await
89 .await 78 .map_err(I2cDeviceError::I2c)?;
90 .map_err(I2cDeviceError::I2c)?; 79 Ok(())
91 Ok(())
92 }
93 } 80 }
94 81
95 type TransactionFuture<'a, 'b> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a, 'b: 'a; 82 async fn transaction<'a, 'b>(
96
97 fn transaction<'a, 'b>(
98 &'a mut self, 83 &'a mut self,
99 address: u8, 84 address: u8,
100 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>], 85 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
101 ) -> Self::TransactionFuture<'a, 'b> { 86 ) -> Result<(), I2cDeviceError<BUS::Error>> {
102 let _ = address; 87 let _ = address;
103 let _ = operations; 88 let _ = operations;
104 async move { todo!() } 89 todo!()
105 } 90 }
106} 91}
107 92
@@ -136,55 +121,41 @@ where
136 M: RawMutex + 'static, 121 M: RawMutex + 'static,
137 BUS: i2c::I2c + SetConfig + 'static, 122 BUS: i2c::I2c + SetConfig + 'static,
138{ 123{
139 type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 124 async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
140 125 let mut bus = self.bus.lock().await;
141 fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> { 126 bus.set_config(&self.config);
142 async move { 127 bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
143 let mut bus = self.bus.lock().await; 128 Ok(())
144 bus.set_config(&self.config);
145 bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
146 Ok(())
147 }
148 } 129 }
149 130
150 type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 131 async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
151 132 let mut bus = self.bus.lock().await;
152 fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Self::WriteFuture<'a> { 133 bus.set_config(&self.config);
153 async move { 134 bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
154 let mut bus = self.bus.lock().await; 135 Ok(())
155 bus.set_config(&self.config);
156 bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
157 Ok(())
158 }
159 } 136 }
160 137
161 type WriteReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a; 138 async fn write_read<'a>(
162
163 fn write_read<'a>(
164 &'a mut self, 139 &'a mut self,
165 address: u8, 140 address: u8,
166 wr_buffer: &'a [u8], 141 wr_buffer: &'a [u8],
167 rd_buffer: &'a mut [u8], 142 rd_buffer: &'a mut [u8],
168 ) -> Self::WriteReadFuture<'a> { 143 ) -> Result<(), I2cDeviceError<BUS::Error>> {
169 async move { 144 let mut bus = self.bus.lock().await;
170 let mut bus = self.bus.lock().await; 145 bus.set_config(&self.config);
171 bus.set_config(&self.config); 146 bus.write_read(address, wr_buffer, rd_buffer)
172 bus.write_read(address, wr_buffer, rd_buffer) 147 .await
173 .await 148 .map_err(I2cDeviceError::I2c)?;
174 .map_err(I2cDeviceError::I2c)?; 149 Ok(())
175 Ok(())
176 }
177 } 150 }
178 151
179 type TransactionFuture<'a, 'b> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a, 'b: 'a; 152 async fn transaction<'a, 'b>(
180
181 fn transaction<'a, 'b>(
182 &'a mut self, 153 &'a mut self,
183 address: u8, 154 address: u8,
184 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>], 155 operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
185 ) -> Self::TransactionFuture<'a, 'b> { 156 ) -> Result<(), I2cDeviceError<BUS::Error>> {
186 let _ = address; 157 let _ = address;
187 let _ = operations; 158 let _ = operations;
188 async move { todo!() } 159 todo!()
189 } 160 }
190} 161}
diff --git a/embassy-embedded-hal/src/shared_bus/asynch/spi.rs b/embassy-embedded-hal/src/shared_bus/asynch/spi.rs
index a3814d6d0..d25716655 100644
--- a/embassy-embedded-hal/src/shared_bus/asynch/spi.rs
+++ b/embassy-embedded-hal/src/shared_bus/asynch/spi.rs
@@ -65,33 +65,25 @@ where
65{ 65{
66 type Bus = BUS; 66 type Bus = BUS;
67 67
68 type TransactionFuture<'a, R, F, Fut> = impl Future<Output = Result<R, Self::Error>> + 'a 68 async fn transaction<R, F, Fut>(&mut self, f: F) -> Result<R, Self::Error>
69 where 69 where
70 Self: 'a, R: 'a, F: FnOnce(*mut Self::Bus) -> Fut + 'a, 70 F: FnOnce(*mut Self::Bus) -> Fut,
71 Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>> + 'a; 71 Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>>,
72
73 fn transaction<'a, R, F, Fut>(&'a mut self, f: F) -> Self::TransactionFuture<'a, R, F, Fut>
74 where
75 R: 'a,
76 F: FnOnce(*mut Self::Bus) -> Fut + 'a,
77 Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>> + 'a,
78 { 72 {
79 async move { 73 let mut bus = self.bus.lock().await;
80 let mut bus = self.bus.lock().await; 74 self.cs.set_low().map_err(SpiDeviceError::Cs)?;
81 self.cs.set_low().map_err(SpiDeviceError::Cs)?;
82 75
83 let f_res = f(&mut *bus).await; 76 let f_res = f(&mut *bus).await;
84 77
85 // On failure, it's important to still flush and deassert CS. 78 // On failure, it's important to still flush and deassert CS.
86 let flush_res = bus.flush().await; 79 let flush_res = bus.flush().await;
87 let cs_res = self.cs.set_high(); 80 let cs_res = self.cs.set_high();
88 81
89 let f_res = f_res.map_err(SpiDeviceError::Spi)?; 82 let f_res = f_res.map_err(SpiDeviceError::Spi)?;
90 flush_res.map_err(SpiDeviceError::Spi)?; 83 flush_res.map_err(SpiDeviceError::Spi)?;
91 cs_res.map_err(SpiDeviceError::Cs)?; 84 cs_res.map_err(SpiDeviceError::Cs)?;
92 85
93 Ok(f_res) 86 Ok(f_res)
94 }
95 } 87 }
96} 88}
97 89
@@ -130,33 +122,25 @@ where
130{ 122{
131 type Bus = BUS; 123 type Bus = BUS;
132 124
133 type TransactionFuture<'a, R, F, Fut> = impl Future<Output = Result<R, Self::Error>> + 'a 125 async fn transaction<R, F, Fut>(&mut self, f: F) -> Result<R, Self::Error>
134 where
135 Self: 'a, R: 'a, F: FnOnce(*mut Self::Bus) -> Fut + 'a,
136 Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>> + 'a;
137
138 fn transaction<'a, R, F, Fut>(&'a mut self, f: F) -> Self::TransactionFuture<'a, R, F, Fut>
139 where 126 where
140 R: 'a, 127 F: FnOnce(*mut Self::Bus) -> Fut,
141 F: FnOnce(*mut Self::Bus) -> Fut + 'a, 128 Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>>,
142 Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>> + 'a,
143 { 129 {
144 async move { 130 let mut bus = self.bus.lock().await;
145 let mut bus = self.bus.lock().await; 131 bus.set_config(&self.config);
146 bus.set_config(&self.config); 132 self.cs.set_low().map_err(SpiDeviceError::Cs)?;
147 self.cs.set_low().map_err(SpiDeviceError::Cs)?;
148 133
149 let f_res = f(&mut *bus).await; 134 let f_res = f(&mut *bus).await;
150 135
151 // On failure, it's important to still flush and deassert CS. 136 // On failure, it's important to still flush and deassert CS.
152 let flush_res = bus.flush().await; 137 let flush_res = bus.flush().await;
153 let cs_res = self.cs.set_high(); 138 let cs_res = self.cs.set_high();
154 139
155 let f_res = f_res.map_err(SpiDeviceError::Spi)?; 140 let f_res = f_res.map_err(SpiDeviceError::Spi)?;
156 flush_res.map_err(SpiDeviceError::Spi)?; 141 flush_res.map_err(SpiDeviceError::Spi)?;
157 cs_res.map_err(SpiDeviceError::Cs)?; 142 cs_res.map_err(SpiDeviceError::Cs)?;
158 143
159 Ok(f_res) 144 Ok(f_res)
160 }
161 } 145 }
162} 146}
generated by cgit (git 2.34.1) at 2026-04-05 18:46:51 +0000