diff options
| author | Dario Nieuwenhuis <[email protected]> | 2023-06-08 16:08:40 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2023-06-08 18:00:48 +0200 |
| commit | 921780e6bfb9bcb2cd087b8aa8b094d792c99fa2 (patch) | |
| tree | bd21fba9800471b860ca44e05567588dcc1afef7 /embassy-rp/src/multicore.rs | |
| parent | 87ad66f2b4a5bfd36dfc8d8aad5492e9e3f915e6 (diff) | |
Make interrupt module more standard.
- Move typelevel interrupts to a special-purpose mod: `embassy_xx::interrupt::typelevel`.
- Reexport the PAC interrupt enum in `embassy_xx::interrupt`.
This has a few advantages:
- The `embassy_xx::interrupt` module is now more "standard".
- It works with `cortex-m` functions for manipulating interrupts, for example.
- It works with RTIC.
- the interrupt enum allows holding value that can be "any interrupt at runtime", this can't be done with typelevel irqs.
- When "const-generics on enums" is stable, we can remove the typelevel interrupts without disruptive changes to `embassy_xx::interrupt`.
Diffstat (limited to 'embassy-rp/src/multicore.rs')
| -rw-r--r-- | embassy-rp/src/multicore.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/embassy-rp/src/multicore.rs b/embassy-rp/src/multicore.rs index 807fda57b..e1246ce8f 100644 --- a/embassy-rp/src/multicore.rs +++ b/embassy-rp/src/multicore.rs | |||
| @@ -50,7 +50,7 @@ | |||
| 50 | use core::mem::ManuallyDrop; | 50 | use core::mem::ManuallyDrop; |
| 51 | use core::sync::atomic::{compiler_fence, AtomicBool, Ordering}; | 51 | use core::sync::atomic::{compiler_fence, AtomicBool, Ordering}; |
| 52 | 52 | ||
| 53 | use crate::interrupt::Interrupt; | 53 | use crate::interrupt::InterruptExt; |
| 54 | use crate::peripherals::CORE1; | 54 | use crate::peripherals::CORE1; |
| 55 | use crate::{gpio, interrupt, pac}; | 55 | use crate::{gpio, interrupt, pac}; |
| 56 | 56 | ||
| @@ -156,7 +156,7 @@ where | |||
| 156 | 156 | ||
| 157 | IS_CORE1_INIT.store(true, Ordering::Release); | 157 | IS_CORE1_INIT.store(true, Ordering::Release); |
| 158 | // Enable fifo interrupt on CORE1 for `pause` functionality. | 158 | // Enable fifo interrupt on CORE1 for `pause` functionality. |
| 159 | unsafe { interrupt::SIO_IRQ_PROC1::enable() }; | 159 | unsafe { interrupt::SIO_IRQ_PROC1.enable() }; |
| 160 | 160 | ||
| 161 | entry() | 161 | entry() |
| 162 | } | 162 | } |
