stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.

1 files changed, 12 insertions, 12 deletions

diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index fbf2d1cf9..9d5dcfc4b 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -1,7 +1,7 @@
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
 use crate::pac::rcc::regs::Cfgr1;
 pub use crate::pac::rcc::vals::{
-    Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as ClockSrc,
+    Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as Sysclk,
 };
 use crate::pac::{FLASH, RCC};
 use crate::time::Hertz;
@@ -23,7 +23,7 @@ pub struct Config {
     pub hse: Option<Hse>,
 
     // sysclk, buses.
-    pub mux: ClockSrc,
+    pub sys: Sysclk,
     pub ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
@@ -43,7 +43,7 @@ impl Default for Config {
         Config {
             hse: None,
             hsi: true,
-            mux: ClockSrc::HSI,
+            sys: Sysclk::HSI,
             ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
@@ -65,11 +65,11 @@ pub(crate) unsafe fn init(config: Config) {
     if !RCC.cr().read().hsion() {
         hsi_enable()
     }
-    if RCC.cfgr1().read().sws() != ClockSrc::HSI {
+    if RCC.cfgr1().read().sws() != Sysclk::HSI {
         // Set HSI as a clock source, reset prescalers.
         RCC.cfgr1().write_value(Cfgr1::default());
         // Wait for clock switch status bits to change.
-        while RCC.cfgr1().read().sws() != ClockSrc::HSI {}
+        while RCC.cfgr1().read().sws() != Sysclk::HSI {}
     }
 
     // Set voltage scale
@@ -94,11 +94,11 @@ pub(crate) unsafe fn init(config: Config) {
         HSE_FREQ
     });
 
-    let sys_clk = match config.mux {
-        ClockSrc::HSE => hse.unwrap(),
-        ClockSrc::HSI => hsi.unwrap(),
-        ClockSrc::_RESERVED_1 => unreachable!(),
-        ClockSrc::PLL1_R => todo!(),
+    let sys_clk = match config.sys {
+        Sysclk::HSE => hse.unwrap(),
+        Sysclk::HSI => hsi.unwrap(),
+        Sysclk::_RESERVED_1 => unreachable!(),
+        Sysclk::PLL1_R => todo!(),
     };
 
     assert!(sys_clk.0 <= 100_000_000);
@@ -142,9 +142,9 @@ pub(crate) unsafe fn init(config: Config) {
     // TODO: Set the SRAM wait states
 
     RCC.cfgr1().modify(|w| {
-        w.set_sw(config.mux);
+        w.set_sw(config.sys);
     });
-    while RCC.cfgr1().read().sws() != config.mux {}
+    while RCC.cfgr1().read().sws() != config.sys {}
 
     RCC.cfgr2().modify(|w| {
         w.set_hpre(config.ahb_pre);