Merge branch 'main' into main

8 files changed, 281 insertions, 217 deletions

diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 77f19a37b..620d7858e 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -2,16 +2,17 @@
 
 use core::marker::PhantomData;
 
-pub use stm32_metapac::timer::vals::{Ckd, Mms2, Ossi, Ossr};
-
 use super::low_level::{CountingMode, OutputPolarity, Timer};
 use super::simple_pwm::PwmPin;
 use super::{AdvancedInstance4Channel, Ch1, Ch2, Ch3, Ch4, Channel, TimerComplementaryPin};
 use crate::Peri;
-use crate::gpio::{AnyPin, OutputType};
+use crate::dma::word::Word;
+use crate::gpio::{AfType, AnyPin, OutputType};
+pub use crate::pac::timer::vals::{Ccds, Ckd, Mms2, Ossi, Ossr};
 use crate::time::Hertz;
 use crate::timer::TimerChannel;
 use crate::timer::low_level::OutputCompareMode;
+use crate::timer::simple_pwm::PwmPinConfig;
 
 /// Complementary PWM pin wrapper.
 ///
@@ -27,9 +28,27 @@ impl<'d, T: AdvancedInstance4Channel, C: TimerChannel, #[cfg(afio)] A> if_afio!(
     pub fn new(pin: Peri<'d, if_afio!(impl TimerComplementaryPin<T, C, A>)>, output_type: OutputType) -> Self {
         critical_section::with(|_| {
             pin.set_low();
-            set_as_af!(
-                pin,
-                crate::gpio::AfType::output(output_type, crate::gpio::Speed::VeryHigh)
+            set_as_af!(pin, AfType::output(output_type, crate::gpio::Speed::VeryHigh));
+        });
+        ComplementaryPwmPin {
+            pin: pin.into(),
+            phantom: PhantomData,
+        }
+    }
+
+    /// Create a new PWM pin instance with config.
+    pub fn new_with_config(
+        pin: Peri<'d, if_afio!(impl TimerComplementaryPin<T, C, A>)>,
+        pin_config: PwmPinConfig,
+    ) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            #[cfg(gpio_v1)]
+            set_as_af!(pin, AfType::output(pin_config.output_type, pin_config.speed));
+            #[cfg(gpio_v2)]
+            pin.set_as_af(
+                pin.af_num(),
+                AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull),
             );
         });
         ComplementaryPwmPin {
@@ -176,20 +195,20 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Get max duty value.
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
-    pub fn get_max_duty(&self) -> u16 {
+    pub fn get_max_duty(&self) -> u32 {
         if self.inner.get_counting_mode().is_center_aligned() {
-            self.inner.get_max_compare_value() as u16
+            self.inner.get_max_compare_value().into()
         } else {
-            self.inner.get_max_compare_value() as u16 + 1
+            self.inner.get_max_compare_value().into() + 1
         }
     }
 
     /// Set the duty for a given channel.
     ///
     /// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
-    pub fn set_duty(&mut self, channel: Channel, duty: u16) {
+    pub fn set_duty(&mut self, channel: Channel, duty: u32) {
         assert!(duty <= self.get_max_duty());
-        self.inner.set_compare_value(channel, duty as _)
+        self.inner.set_compare_value(channel, unwrap!(duty.try_into()))
     }
 
     /// Set the output polarity for a given channel.
@@ -219,9 +238,34 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Generate a sequence of PWM waveform
     ///
     /// Note:
+    /// The DMA channel provided does not need to correspond to the requested channel.
+    pub async fn waveform<C: TimerChannel, W: Word + Into<T::Word>>(
+        &mut self,
+        dma: Peri<'_, impl super::Dma<T, C>>,
+        channel: Channel,
+        duty: &[W],
+    ) {
+        self.inner.enable_channel(channel, true);
+        self.inner.enable_channel(C::CHANNEL, true);
+        self.inner.clamp_compare_value::<W>(channel);
+        self.inner.set_cc_dma_selection(Ccds::ON_UPDATE);
+        self.inner.set_cc_dma_enable_state(C::CHANNEL, true);
+        self.inner.setup_channel_update_dma(dma, channel, duty).await;
+        self.inner.set_cc_dma_enable_state(C::CHANNEL, false);
+    }
+
+    /// Generate a sequence of PWM waveform
+    ///
+    /// Note:
     /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
-    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
+    pub async fn waveform_up<W: Word + Into<T::Word>>(
+        &mut self,
+        dma: Peri<'_, impl super::UpDma<T>>,
+        channel: Channel,
+        duty: &[W],
+    ) {
         self.inner.enable_channel(channel, true);
+        self.inner.clamp_compare_value::<W>(channel);
         self.inner.enable_update_dma(true);
         self.inner.setup_update_dma(dma, channel, duty).await;
         self.inner.enable_update_dma(false);
@@ -256,13 +300,21 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
     ///
-    pub async fn waveform_up_multi_channel(
+    pub async fn waveform_up_multi_channel<W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'_, impl super::UpDma<T>>,
         starting_channel: Channel,
         ending_channel: Channel,
-        duty: &[u16],
+        duty: &[W],
     ) {
+        [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
+            .iter()
+            .filter(|ch| ch.index() >= starting_channel.index())
+            .filter(|ch| ch.index() <= ending_channel.index())
+            .for_each(|ch| {
+                self.inner.enable_channel(*ch, true);
+                self.inner.clamp_compare_value::<W>(*ch);
+            });
         self.inner.enable_update_dma(true);
         self.inner
             .setup_update_dma_burst(dma, starting_channel, ending_channel, duty)
@@ -291,20 +343,20 @@ impl<'d, T: AdvancedInstance4Channel> embedded_hal_02::Pwm for ComplementaryPwm<
     }
 
     fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
-        self.inner.get_compare_value(channel) as u16
+        unwrap!(self.inner.get_compare_value(channel).try_into())
     }
 
     fn get_max_duty(&self) -> Self::Duty {
         if self.inner.get_counting_mode().is_center_aligned() {
-            self.inner.get_max_compare_value() as u16
+            unwrap!(self.inner.get_max_compare_value().try_into())
         } else {
-            self.inner.get_max_compare_value() as u16 + 1
+            unwrap!(self.inner.get_max_compare_value().try_into()) + 1
         }
     }
 
     fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
-        assert!(duty <= self.get_max_duty());
-        self.inner.set_compare_value(channel, duty as u32)
+        assert!(duty <= unwrap!(self.get_max_duty().try_into()));
+        self.inner.set_compare_value(channel, unwrap!(duty.try_into()))
     }
 
     fn set_period<P>(&mut self, period: P)
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index 9cf0f8c34..3e1482b67 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -97,7 +97,7 @@ impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
 
     /// Get capture value for a channel.
     pub fn get_capture_value(&self, channel: Channel) -> u32 {
-        self.inner.get_capture_value(channel)
+        self.inner.get_capture_value(channel).into()
     }
 
     /// Get input interrupt.
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index aba08081f..82e936f3a 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -13,7 +13,7 @@ use embassy_hal_internal::Peri;
 pub use stm32_metapac::timer::vals::{FilterValue, Mms as MasterMode, Sms as SlaveMode, Ts as TriggerSource};
 
 use super::*;
-use crate::dma::{Transfer, WritableRingBuffer};
+use crate::dma::{self, Transfer, WritableRingBuffer};
 use crate::pac::timer::vals;
 use crate::rcc;
 use crate::time::Hertz;
@@ -268,6 +268,11 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
         unsafe { crate::pac::timer::TimGp32::from_ptr(T::regs()) }
     }
 
+    #[cfg(stm32l0)]
+    fn regs_gp32_unchecked(&self) -> crate::pac::timer::TimGp16 {
+        unsafe { crate::pac::timer::TimGp16::from_ptr(T::regs()) }
+    }
+
     /// Start the timer.
     pub fn start(&self) {
         self.regs_core().cr1().modify(|r| r.set_cen(true));
@@ -296,7 +301,12 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
 
     /// get the capability of the timer
     pub fn bits(&self) -> TimerBits {
-        T::BITS
+        match T::Word::bits() {
+            16 => TimerBits::Bits16,
+            #[cfg(not(stm32l0))]
+            32 => TimerBits::Bits32,
+            _ => unreachable!(),
+        }
     }
 
     /// Set the frequency of how many times per second the timer counts up to the max value or down to 0.
@@ -306,18 +316,10 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
     /// In center-aligned mode (which not all timers support), the wrap-around frequency is effectively halved
     /// because it needs to count up and down.
     pub fn set_frequency(&self, frequency: Hertz) {
-        match T::BITS {
-            TimerBits::Bits16 => {
-                self.set_frequency_internal(frequency, 16);
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                self.set_frequency_internal(frequency, 32);
-            }
-        }
+        self.set_frequency_internal(frequency, T::Word::bits());
     }
 
-    pub(crate) fn set_frequency_internal(&self, frequency: Hertz, max_divide_by_bits: u8) {
+    pub(crate) fn set_frequency_internal(&self, frequency: Hertz, max_divide_by_bits: usize) {
         let f = frequency.0;
         assert!(f > 0);
         let timer_f = T::frequency().0;
@@ -326,25 +328,15 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
         let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << max_divide_by_bits)).try_into());
         let divide_by = pclk_ticks_per_timer_period / (u64::from(psc) + 1);
 
-        match T::BITS {
-            TimerBits::Bits16 => {
-                // the timer counts `0..=arr`, we want it to count `0..divide_by`
-                let arr = unwrap!(u16::try_from(divide_by - 1));
-
-                let regs = self.regs_core();
-                regs.psc().write_value(psc);
-                regs.arr().write(|r| r.set_arr(arr));
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                // the timer counts `0..=arr`, we want it to count `0..divide_by`
-                let arr: u32 = unwrap!(u32::try_from(divide_by - 1));
+        // the timer counts `0..=arr`, we want it to count `0..divide_by`
+        let arr: T::Word = unwrap!(T::Word::try_from(divide_by - 1));
 
-                let regs = self.regs_gp32_unchecked();
-                regs.psc().write_value(psc);
-                regs.arr().write_value(arr);
-            }
-        }
+        let regs = self.regs_gp32_unchecked();
+        regs.psc().write_value(psc);
+        #[cfg(stm32l0)]
+        regs.arr().write(|r| r.set_arr(unwrap!(arr.try_into())));
+        #[cfg(not(stm32l0))]
+        regs.arr().write_value(arr.into());
     }
 
     /// Set tick frequency.
@@ -393,23 +385,14 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
     pub fn get_frequency(&self) -> Hertz {
         let timer_f = T::frequency();
 
-        match T::BITS {
-            TimerBits::Bits16 => {
-                let regs = self.regs_core();
-                let arr = regs.arr().read().arr();
-                let psc = regs.psc().read();
+        let regs = self.regs_gp32_unchecked();
+        #[cfg(not(stm32l0))]
+        let arr = regs.arr().read();
+        #[cfg(stm32l0)]
+        let arr = regs.arr().read().arr();
+        let psc = regs.psc().read();
 
-                timer_f / arr / (psc + 1)
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                let regs = self.regs_gp32_unchecked();
-                let arr = regs.arr().read();
-                let psc = regs.psc().read();
-
-                timer_f / arr / (psc + 1)
-            }
-        }
+        timer_f / arr / (psc + 1)
     }
 
     /// Get the clock frequency of the timer (before prescaler is applied).
@@ -469,42 +452,29 @@ impl<'d, T: GeneralInstance1Channel> Timer<'d, T> {
     }
 
     /// Get max compare value. This depends on the timer frequency and the clock frequency from RCC.
-    pub fn get_max_compare_value(&self) -> u32 {
-        match T::BITS {
-            TimerBits::Bits16 => self.regs_1ch().arr().read().arr() as u32,
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => self.regs_gp32_unchecked().arr().read(),
-        }
+    pub fn get_max_compare_value(&self) -> T::Word {
+        #[cfg(not(stm32l0))]
+        return unwrap!(self.regs_gp32_unchecked().arr().read().try_into());
+        #[cfg(stm32l0)]
+        return unwrap!(self.regs_gp32_unchecked().arr().read().arr().try_into());
     }
 
     /// Set the max compare value.
     ///
     /// An update event is generated to load the new value. The update event is
     /// generated such that it will not cause an interrupt or DMA request.
-    pub fn set_max_compare_value(&self, ticks: u32) {
-        match T::BITS {
-            TimerBits::Bits16 => {
-                let arr = unwrap!(u16::try_from(ticks));
+    pub fn set_max_compare_value(&self, ticks: T::Word) {
+        let arr = ticks;
 
-                let regs = self.regs_1ch();
-                regs.arr().write(|r| r.set_arr(arr));
+        let regs = self.regs_gp32_unchecked();
+        #[cfg(not(stm32l0))]
+        regs.arr().write_value(arr.into());
+        #[cfg(stm32l0)]
+        regs.arr().write(|r| r.set_arr(unwrap!(arr.try_into())));
 
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                let arr = ticks;
-
-                let regs = self.regs_gp32_unchecked();
-                regs.arr().write_value(arr);
-
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
-            }
-        }
+        regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
+        regs.egr().write(|r| r.set_ug(true));
+        regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
     }
 }
 
@@ -638,35 +608,44 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
     }
 
     /// Set compare value for a channel.
-    pub fn set_compare_value(&self, channel: Channel, value: u32) {
-        match T::BITS {
-            TimerBits::Bits16 => {
-                let value = unwrap!(u16::try_from(value));
-                self.regs_gp16().ccr(channel.index()).modify(|w| w.set_ccr(value));
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                self.regs_gp32_unchecked().ccr(channel.index()).write_value(value);
-            }
-        }
+    pub fn set_compare_value(&self, channel: Channel, value: T::Word) {
+        #[cfg(not(stm32l0))]
+        self.regs_gp32_unchecked()
+            .ccr(channel.index())
+            .write_value(value.into());
+        #[cfg(stm32l0)]
+        self.regs_gp16()
+            .ccr(channel.index())
+            .modify(|w| w.set_ccr(unwrap!(value.try_into())));
     }
 
     /// Get compare value for a channel.
-    pub fn get_compare_value(&self, channel: Channel) -> u32 {
-        match T::BITS {
-            TimerBits::Bits16 => self.regs_gp16().ccr(channel.index()).read().ccr() as u32,
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => self.regs_gp32_unchecked().ccr(channel.index()).read(),
-        }
+    pub fn get_compare_value(&self, channel: Channel) -> T::Word {
+        #[cfg(not(stm32l0))]
+        return unwrap!(self.regs_gp32_unchecked().ccr(channel.index()).read().try_into());
+        #[cfg(stm32l0)]
+        return unwrap!(self.regs_gp32_unchecked().ccr(channel.index()).read().ccr().try_into());
+    }
+
+    pub(crate) fn clamp_compare_value<W: Word>(&mut self, channel: Channel) {
+        self.set_compare_value(
+            channel,
+            unwrap!(
+                self.get_compare_value(channel)
+                    .into()
+                    .clamp(0, W::max() as u32)
+                    .try_into()
+            ),
+        );
     }
 
     /// Setup a ring buffer for the channel
-    pub fn setup_ring_buffer<'a>(
+    pub fn setup_ring_buffer<'a, W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'a, impl super::UpDma<T>>,
         channel: Channel,
-        dma_buf: &'a mut [u16],
-    ) -> WritableRingBuffer<'a, u16> {
+        dma_buf: &'a mut [W],
+    ) -> WritableRingBuffer<'a, W> {
         #[allow(clippy::let_unit_value)] // eg. stm32f334
         let req = dma.request();
 
@@ -686,7 +665,7 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
             WritableRingBuffer::new(
                 dma,
                 req,
-                self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
+                self.regs_1ch().ccr(channel.index()).as_ptr() as *mut W,
                 dma_buf,
                 dma_transfer_option,
             )
@@ -697,15 +676,35 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
     ///
     /// Note:
     /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
-    pub fn setup_update_dma<'a>(
+    pub fn setup_update_dma<'a, W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'a, impl super::UpDma<T>>,
         channel: Channel,
-        duty: &'a [u16],
+        duty: &'a [W],
     ) -> Transfer<'a> {
-        #[allow(clippy::let_unit_value)] // eg. stm32f334
-        let req = dma.request();
+        self.setup_update_dma_inner(dma.request(), dma, channel, duty)
+    }
 
+    /// Generate a sequence of PWM waveform
+    ///
+    /// Note:
+    /// The DMA channel provided does not need to correspond to the requested channel.
+    pub fn setup_channel_update_dma<'a, C: TimerChannel, W: Word + Into<T::Word>>(
+        &mut self,
+        dma: Peri<'a, impl super::Dma<T, C>>,
+        channel: Channel,
+        duty: &'a [W],
+    ) -> Transfer<'a> {
+        self.setup_update_dma_inner(dma.request(), dma, channel, duty)
+    }
+
+    fn setup_update_dma_inner<'a, W: Word + Into<T::Word>>(
+        &mut self,
+        request: dma::Request,
+        dma: Peri<'a, impl dma::Channel>,
+        channel: Channel,
+        duty: &'a [W],
+    ) -> Transfer<'a> {
         unsafe {
             #[cfg(not(any(bdma, gpdma)))]
             use crate::dma::{Burst, FifoThreshold};
@@ -719,29 +718,13 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
                 ..Default::default()
             };
 
-            match self.bits() {
-                TimerBits::Bits16 => Transfer::new_write(
-                    dma,
-                    req,
-                    duty,
-                    self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
-                    dma_transfer_option,
-                ),
-                #[cfg(not(any(stm32l0)))]
-                TimerBits::Bits32 => {
-                    #[cfg(not(any(bdma, gpdma)))]
-                    panic!("unsupported timer bits");
-
-                    #[cfg(any(bdma, gpdma))]
-                    Transfer::new_write(
-                        dma,
-                        req,
-                        duty,
-                        self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u32,
-                        dma_transfer_option,
-                    )
-                }
-            }
+            Transfer::new_write(
+                dma,
+                request,
+                duty,
+                self.regs_gp16().ccr(channel.index()).as_ptr() as *mut W,
+                dma_transfer_option,
+            )
         }
     }
 
@@ -774,12 +757,12 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
     ///
-    pub fn setup_update_dma_burst<'a>(
+    pub fn setup_update_dma_burst<'a, W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'a, impl super::UpDma<T>>,
         starting_channel: Channel,
         ending_channel: Channel,
-        duty: &'a [u16],
+        duty: &'a [W],
     ) -> Transfer<'a> {
         let cr1_addr = self.regs_gp16().cr1().as_ptr() as u32;
         let start_ch_index = starting_channel.index();
@@ -815,14 +798,14 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
                 dma,
                 req,
                 duty,
-                self.regs_gp16().dmar().as_ptr() as *mut u16,
+                self.regs_gp16().dmar().as_ptr() as *mut W,
                 dma_transfer_option,
             )
         }
     }
 
     /// Get capture value for a channel.
-    pub fn get_capture_value(&self, channel: Channel) -> u32 {
+    pub fn get_capture_value(&self, channel: Channel) -> T::Word {
         self.get_compare_value(channel)
     }
 
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 3fa363881..998e3a6f4 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -15,6 +15,8 @@ pub mod qei;
 pub mod ringbuffered;
 pub mod simple_pwm;
 
+use crate::dma::word::Word;
+use crate::fmt::Debuggable;
 use crate::interrupt;
 use crate::rcc::RccPeripheral;
 
@@ -163,7 +165,12 @@ pub trait CoreInstance: SealedInstance + 'static {
     type UpdateInterrupt: interrupt::typelevel::Interrupt;
 
     /// Amount of bits this timer has.
-    const BITS: TimerBits;
+    type Word: Word
+        + TryInto<u16, Error: Debuggable>
+        + From<u16>
+        + TryFrom<u32, Error: Debuggable>
+        + Into<u32>
+        + TryFrom<u64, Error: Debuggable>;
 
     /// Registers for this timer.
     ///
@@ -241,7 +248,7 @@ dma_trait!(Dma, GeneralInstance4Channel, TimerChannel);
 
 #[allow(unused)]
 macro_rules! impl_core_timer {
-    ($inst:ident, $bits:expr) => {
+    ($inst:ident, $bits:ident) => {
         impl SealedInstance for crate::peripherals::$inst {
             fn state() -> &'static State {
                 static STATE: State = State::new();
@@ -251,8 +258,7 @@ macro_rules! impl_core_timer {
 
         impl CoreInstance for crate::peripherals::$inst {
             type UpdateInterrupt = crate::_generated::peripheral_interrupts::$inst::UP;
-
-            const BITS: TimerBits = $bits;
+            type Word = $bits;
 
             fn regs() -> *mut () {
                 crate::pac::$inst.as_ptr()
@@ -306,13 +312,13 @@ macro_rules! impl_general_4ch_blank_sealed {
 
 foreach_interrupt! {
     ($inst:ident, timer, TIM_BASIC, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
     };
 
     ($inst:ident, timer, TIM_1CH, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -322,7 +328,7 @@ foreach_interrupt! {
     };
 
     ($inst:ident, timer, TIM_2CH, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -332,7 +338,7 @@ foreach_interrupt! {
     };
 
     ($inst:ident, timer, TIM_GP16, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -342,7 +348,7 @@ foreach_interrupt! {
     };
 
     ($inst:ident, timer, TIM_GP32, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits32);
+        impl_core_timer!($inst, u32);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -353,7 +359,7 @@ foreach_interrupt! {
     };
 
     ($inst:ident, timer, TIM_1CH_CMP, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -366,7 +372,7 @@ foreach_interrupt! {
     };
 
     ($inst:ident, timer, TIM_2CH_CMP, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -379,7 +385,7 @@ foreach_interrupt! {
     };
 
     ($inst:ident, timer, TIM_ADV, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -400,7 +406,7 @@ pub struct UpdateInterruptHandler<T: CoreInstance> {
 impl<T: CoreInstance> interrupt::typelevel::Handler<T::UpdateInterrupt> for UpdateInterruptHandler<T> {
     unsafe fn on_interrupt() {
         #[cfg(feature = "low-power")]
-        crate::low_power::Executor::on_wakeup_irq();
+        crate::low_power::Executor::on_wakeup_irq_or_event();
 
         let regs = crate::pac::timer::TimCore::from_ptr(T::regs());
 
@@ -430,7 +436,7 @@ impl<T: GeneralInstance1Channel> interrupt::typelevel::Handler<T::CaptureCompare
 {
     unsafe fn on_interrupt() {
         #[cfg(feature = "low-power")]
-        crate::low_power::Executor::on_wakeup_irq();
+        crate::low_power::Executor::on_wakeup_irq_or_event();
 
         let regs = crate::pac::timer::TimGp16::from_ptr(T::regs());
 
diff --git a/embassy-stm32/src/timer/one_pulse.rs b/embassy-stm32/src/timer/one_pulse.rs
index fe8681356..989e1d630 100644
--- a/embassy-stm32/src/timer/one_pulse.rs
+++ b/embassy-stm32/src/timer/one_pulse.rs
@@ -199,7 +199,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     fn new_inner(&mut self, freq: Hertz, pulse_end: u32, counting_mode: CountingMode) {
         self.inner.set_counting_mode(counting_mode);
         self.inner.set_tick_freq(freq);
-        self.inner.set_max_compare_value(pulse_end);
+        self.inner.set_max_compare_value(unwrap!(pulse_end.try_into()));
         self.inner.regs_core().cr1().modify(|r| r.set_opm(true));
         // Required for advanced timers, see GeneralInstance4Channel for details
         self.inner.enable_outputs();
@@ -211,14 +211,14 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
 
     /// Get the end of the pulse in ticks from the trigger.
     pub fn pulse_end(&self) -> u32 {
-        let max = self.inner.get_max_compare_value();
+        let max: u32 = self.inner.get_max_compare_value().into();
         assert!(max < u32::MAX);
         max + 1
     }
 
     /// Set the end of the pulse in ticks from the trigger.
     pub fn set_pulse_end(&mut self, ticks: u32) {
-        self.inner.set_max_compare_value(ticks)
+        self.inner.set_max_compare_value(unwrap!(ticks.try_into()))
     }
 
     /// Reset the timer on each trigger
@@ -327,7 +327,7 @@ pub struct OnePulseChannel<'d, T: GeneralInstance4Channel> {
 impl<'d, T: GeneralInstance4Channel> OnePulseChannel<'d, T> {
     /// Get the end of the pulse in ticks from the trigger.
     pub fn pulse_end(&self) -> u32 {
-        let max = self.inner.get_max_compare_value();
+        let max: u32 = self.inner.get_max_compare_value().into();
         assert!(max < u32::MAX);
         max + 1
     }
@@ -339,13 +339,13 @@ impl<'d, T: GeneralInstance4Channel> OnePulseChannel<'d, T> {
 
     /// Get the start of the pulse in ticks from the trigger.
     pub fn pulse_delay(&mut self) -> u32 {
-        self.inner.get_compare_value(self.channel)
+        self.inner.get_compare_value(self.channel).into()
     }
 
     /// Set the start of the pulse in ticks from the trigger.
     pub fn set_pulse_delay(&mut self, delay: u32) {
         assert!(delay <= self.pulse_end());
-        self.inner.set_compare_value(self.channel, delay);
+        self.inner.set_compare_value(self.channel, unwrap!(delay.try_into()));
     }
 
     /// Set the pulse width in ticks.
diff --git a/embassy-stm32/src/timer/pwm_input.rs b/embassy-stm32/src/timer/pwm_input.rs
index 057ab011a..f2f00927d 100644
--- a/embassy-stm32/src/timer/pwm_input.rs
+++ b/embassy-stm32/src/timer/pwm_input.rs
@@ -91,16 +91,18 @@ impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
 
     /// Get the period tick count
     pub fn get_period_ticks(&self) -> u32 {
-        self.inner.get_capture_value(self.channel)
+        self.inner.get_capture_value(self.channel).into()
     }
 
     /// Get the pulse width tick count
     pub fn get_width_ticks(&self) -> u32 {
-        self.inner.get_capture_value(match self.channel {
-            Channel::Ch1 => Channel::Ch2,
-            Channel::Ch2 => Channel::Ch1,
-            _ => panic!("Invalid channel for PWM input"),
-        })
+        self.inner
+            .get_capture_value(match self.channel {
+                Channel::Ch1 => Channel::Ch2,
+                Channel::Ch2 => Channel::Ch1,
+                _ => panic!("Invalid channel for PWM input"),
+            })
+            .into()
     }
 
     /// Get the duty cycle in 100%
diff --git a/embassy-stm32/src/timer/ringbuffered.rs b/embassy-stm32/src/timer/ringbuffered.rs
index e8f97bf59..fbb6b19ea 100644
--- a/embassy-stm32/src/timer/ringbuffered.rs
+++ b/embassy-stm32/src/timer/ringbuffered.rs
@@ -7,6 +7,7 @@ use super::low_level::Timer;
 use super::{Channel, GeneralInstance4Channel};
 use crate::dma::WritableRingBuffer;
 use crate::dma::ringbuffer::Error;
+use crate::dma::word::Word;
 
 /// A PWM channel that uses a DMA ring buffer for continuous waveform generation.
 ///
@@ -23,17 +24,17 @@ use crate::dma::ringbuffer::Error;
 /// channel.start(); // Start DMA transfer
 /// channel.write(&[100, 200, 300]).ok(); // Update duty cycles
 /// ```
-pub struct RingBufferedPwmChannel<'d, T: GeneralInstance4Channel> {
+pub struct RingBufferedPwmChannel<'d, T: GeneralInstance4Channel, W: Word + Into<T::Word>> {
     timer: ManuallyDrop<Timer<'d, T>>,
-    ring_buf: WritableRingBuffer<'d, u16>,
+    ring_buf: WritableRingBuffer<'d, W>,
     channel: Channel,
 }
 
-impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
+impl<'d, T: GeneralInstance4Channel, W: Word + Into<T::Word>> RingBufferedPwmChannel<'d, T, W> {
     pub(crate) fn new(
         timer: ManuallyDrop<Timer<'d, T>>,
         channel: Channel,
-        ring_buf: WritableRingBuffer<'d, u16>,
+        ring_buf: WritableRingBuffer<'d, W>,
     ) -> Self {
         Self {
             timer,
@@ -55,18 +56,18 @@ impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
     }
 
     /// Write elements directly to the raw buffer. This can be used to fill the buffer before starting the DMA transfer.
-    pub fn write_immediate(&mut self, buf: &[u16]) -> Result<(usize, usize), Error> {
+    pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), Error> {
         self.ring_buf.write_immediate(buf)
     }
 
     /// Write elements from the ring buffer
     /// Return a tuple of the length written and the length remaining in the buffer
-    pub fn write(&mut self, buf: &[u16]) -> Result<(usize, usize), Error> {
+    pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), Error> {
         self.ring_buf.write(buf)
     }
 
     /// Write an exact number of elements to the ringbuffer.
-    pub async fn write_exact(&mut self, buffer: &[u16]) -> Result<usize, Error> {
+    pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, Error> {
         self.ring_buf.write_exact(buffer).await
     }
 
@@ -140,7 +141,7 @@ impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
     pub fn max_duty_cycle(&self) -> u16 {
-        let max = self.timer.get_max_compare_value();
+        let max: u32 = self.timer.get_max_compare_value().into();
         assert!(max < u16::MAX as u32);
         max as u16 + 1
     }
@@ -155,15 +156,3 @@ impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
         self.timer.set_output_compare_mode(self.channel, mode);
     }
 }
-
-/// A group of four [`SimplePwmChannel`]s, obtained from [`SimplePwm::split`].
-pub struct RingBufferedPwmChannels<'d, T: GeneralInstance4Channel> {
-    /// Channel 1
-    pub ch1: RingBufferedPwmChannel<'d, T>,
-    /// Channel 2
-    pub ch2: RingBufferedPwmChannel<'d, T>,
-    /// Channel 3
-    pub ch3: RingBufferedPwmChannel<'d, T>,
-    /// Channel 4
-    pub ch4: RingBufferedPwmChannel<'d, T>,
-}
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 484e9fd81..9a5f0fd1d 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -7,9 +7,11 @@ use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer};
 use super::ringbuffered::RingBufferedPwmChannel;
 use super::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance4Channel, TimerChannel, TimerPin};
 use crate::Peri;
+use crate::dma::word::Word;
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
+use crate::pac::timer::vals::Ccds;
 use crate::time::Hertz;
 
 /// PWM pin wrapper.
@@ -98,18 +100,16 @@ impl<'d, T: GeneralInstance4Channel> SimplePwmChannel<'d, T> {
     /// Get max duty value.
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
-    pub fn max_duty_cycle(&self) -> u16 {
-        let max = self.timer.get_max_compare_value();
-        assert!(max < u16::MAX as u32);
-        max as u16 + 1
+    pub fn max_duty_cycle(&self) -> u32 {
+        self.timer.get_max_compare_value().into() + 1
     }
 
     /// Set the duty for a given channel.
     ///
     /// The value ranges from 0 for 0% duty, to [`max_duty_cycle`](Self::max_duty_cycle) for 100% duty, both included.
-    pub fn set_duty_cycle(&mut self, duty: u16) {
+    pub fn set_duty_cycle(&mut self, duty: u32) {
         assert!(duty <= (*self).max_duty_cycle());
-        self.timer.set_compare_value(self.channel, duty.into())
+        self.timer.set_compare_value(self.channel, unwrap!(duty.try_into()))
     }
 
     /// Set the duty cycle to 0%, or always inactive.
@@ -126,21 +126,21 @@ impl<'d, T: GeneralInstance4Channel> SimplePwmChannel<'d, T> {
     ///
     /// The caller is responsible for ensuring that `num` is less than or equal to `denom`,
     /// and that `denom` is not zero.
-    pub fn set_duty_cycle_fraction(&mut self, num: u16, denom: u16) {
+    pub fn set_duty_cycle_fraction(&mut self, num: u32, denom: u32) {
         assert!(denom != 0);
         assert!(num <= denom);
         let duty = u32::from(num) * u32::from(self.max_duty_cycle()) / u32::from(denom);
 
         // This is safe because we know that `num <= denom`, so `duty <= self.max_duty_cycle()` (u16)
         #[allow(clippy::cast_possible_truncation)]
-        self.set_duty_cycle(duty as u16);
+        self.set_duty_cycle(unwrap!(duty.try_into()));
     }
 
     /// Set the duty cycle to `percent / 100`
     ///
     /// The caller is responsible for ensuring that `percent` is less than or equal to 100.
     pub fn set_duty_cycle_percent(&mut self, percent: u8) {
-        self.set_duty_cycle_fraction(u16::from(percent), 100)
+        self.set_duty_cycle_fraction(percent as u32, 100)
     }
 
     /// Get the duty for a given channel.
@@ -171,13 +171,14 @@ impl<'d, T: GeneralInstance4Channel> SimplePwmChannel<'d, T> {
     ///
     /// # Panics
     /// Panics if `dma_buf` is empty or longer than 65535 elements.
-    pub fn into_ring_buffered_channel(
+    pub fn into_ring_buffered_channel<W: Word + Into<T::Word>>(
         mut self,
         tx_dma: Peri<'d, impl super::UpDma<T>>,
-        dma_buf: &'d mut [u16],
-    ) -> RingBufferedPwmChannel<'d, T> {
+        dma_buf: &'d mut [W],
+    ) -> RingBufferedPwmChannel<'d, T, W> {
         assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
 
+        self.timer.clamp_compare_value::<W>(self.channel);
         self.timer.enable_update_dma(true);
 
         RingBufferedPwmChannel::new(
@@ -332,10 +333,27 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Get max duty value.
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
-    pub fn max_duty_cycle(&self) -> u16 {
-        let max = self.inner.get_max_compare_value();
-        assert!(max < u16::MAX as u32);
-        max as u16 + 1
+    pub fn max_duty_cycle(&self) -> u32 {
+        self.inner.get_max_compare_value().into() + 1
+    }
+
+    /// Generate a sequence of PWM waveform
+    ///
+    /// Note:
+    /// The DMA channel provided does not need to correspond to the requested channel.
+    pub async fn waveform<C: TimerChannel, W: Word + Into<T::Word>>(
+        &mut self,
+        dma: Peri<'_, impl super::Dma<T, C>>,
+        channel: Channel,
+        duty: &[W],
+    ) {
+        self.inner.enable_channel(channel, true);
+        self.inner.enable_channel(C::CHANNEL, true);
+        self.inner.clamp_compare_value::<W>(channel);
+        self.inner.set_cc_dma_selection(Ccds::ON_UPDATE);
+        self.inner.set_cc_dma_enable_state(C::CHANNEL, true);
+        self.inner.setup_channel_update_dma(dma, channel, duty).await;
+        self.inner.set_cc_dma_enable_state(C::CHANNEL, false);
     }
 
     /// Generate a sequence of PWM waveform
@@ -344,8 +362,14 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
-    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
+    pub async fn waveform_up<W: Word + Into<T::Word>>(
+        &mut self,
+        dma: Peri<'_, impl super::UpDma<T>>,
+        channel: Channel,
+        duty: &[W],
+    ) {
         self.inner.enable_channel(channel, true);
+        self.inner.clamp_compare_value::<W>(channel);
         self.inner.enable_update_dma(true);
         self.inner.setup_update_dma(dma, channel, duty).await;
         self.inner.enable_update_dma(false);
@@ -380,13 +404,21 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
     ///
-    pub async fn waveform_up_multi_channel(
+    pub async fn waveform_up_multi_channel<W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'_, impl super::UpDma<T>>,
         starting_channel: Channel,
         ending_channel: Channel,
-        duty: &[u16],
+        duty: &[W],
     ) {
+        [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
+            .iter()
+            .filter(|ch| ch.index() >= starting_channel.index())
+            .filter(|ch| ch.index() <= ending_channel.index())
+            .for_each(|ch| {
+                self.inner.enable_channel(*ch, true);
+                self.inner.clamp_compare_value::<W>(*ch);
+            });
         self.inner.enable_update_dma(true);
         self.inner
             .setup_update_dma_burst(dma, starting_channel, ending_channel, duty)
@@ -401,11 +433,11 @@ impl<'d, T: GeneralInstance4Channel> embedded_hal_1::pwm::ErrorType for SimplePw
 
 impl<'d, T: GeneralInstance4Channel> embedded_hal_1::pwm::SetDutyCycle for SimplePwmChannel<'d, T> {
     fn max_duty_cycle(&self) -> u16 {
-        self.max_duty_cycle()
+        unwrap!(self.max_duty_cycle().try_into())
     }
 
     fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
-        self.set_duty_cycle(duty);
+        self.set_duty_cycle(duty.into());
         Ok(())
     }
 
@@ -420,7 +452,7 @@ impl<'d, T: GeneralInstance4Channel> embedded_hal_1::pwm::SetDutyCycle for Simpl
     }
 
     fn set_duty_cycle_fraction(&mut self, num: u16, denom: u16) -> Result<(), Self::Error> {
-        self.set_duty_cycle_fraction(num, denom);
+        self.set_duty_cycle_fraction(num.into(), denom.into());
         Ok(())
     }
 
@@ -448,16 +480,16 @@ impl<'d, T: GeneralInstance4Channel> embedded_hal_02::Pwm for SimplePwm<'d, T> {
     }
 
     fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
-        self.inner.get_compare_value(channel)
+        self.inner.get_compare_value(channel).into()
     }
 
     fn get_max_duty(&self) -> Self::Duty {
-        self.inner.get_max_compare_value() + 1
+        self.inner.get_max_compare_value().into() + 1
     }
 
     fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
         assert!(duty <= self.max_duty_cycle() as u32);
-        self.inner.set_compare_value(channel, duty)
+        self.inner.set_compare_value(channel, unwrap!(duty.try_into()))
     }
 
     fn set_period<P>(&mut self, period: P)