201 files changed, 23747 insertions, 2513 deletions

diff --git a/.github/ci/book.sh b/.github/ci/book.sh
index 6c300bf09..a39f0dac7 100755
--- a/.github/ci/book.sh
+++ b/.github/ci/book.sh
@@ -9,7 +9,7 @@ set -euxo pipefail
 make -C docs
 
 export KUBECONFIG=/ci/secrets/kubeconfig.yml
-POD=$(kubectl -n embassy get po -l app=website -o jsonpath={.items[0].metadata.name})
+POD=$(kubectl get po -l app=website -o jsonpath={.items[0].metadata.name})
 
 mkdir -p build
 mv docs/book build/book
diff --git a/.github/ci/build-nightly.sh b/.github/ci/build-nightly.sh
index 82e9436f3..04fbd2353 100755
--- a/.github/ci/build-nightly.sh
+++ b/.github/ci/build-nightly.sh
@@ -23,7 +23,7 @@ fi
 hashtime restore /ci/cache/filetime.json || true
 hashtime save /ci/cache/filetime.json
 
-cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev d015fd5e972a3e550ebef0da6748099b88a93ba6
+cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev c60400e213f7eb0296581183140ec147dd7a848b
 
 ./ci-nightly.sh
 
diff --git a/.github/ci/build-xtensa.sh b/.github/ci/build-xtensa.sh
index 3f74b4a5a..f07816861 100755
--- a/.github/ci/build-xtensa.sh
+++ b/.github/ci/build-xtensa.sh
@@ -25,7 +25,7 @@ fi
 hashtime restore /ci/cache/filetime.json || true
 hashtime save /ci/cache/filetime.json
 
-cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev d015fd5e972a3e550ebef0da6748099b88a93ba6
+cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev c60400e213f7eb0296581183140ec147dd7a848b
 
 ./ci-xtensa.sh
 
diff --git a/.github/ci/build.sh b/.github/ci/build.sh
index 3c196f72b..cd3006c49 100755
--- a/.github/ci/build.sh
+++ b/.github/ci/build.sh
@@ -28,7 +28,7 @@ fi
 hashtime restore /ci/cache/filetime.json || true
 hashtime save /ci/cache/filetime.json
 
-cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev d015fd5e972a3e550ebef0da6748099b88a93ba6
+cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev c60400e213f7eb0296581183140ec147dd7a848b
 
 ./ci.sh
 
diff --git a/.github/ci/doc.sh b/.github/ci/doc.sh
index 535fc5262..85eed9f80 100755
--- a/.github/ci/doc.sh
+++ b/.github/ci/doc.sh
@@ -12,11 +12,11 @@ export CARGO_TARGET_DIR=/ci/cache/target
 export PATH=$CARGO_HOME/bin:$PATH
 mv rust-toolchain-nightly.toml rust-toolchain.toml
 
-cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev d015fd5e972a3e550ebef0da6748099b88a93ba6
+cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev c60400e213f7eb0296581183140ec147dd7a848b
 
 cargo embassy-devtool doc -o webroot
 
 export KUBECONFIG=/ci/secrets/kubeconfig.yml
-POD=$(kubectl -n embassy get po -l app=docserver -o jsonpath={.items[0].metadata.name})
+POD=$(kubectl get po -l app=docserver -o jsonpath={.items[0].metadata.name})
 kubectl cp webroot/crates $POD:/data
 kubectl cp webroot/static $POD:/data
diff --git a/.github/ci/janitor.sh b/.github/ci/janitor.sh
index bc43075bd..9679308f2 100755
--- a/.github/ci/janitor.sh
+++ b/.github/ci/janitor.sh
@@ -9,7 +9,7 @@ export CARGO_HOME=/ci/cache/cargo
 export CARGO_TARGET_DIR=/ci/cache/target
 export PATH=$CARGO_HOME/bin:$PATH
 
-cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev d015fd5e972a3e550ebef0da6748099b88a93ba6
+cargo install --git https://github.com/embassy-rs/cargo-embassy-devtool --locked --rev c60400e213f7eb0296581183140ec147dd7a848b
 
 cargo embassy-devtool check-crlf
 cargo embassy-devtool check-manifest
diff --git a/.github/workflows/changelog.yml b/.github/workflows/changelog.yml
index 8ee143cad..0cb66ded5 100644
--- a/.github/workflows/changelog.yml
+++ b/.github/workflows/changelog.yml
@@ -1,362 +1,362 @@
-name: Changelog check
-
-on:
-  pull_request:
-    # We will not track changes for the following packages/directories.
-    paths-ignore:
-      - "/examples/"
-      - "/docs/"
-      - "/out/"
-      - "/tests/"
-      - "/release/"
-      - "/cyw43-firmware/"
-    # Run on labeled/unlabeled in addition to defaults to detect
-    # adding/removing skip-changelog labels.
-    types: [opened, reopened, labeled, unlabeled, synchronize]
-
-jobs:
-  changelog:
-    runs-on: ubuntu-latest
-
-    steps:
-      - name: Checkout sources
-        uses: actions/checkout@v4
-
-      - name: Check which package is modified
-        uses: dorny/paths-filter@v3
-        id: changes
-        with:
-          filters: |
-            cyw43:
-            - 'cyw43/**'
-            cyw43-pio:
-            - 'cyw43-pio/**'
-            embassy-boot:
-            - 'embassy-boot/**'
-            embassy-boot-nrf:
-            - 'embassy-boot-nrf/**'
-            embassy-boot-rp:
-            - 'embassy-boot-rp/**'
-            embassy-boot-stm32:
-            - 'embassy-boot-stm32/**'
-            embassy-embedded-hal:
-            - 'embassy-embedded-hal/**'
-            embassy-executor:
-            - 'embassy-executor/**'
-            embassy-executor-macros:
-            - 'embassy-executor-macros/**'
-            embassy-executor-timer-queue:
-            - 'embassy-executor-timer-queue/**'
-            embassy-futures:
-            - 'embassy-futures/**'
-            embassy-imxrt:
-            - 'embassy-imxrt/**'
-            embassy-mspm0:
-            - 'embassy-mspm0/**'
-            embassy-net:
-            - 'embassy-net/**'
-            embassy-net-adin1110:
-            - 'embassy-net-adin1110/**'
-            embassy-net-driver:
-            - 'embassy-net-driver/**'
-            embassy-net-driver-channel:
-            - 'embassy-net-driver-channel/**'
-            embassy-net-enc28j60:
-            - 'embassy-net-enc28j60/**'
-            embassy-net-esp-hosted:
-            - 'embassy-net-esp-hosted/**'
-            embassy-net-nrf91:
-            - 'embassy-net-nrf91/**'
-            embassy-net-ppp:
-            - 'embassy-net-ppp/**'
-            embassy-net-tuntap:
-            - 'embassy-net-tuntap/**'
-            embassy-net-wiznet:
-            - 'embassy-net-wiznet/**'
-            embassy-nrf:
-            - 'embassy-nrf/**'
-            embassy-nxp:
-            - 'embassy-nxp/**'
-            embassy-rp:
-            - 'embassy-rp/**'
-            embassy-stm32:
-            - 'embassy-stm32/**'
-            embassy-stm32-wpan:
-            - 'embassy-stm32-wpan/**'
-            embassy-sync:
-            - 'embassy-sync/**'
-            embassy-time:
-            - 'embassy-time/**'
-            embassy-time-driver:
-            - 'embassy-time-driver/**'
-            embassy-time-queue-utils:
-            - 'embassy-time-queue-utils/**'
-            embassy-usb:
-            - 'embassy-usb/**'
-            embassy-usb-dfu:
-            - 'embassy-usb-dfu/**'
-            embassy-usb-driver:
-            - 'embassy-usb-driver/**'
-            embassy-usb-logger:
-            - 'embassy-usb-logger/**'
-            embassy-usb-synopsys-otg:
-            - 'embassy-usb-synopsys-otg/**'
-      - name: Check that changelog updated (cyw43)
-        if: steps.changes.outputs.cyw43 == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: cyw43/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the cyw43/CHANGELOG.md file."
-      - name: Check that changelog updated (cyw43-pio)
-        if: steps.changes.outputs.cyw43-pio == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: cyw43-pio/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the cyw43-pio/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-boot)
-        if: steps.changes.outputs.embassy-boot == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-boot/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-boot/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-boot-nrf)
-        if: steps.changes.outputs.embassy-boot-nrf == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-boot-nrf/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-boot-nrf/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-boot-rp)
-        if: steps.changes.outputs.embassy-boot-rp == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-boot-rp/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-boot-rp/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-boot-stm32)
-        if: steps.changes.outputs.embassy-boot-stm32 == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-boot-stm32/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-boot-stm32/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-embedded-hal)
-        if: steps.changes.outputs.embassy-embedded-hal == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-embedded-hal/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-embedded-hal/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-executor)
-        if: steps.changes.outputs.embassy-executor == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-executor/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-executor/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-executor-macros)
-        if: steps.changes.outputs.embassy-executor-macros == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-executor/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-executor/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-executor-timer-queue)
-        if: steps.changes.outputs.embassy-executor-timer-queue == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-executor-timer-queue/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-executor-timer-queue/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-futures)
-        if: steps.changes.outputs.embassy-futures == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-futures/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-futures/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-imxrt)
-        if: steps.changes.outputs.embassy-imxrt == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-imxrt/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-imxrt/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-mspm0)
-        if: steps.changes.outputs.embassy-mspm0 == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-mspm0/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-mspm0/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-net)
-        if: steps.changes.outputs.embassy-net == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-net/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-net-adin1110)
-        if: steps.changes.outputs.embassy-net-adin1110 == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-net-adin1110/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-adin1110/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-net-driver)
-        if: steps.changes.outputs.embassy-net-driver == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-net-driver/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-driver/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-net-driver-channel)
-        if: steps.changes.outputs.embassy-net-driver-channel == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-net-driver-channel/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-driver-channel/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-net-enc28j60)
-        if: steps.changes.outputs.embassy-net-enc28j60 == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-net-enc28j60/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-enc28j60/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-net-esp-hosted)
-        if: steps.changes.outputs.embassy-net-esp-hosted == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-net-esp-hosted/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-esp-hosted/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-net-nrf91)
-        if: steps.changes.outputs.embassy-net-nrf91 == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-net-nrf91/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-nrf91/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-net-ppp)
-        if: steps.changes.outputs.embassy-net-ppp == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-net-ppp/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-ppp/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-net-tuntap)
-        if: steps.changes.outputs.embassy-net-tuntap == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-net-tuntap/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-tuntap/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-net-wiznet)
-        if: steps.changes.outputs.embassy-net-wiznet == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-net-wiznet/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-wiznet/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-nrf)
-        if: steps.changes.outputs.embassy-nrf == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-nrf/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-nrf/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-nxp)
-        if: steps.changes.outputs.embassy-nxp == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-nxp/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-nxp/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-rp)
-        if: steps.changes.outputs.embassy-rp == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-rp/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-rp/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-stm32)
-        if: steps.changes.outputs.embassy-stm32 == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-stm32/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-stm32/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-stm32-wpan)
-        if: steps.changes.outputs.embassy-stm32-wpan == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-stm32-wpan/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-stm32-wpan/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-sync)
-        if: steps.changes.outputs.embassy-sync == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-sync/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-sync/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-time)
-        if: steps.changes.outputs.embassy-time == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-time/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-time/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-time-driver)
-        if: steps.changes.outputs.embassy-time-driver == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-time-driver/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-time-driver/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-time-queue-utils)
-        if: steps.changes.outputs.embassy-time-queue-utils == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-time-queue-utils/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-time-queue-utils/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-usb)
-        if: steps.changes.outputs.embassy-usb == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-usb/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-usb/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-usb-dfu)
-        if: steps.changes.outputs.embassy-usb-dfu == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-usb-dfu/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-usb-dfu/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-usb-driver)
-        if: steps.changes.outputs.embassy-usb-driver == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-usb-driver/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-usb-driver/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-usb-logger)
-        if: steps.changes.outputs.embassy-usb-logger == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-usb-logger/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-usb-logger/CHANGELOG.md file."
-      - name: Check that changelog updated (embassy-usb-synopsys-otg)
-        if: steps.changes.outputs.embassy-usb-synopsys-otg == 'true'
-        uses: dangoslen/changelog-enforcer@v3
-        with:
-          changeLogPath: embassy-usb-synopsys-otg/CHANGELOG.md
-          skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the embassy-usb-synopsys-otg/CHANGELOG.md file."
+# name: Changelog check
+# 
+# on:
+#   pull_request:
+#     # We will not track changes for the following packages/directories.
+#     paths-ignore:
+#       - "/examples/"
+#       - "/docs/"
+#       - "/out/"
+#       - "/tests/"
+#       - "/release/"
+#       - "/cyw43-firmware/"
+#     # Run on labeled/unlabeled in addition to defaults to detect
+#     # adding/removing skip-changelog labels.
+#     types: [opened, reopened, labeled, unlabeled, synchronize]
+# 
+# jobs:
+#   changelog:
+#     runs-on: ubuntu-latest
+# 
+#     steps:
+#       - name: Checkout sources
+#         uses: actions/checkout@v4
+# 
+#       - name: Check which package is modified
+#         uses: dorny/paths-filter@v3
+#         id: changes
+#         with:
+#           filters: |
+#             cyw43:
+#             - 'cyw43/**'
+#             cyw43-pio:
+#             - 'cyw43-pio/**'
+#             embassy-boot:
+#             - 'embassy-boot/**'
+#             embassy-boot-nrf:
+#             - 'embassy-boot-nrf/**'
+#             embassy-boot-rp:
+#             - 'embassy-boot-rp/**'
+#             embassy-boot-stm32:
+#             - 'embassy-boot-stm32/**'
+#             embassy-embedded-hal:
+#             - 'embassy-embedded-hal/**'
+#             embassy-executor:
+#             - 'embassy-executor/**'
+#             embassy-executor-macros:
+#             - 'embassy-executor-macros/**'
+#             embassy-executor-timer-queue:
+#             - 'embassy-executor-timer-queue/**'
+#             embassy-futures:
+#             - 'embassy-futures/**'
+#             embassy-imxrt:
+#             - 'embassy-imxrt/**'
+#             embassy-mspm0:
+#             - 'embassy-mspm0/**'
+#             embassy-net:
+#             - 'embassy-net/**'
+#             embassy-net-adin1110:
+#             - 'embassy-net-adin1110/**'
+#             embassy-net-driver:
+#             - 'embassy-net-driver/**'
+#             embassy-net-driver-channel:
+#             - 'embassy-net-driver-channel/**'
+#             embassy-net-enc28j60:
+#             - 'embassy-net-enc28j60/**'
+#             embassy-net-esp-hosted:
+#             - 'embassy-net-esp-hosted/**'
+#             embassy-net-nrf91:
+#             - 'embassy-net-nrf91/**'
+#             embassy-net-ppp:
+#             - 'embassy-net-ppp/**'
+#             embassy-net-tuntap:
+#             - 'embassy-net-tuntap/**'
+#             embassy-net-wiznet:
+#             - 'embassy-net-wiznet/**'
+#             embassy-nrf:
+#             - 'embassy-nrf/**'
+#             embassy-nxp:
+#             - 'embassy-nxp/**'
+#             embassy-rp:
+#             - 'embassy-rp/**'
+#             embassy-stm32:
+#             - 'embassy-stm32/**'
+#             embassy-stm32-wpan:
+#             - 'embassy-stm32-wpan/**'
+#             embassy-sync:
+#             - 'embassy-sync/**'
+#             embassy-time:
+#             - 'embassy-time/**'
+#             embassy-time-driver:
+#             - 'embassy-time-driver/**'
+#             embassy-time-queue-utils:
+#             - 'embassy-time-queue-utils/**'
+#             embassy-usb:
+#             - 'embassy-usb/**'
+#             embassy-usb-dfu:
+#             - 'embassy-usb-dfu/**'
+#             embassy-usb-driver:
+#             - 'embassy-usb-driver/**'
+#             embassy-usb-logger:
+#             - 'embassy-usb-logger/**'
+#             embassy-usb-synopsys-otg:
+#             - 'embassy-usb-synopsys-otg/**'
+#       - name: Check that changelog updated (cyw43)
+#         if: steps.changes.outputs.cyw43 == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: cyw43/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the cyw43/CHANGELOG.md file."
+#       - name: Check that changelog updated (cyw43-pio)
+#         if: steps.changes.outputs.cyw43-pio == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: cyw43-pio/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the cyw43-pio/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-boot)
+#         if: steps.changes.outputs.embassy-boot == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-boot/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-boot/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-boot-nrf)
+#         if: steps.changes.outputs.embassy-boot-nrf == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-boot-nrf/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-boot-nrf/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-boot-rp)
+#         if: steps.changes.outputs.embassy-boot-rp == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-boot-rp/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-boot-rp/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-boot-stm32)
+#         if: steps.changes.outputs.embassy-boot-stm32 == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-boot-stm32/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-boot-stm32/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-embedded-hal)
+#         if: steps.changes.outputs.embassy-embedded-hal == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-embedded-hal/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-embedded-hal/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-executor)
+#         if: steps.changes.outputs.embassy-executor == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-executor/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-executor/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-executor-macros)
+#         if: steps.changes.outputs.embassy-executor-macros == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-executor/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-executor/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-executor-timer-queue)
+#         if: steps.changes.outputs.embassy-executor-timer-queue == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-executor-timer-queue/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-executor-timer-queue/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-futures)
+#         if: steps.changes.outputs.embassy-futures == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-futures/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-futures/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-imxrt)
+#         if: steps.changes.outputs.embassy-imxrt == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-imxrt/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-imxrt/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-mspm0)
+#         if: steps.changes.outputs.embassy-mspm0 == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-mspm0/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-mspm0/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-net)
+#         if: steps.changes.outputs.embassy-net == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-net/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-net-adin1110)
+#         if: steps.changes.outputs.embassy-net-adin1110 == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-net-adin1110/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-adin1110/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-net-driver)
+#         if: steps.changes.outputs.embassy-net-driver == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-net-driver/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-driver/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-net-driver-channel)
+#         if: steps.changes.outputs.embassy-net-driver-channel == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-net-driver-channel/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-driver-channel/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-net-enc28j60)
+#         if: steps.changes.outputs.embassy-net-enc28j60 == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-net-enc28j60/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-enc28j60/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-net-esp-hosted)
+#         if: steps.changes.outputs.embassy-net-esp-hosted == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-net-esp-hosted/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-esp-hosted/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-net-nrf91)
+#         if: steps.changes.outputs.embassy-net-nrf91 == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-net-nrf91/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-nrf91/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-net-ppp)
+#         if: steps.changes.outputs.embassy-net-ppp == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-net-ppp/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-ppp/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-net-tuntap)
+#         if: steps.changes.outputs.embassy-net-tuntap == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-net-tuntap/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-tuntap/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-net-wiznet)
+#         if: steps.changes.outputs.embassy-net-wiznet == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-net-wiznet/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-net-wiznet/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-nrf)
+#         if: steps.changes.outputs.embassy-nrf == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-nrf/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-nrf/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-nxp)
+#         if: steps.changes.outputs.embassy-nxp == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-nxp/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-nxp/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-rp)
+#         if: steps.changes.outputs.embassy-rp == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-rp/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-rp/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-stm32)
+#         if: steps.changes.outputs.embassy-stm32 == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-stm32/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-stm32/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-stm32-wpan)
+#         if: steps.changes.outputs.embassy-stm32-wpan == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-stm32-wpan/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-stm32-wpan/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-sync)
+#         if: steps.changes.outputs.embassy-sync == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-sync/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-sync/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-time)
+#         if: steps.changes.outputs.embassy-time == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-time/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-time/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-time-driver)
+#         if: steps.changes.outputs.embassy-time-driver == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-time-driver/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-time-driver/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-time-queue-utils)
+#         if: steps.changes.outputs.embassy-time-queue-utils == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-time-queue-utils/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-time-queue-utils/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-usb)
+#         if: steps.changes.outputs.embassy-usb == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-usb/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-usb/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-usb-dfu)
+#         if: steps.changes.outputs.embassy-usb-dfu == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-usb-dfu/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-usb-dfu/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-usb-driver)
+#         if: steps.changes.outputs.embassy-usb-driver == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-usb-driver/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-usb-driver/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-usb-logger)
+#         if: steps.changes.outputs.embassy-usb-logger == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-usb-logger/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-usb-logger/CHANGELOG.md file."
+#       - name: Check that changelog updated (embassy-usb-synopsys-otg)
+#         if: steps.changes.outputs.embassy-usb-synopsys-otg == 'true'
+#         uses: dangoslen/changelog-enforcer@v3
+#         with:
+#           changeLogPath: embassy-usb-synopsys-otg/CHANGELOG.md
+#           skipLabels: "skip-changelog"
+#           missingUpdateErrorMessage: "Please add a changelog entry in the embassy-usb-synopsys-otg/CHANGELOG.md file."
diff --git a/README.md b/README.md
index 950d19a6d..1d6f3499d 100644
--- a/README.md
+++ b/README.md
@@ -38,7 +38,7 @@ Rust's [async/await](https://rust-lang.github.io/async-book/) allows for unprece
 
 - **Bluetooth**
     - The [trouble](https://github.com/embassy-rs/trouble) crate provides a Bluetooth Low Energy 4.x and 5.x Host that runs on any microcontroller implementing the [bt-hci](https://github.com/embassy-rs/bt-hci) traits (currently
-      `nRF52`, `rp2040`, `rp23xx` and `esp32` and `serial` controllers are supported).
+      `nRF52`, `nrf54`, `rp2040`, `rp23xx` and `esp32` and `serial` controllers are supported).
     - The [nrf-softdevice](https://github.com/embassy-rs/nrf-softdevice) crate provides Bluetooth Low Energy 4.x and 5.x support for nRF52 microcontrollers.
     - The [embassy-stm32-wpan](https://github.com/embassy-rs/embassy/tree/main/embassy-stm32-wpan) crate provides Bluetooth Low Energy 5.x support for stm32wb microcontrollers.
 
diff --git a/cyw43/CHANGELOG.md b/cyw43/CHANGELOG.md
index 9fe341357..4f0dc896b 100644
--- a/cyw43/CHANGELOG.md
+++ b/cyw43/CHANGELOG.md
@@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
+- Reset WPA security before creating secure AP
+
 ## 0.6.0 - 2025-11-27
 
 - Updated documentation for Control::join() #4678
diff --git a/cyw43/src/control.rs b/cyw43/src/control.rs
index 49e3faee4..07fa1955e 100644
--- a/cyw43/src/control.rs
+++ b/cyw43/src/control.rs
@@ -436,6 +436,9 @@ impl<'a> Control<'a> {
         // Set wifi up again
         self.up().await;
 
+        // Disable authentication
+        self.ioctl_set_u32(Ioctl::SetAuth, 0, AUTH_OPEN).await;
+
         // Turn on AP mode
         self.ioctl_set_u32(Ioctl::SetAp, 0, 1).await;
 
@@ -470,8 +473,6 @@ impl<'a> Control<'a> {
             pfi.passphrase[..passphrase.as_bytes().len()].copy_from_slice(passphrase.as_bytes());
             self.ioctl(IoctlType::Set, Ioctl::SetWsecPmk, 0, &mut pfi.to_bytes())
                 .await;
-        } else {
-            self.ioctl_set_u32(Ioctl::SetAuth, 0, 0).await;
         }
 
         // Change mutlicast rate from 1 Mbps to 11 Mbps
@@ -547,6 +548,14 @@ impl<'a> Control<'a> {
         n
     }
 
+    /// Retrieve the latest RSSI value
+    pub async fn get_rssi(&mut self) -> i32 {
+        let mut rssi_buf = [0u8; 4];
+        let n = self.ioctl(IoctlType::Get, Ioctl::GetRssi, 0, &mut rssi_buf).await;
+        assert_eq!(n, 4);
+        i32::from_ne_bytes(rssi_buf)
+    }
+
     async fn set_iovar_u32x2(&mut self, name: &str, val1: u32, val2: u32) {
         let mut buf = [0; 8];
         buf[0..4].copy_from_slice(&val1.to_le_bytes());
diff --git a/docs/pages/mcxa.adoc b/docs/pages/mcxa.adoc
new file mode 100644
index 000000000..e2284f45f
--- /dev/null
+++ b/docs/pages/mcxa.adoc
@@ -0,0 +1,18 @@
+= Embassy MCX-A HAL
+
+The link: link:https://github.com/embassy-rs/embassy/tree/main/embassy-mcxa[Embassy MCX-A HAL] is based on the following PAC (Peripheral Access Crate):
+
+* link:https://github.com/OpenDevicePartnership/mcxa-pac[mcxa-pac]
+
+== Peripherals
+
+The following peripherals have a HAL implementation at present
+
+* Clocks
+* GPIO
+* ADC
+* CLKOUT
+* I2C
+* LPUart
+* OSTimer
+* RTC
diff --git a/docs/pages/overview.adoc b/docs/pages/overview.adoc
index 18eaaeb75..894789d33 100644
--- a/docs/pages/overview.adoc
+++ b/docs/pages/overview.adoc
@@ -27,7 +27,7 @@ Embassy provides implementations of both async and blocking APIs where it makes
 The Embassy project maintains HALs for select hardware, but you can still use HALs from other projects with Embassy.
 
 * link:https://docs.embassy.dev/embassy-stm32/[embassy-stm32], for all STM32 microcontroller families.
-* link:https://docs.embassy.dev/embassy-nrf/[embassy-nrf], for the Nordic Semiconductor nRF52, nRF53, nRF91 series.
+* link:https://docs.embassy.dev/embassy-nrf/[embassy-nrf], for the Nordic Semiconductor nRF52, nRF53, nRF54, nRF91 series.
 * link:https://docs.embassy.dev/embassy-rp/[embassy-rp], for the Raspberry Pi RP2040 as well as RP235x microcontroller.
 * link:https://docs.embassy.dev/embassy-mspm0/[embassy-mspm0], for the Texas Instruments MSPM0 microcontrollers.
 * link:https://github.com/esp-rs/esp-hal[esp-hal], for the Espressif Systems ESP32 series of chips.
@@ -42,7 +42,9 @@ as they implement both the link:https://github.com/rust-embedded/embedded-hal[Em
 The link:https://docs.embassy.dev/embassy-net/[embassy-net] network stack implements extensive networking functionality, including Ethernet, IP, TCP, UDP, ICMP and DHCP. Async drastically simplifies managing timeouts and serving multiple connections concurrently. Several drivers for WiFi and Ethernet chips can be found.
 
 === Bluetooth
-The link:https://github.com/embassy-rs/nrf-softdevice[nrf-softdevice] crate provides Bluetooth Low Energy 4.x and 5.x support for nRF52 microcontrollers.
+
+* The link:https://github.com/embassy-rs/trouble[trouble] crate provides a Bluetooth Low Energy 4.x and 5.x Host that runs on any microcontroller implementing the link:https://github.com/embassy-rs/bt-hci[bt-hci] traits (currently `nRF52`, `nrf54`, `rp2040`, `rp23xx` and `esp32` and `serial` controllers are supported).
+* The link:https://github.com/embassy-rs/nrf-softdevice[nrf-softdevice] crate provides Bluetooth Low Energy 4.x and 5.x support for nRF52 microcontrollers.
 
 === LoRa
 link:https://github.com/lora-rs/lora-rs[lora-rs] supports LoRa networking on a wide range of LoRa radios, fully integrated with a Rust LoRaWAN implementation. It provides four crates — lora-phy, lora-modulation, lorawan-encoding, and lorawan-device — and basic examples for various development boards. It has support for STM32WL wireless microcontrollers or Semtech SX127x transceivers, among others.
diff --git a/embassy-mcxa/.gitignore b/embassy-mcxa/.gitignore
new file mode 100644
index 000000000..d128a49cb
--- /dev/null
+++ b/embassy-mcxa/.gitignore
@@ -0,0 +1,19 @@
+# Rust
+/target/
+
+# IDE
+.vscode/
+.idea/
+
+# OS
+.DS_Store
+Thumbs.db
+
+# Embedded
+*.bin
+*.hex
+*.elf
+*.map
+
+# Debug
+*.log
diff --git a/embassy-mcxa/Cargo.toml b/embassy-mcxa/Cargo.toml
new file mode 100644
index 000000000..cb985a2e9
--- /dev/null
+++ b/embassy-mcxa/Cargo.toml
@@ -0,0 +1,69 @@
+[package]
+name = "embassy-mcxa"
+version = "0.1.0"
+edition = "2021"
+license = "MIT OR Apache-2.0"
+description = "Embassy Hardware Abstraction Layer (HAL) for NXP MCXA series of MCUs"
+repository = "https://github.com/embassy-rs/embassy"
+keywords = ["embedded", "hal", "nxp", "mcxa", "embassy"]
+categories = ["embedded", "hardware-support", "no-std"]
+documentation = "https://docs.embassy.dev/embassy-mcxa"
+
+[package.metadata.embassy]
+build = [
+    {target = "thumbv8m.main-none-eabihf", features = ["defmt", "time", "unstable-pac"]},
+]
+
+[package.metadata.embassy_docs]
+src_base = "https://github.com/embassy-rs/embassy/blob/embassy-mcxa-v$VERSION/embassy-mcxa/src/"
+src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-mcxa/src/"
+
+features = ["defmt", "time", "unstable-pac"]
+flavors = [
+    { name = "mcx-a256", target = "thumbv8m.main-none-eabihf" },
+]
+
+[dependencies]
+cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
+# If you would like "device" to be an optional feature, please open an issue.
+cortex-m-rt = { version = "0.7", features = ["device"] }
+critical-section = "1.2.0"
+defmt = { version = "1.0", optional = true }
+embassy-embedded-hal = "0.5.0"
+embassy-hal-internal = { version = "0.3.0", features = ["cortex-m", "prio-bits-3"] }
+embassy-sync = "0.7.2"
+embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
+embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
+embedded-hal-async = { version = "1.0" }
+embedded-hal-nb = { version = "1.0" }
+embedded-io = "0.6"
+embedded-io-async = { version = "0.6.1" }
+heapless = "0.8"
+mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt", "critical-section"], version = "0.1.0", rev = "02bd04a21ef8f8f67f88239ff5df765bb7e60fd8" }
+nb = "1.1.0"
+paste = "1.0.15"
+maitake-sync = { version = "0.2.2", default-features = false, features = ["critical-section", "no-cache-pad"] }
+
+# `time` dependencies
+embassy-time = { version = "0.5.0", optional = true }
+embassy-time-driver = { version = "0.2.1", optional = true }
+
+[features]
+default = ["rt"]
+
+# Base defmt feature enables core + panic handler
+# Use with one logger feature: defmt-rtt (preferred) or defmt-uart (fallback)
+defmt = ["dep:defmt", "mcxa-pac/defmt"]
+
+unstable-pac = []
+
+# dummy feature to silence embassy-hal-internal lint
+#
+# This feature makes no change to embassy-mcxa's operation.
+rt = []
+
+# Embassy time
+time = [
+    "dep:embassy-time",
+    "dep:embassy-time-driver",
+]
diff --git a/embassy-mcxa/README.md b/embassy-mcxa/README.md
new file mode 100644
index 000000000..079eeb487
--- /dev/null
+++ b/embassy-mcxa/README.md
@@ -0,0 +1,5 @@
+# Embassy MCXA256 HAL
+
+A Hardware Abstraction Layer (HAL) for the NXP MCXA256 microcontroller
+using the Embassy async framework. This HAL provides safe, idiomatic
+Rust interfaces for GPIO, UART, and OSTIMER peripherals.
diff --git a/embassy-mcxa/src/adc.rs b/embassy-mcxa/src/adc.rs
new file mode 100644
index 000000000..d7d17cf5f
--- /dev/null
+++ b/embassy-mcxa/src/adc.rs
@@ -0,0 +1,752 @@
+//! ADC driver
+use core::marker::PhantomData;
+
+use embassy_hal_internal::{Peri, PeripheralType};
+use maitake_sync::WaitCell;
+use paste::paste;
+
+use crate::clocks::periph_helpers::{AdcClockSel, AdcConfig, Div4};
+use crate::clocks::{ClockError, Gate, PoweredClock, enable_and_reset};
+use crate::gpio::{GpioPin, SealedPin};
+use crate::interrupt::typelevel::{Handler, Interrupt};
+use crate::pac;
+use crate::pac::adc1::cfg::{HptExdi, Pwrsel, Refsel, Tcmdres, Tprictrl, Tres};
+use crate::pac::adc1::cmdh1::{Avgs, Cmpen, Next, Sts};
+use crate::pac::adc1::cmdl1::{Adch, Mode};
+use crate::pac::adc1::ctrl::CalAvgs;
+use crate::pac::adc1::tctrl::{Tcmd, Tpri};
+
+const G_LPADC_RESULT_SHIFT: u32 = 0;
+
+/// Trigger priority policy for ADC conversions.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(u8)]
+pub enum TriggerPriorityPolicy {
+    ConvPreemptImmediatelyNotAutoResumed = 0,
+    ConvPreemptSoftlyNotAutoResumed = 1,
+    ConvPreemptImmediatelyAutoRestarted = 4,
+    ConvPreemptSoftlyAutoRestarted = 5,
+    ConvPreemptImmediatelyAutoResumed = 12,
+    ConvPreemptSoftlyAutoResumed = 13,
+    ConvPreemptSubsequentlyNotAutoResumed = 2,
+    ConvPreemptSubsequentlyAutoRestarted = 6,
+    ConvPreemptSubsequentlyAutoResumed = 14,
+    TriggerPriorityExceptionDisabled = 16,
+}
+
+/// Configuration for the LPADC peripheral.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct LpadcConfig {
+    /// Control system transition to Stop and Wait power modes while ADC is converting.
+    /// When enabled in Doze mode, immediate entries to Wait or Stop are allowed.
+    /// When disabled, the ADC will wait for the current averaging iteration/FIFO storage to complete before acknowledging stop or wait mode entry.
+    pub enable_in_doze_mode: bool,
+    /// Auto-Calibration Averages.
+    pub conversion_average_mode: CalAvgs,
+    /// ADC analog circuits are pre-enabled and ready to execute conversions without startup delays(at the cost of higher DC current consumption).
+    pub enable_analog_preliminary: bool,
+    /// Power-up delay value (in ADC clock cycles)
+    pub power_up_delay: u8,
+    /// Reference voltage source selection
+    pub reference_voltage_source: Refsel,
+    /// Power configuration selection.
+    pub power_level_mode: Pwrsel,
+    /// Trigger priority policy for handling multiple triggers
+    pub trigger_priority_policy: TriggerPriorityPolicy,
+    /// Enables the ADC pausing function. When enabled, a programmable delay is inserted during command execution sequencing between LOOP iterations,
+    /// between commands in a sequence, and between conversions when command is executing in "Compare Until True" configuration.
+    pub enable_conv_pause: bool,
+    /// Controls the duration of pausing during command execution sequencing. The pause delay is a count of (convPauseDelay*4) ADCK cycles.
+    /// Only available when ADC pausing function is enabled. The available value range is in 9-bit.
+    pub conv_pause_delay: u16,
+    /// FIFO watermark level for interrupt generation.
+    /// When the number of datawords stored in the ADC Result FIFO is greater than the value in this field,
+    /// the ready flag would be asserted to indicate stored data has reached the programmable threshold.
+    pub fifo_watermark: u8,
+    /// Power configuration (normal/deep sleep behavior)
+    pub power: PoweredClock,
+    /// ADC clock source selection
+    pub source: AdcClockSel,
+    /// Clock divider for ADC clock
+    pub div: Div4,
+}
+
+impl Default for LpadcConfig {
+    fn default() -> Self {
+        LpadcConfig {
+            enable_in_doze_mode: true,
+            conversion_average_mode: CalAvgs::NoAverage,
+            enable_analog_preliminary: false,
+            power_up_delay: 0x80,
+            reference_voltage_source: Refsel::Option1,
+            power_level_mode: Pwrsel::Lowest,
+            trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed,
+            enable_conv_pause: false,
+            conv_pause_delay: 0,
+            fifo_watermark: 0,
+            power: PoweredClock::NormalEnabledDeepSleepDisabled,
+            source: AdcClockSel::FroLfDiv,
+            div: Div4::no_div(),
+        }
+    }
+}
+
+/// Configuration for a conversion command.
+///
+/// Defines the parameters for a single ADC conversion operation.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct ConvCommandConfig {
+    pub channel_number: Adch,
+    pub chained_next_command_number: Next,
+    pub enable_auto_channel_increment: bool,
+    pub loop_count: u8,
+    pub hardware_average_mode: Avgs,
+    pub sample_time_mode: Sts,
+    pub hardware_compare_mode: Cmpen,
+    pub hardware_compare_value_high: u32,
+    pub hardware_compare_value_low: u32,
+    pub conversion_resolution_mode: Mode,
+    pub enable_wait_trigger: bool,
+}
+
+/// Configuration for a conversion trigger.
+///
+/// Defines how a trigger initiates ADC conversions.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct ConvTriggerConfig {
+    pub target_command_id: Tcmd,
+    pub delay_power: u8,
+    pub priority: Tpri,
+    pub enable_hardware_trigger: bool,
+}
+
+/// Shorthand for `Result<T>`.
+pub type Result<T> = core::result::Result<T, Error>;
+
+/// ADC Error types
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    /// FIFO is empty, no conversion result available
+    FifoEmpty,
+    /// Invalid configuration
+    InvalidConfig,
+    /// Clock configuration error.
+    ClockSetup(ClockError),
+}
+
+/// Result of an ADC conversion.
+///
+/// Contains the conversion value and metadata about the conversion.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct ConvResult {
+    pub command_id_source: u8,
+    pub loop_count_index: u8,
+    pub trigger_id_source: u8,
+    pub conv_value: u16,
+}
+
+/// ADC interrupt handler.
+pub struct InterruptHandler<I: Instance> {
+    _phantom: PhantomData<I>,
+}
+
+/// ADC driver instance.
+pub struct Adc<'a, I: Instance, M: ModeAdc> {
+    _inst: PhantomData<&'a mut I>,
+    _phantom: PhantomData<M>,
+}
+
+impl<'a, I: Instance> Adc<'a, I, Blocking> {
+    /// Create a new blocking instance of the ADC driver.
+    /// # Arguments
+    /// * `_inst` - ADC peripheral instance
+    /// * `pin` - GPIO pin to use for ADC
+    /// * `config` - ADC configuration
+    pub fn new_blocking(_inst: Peri<'a, I>, pin: Peri<'a, impl AdcPin<I>>, config: LpadcConfig) -> Result<Self> {
+        Self::new_inner(_inst, pin, config)
+    }
+}
+
+impl<'a, I: Instance> Adc<'a, I, Async> {
+    /// Initialize ADC with interrupt support.
+    ///
+    /// # Arguments
+    /// * `_inst` - ADC peripheral instance
+    /// * `pin` - GPIO pin to use for ADC
+    /// * `_irq` - Interrupt binding for this ADC instance
+    /// * `config` - ADC configuration
+    pub fn new_async(
+        _inst: Peri<'a, I>,
+        pin: Peri<'a, impl AdcPin<I>>,
+        _irq: impl crate::interrupt::typelevel::Binding<I::Interrupt, InterruptHandler<I>> + 'a,
+        config: LpadcConfig,
+    ) -> Result<Self> {
+        let adc = Self::new_inner(_inst, pin, config);
+
+        I::Interrupt::unpend();
+        unsafe { I::Interrupt::enable() };
+
+        adc
+    }
+
+    /// Read ADC value asynchronously.
+    ///
+    /// Performs a single ADC conversion and returns the result when the ADC interrupt is triggered.
+    ///
+    /// The function:
+    /// 1. Enables the FIFO watermark interrupt
+    /// 2. Triggers a software conversion on trigger 0
+    /// 3. Waits for the conversion to complete
+    /// 4. Returns the conversion result
+    ///
+    /// # Returns
+    /// 16-bit ADC conversion value
+    pub async fn read(&mut self) -> Result<u16> {
+        let wait = I::wait_cell().subscribe().await;
+
+        Adc::<'a, I, Async>::enable_interrupt(self, 0x1);
+        Adc::<'a, I, Async>::do_software_trigger(self, 1);
+
+        let _ = wait.await;
+
+        let result = Adc::<'a, I, Async>::get_conv_result(self).unwrap().conv_value >> G_LPADC_RESULT_SHIFT;
+        Ok(result)
+    }
+}
+
+impl<'a, I: Instance, M: ModeAdc> Adc<'a, I, M> {
+    /// Internal initialization function shared by `new_async` and `new_blocking`.
+    fn new_inner(_inst: Peri<'a, I>, pin: Peri<'a, impl AdcPin<I>>, config: LpadcConfig) -> Result<Self> {
+        let adc = I::ptr();
+
+        _ = unsafe {
+            enable_and_reset::<I>(&AdcConfig {
+                power: config.power,
+                source: config.source,
+                div: config.div,
+            })
+            .map_err(Error::ClockSetup)?
+        };
+
+        pin.mux();
+
+        /* Reset the module. */
+        adc.ctrl().modify(|_, w| w.rst().held_in_reset());
+        adc.ctrl().modify(|_, w| w.rst().released_from_reset());
+
+        adc.ctrl().modify(|_, w| w.rstfifo0().trigger_reset());
+
+        /* Disable the module before setting configuration. */
+        adc.ctrl().modify(|_, w| w.adcen().disabled());
+
+        /* Configure the module generally. */
+        if config.enable_in_doze_mode {
+            adc.ctrl().modify(|_, w| w.dozen().enabled());
+        } else {
+            adc.ctrl().modify(|_, w| w.dozen().disabled());
+        }
+
+        /* Set calibration average mode. */
+        adc.ctrl()
+            .modify(|_, w| w.cal_avgs().variant(config.conversion_average_mode));
+
+        adc.cfg().write(|w| unsafe {
+            let w = if config.enable_analog_preliminary {
+                w.pwren().pre_enabled()
+            } else {
+                w
+            };
+
+            w.pudly()
+                .bits(config.power_up_delay)
+                .refsel()
+                .variant(config.reference_voltage_source)
+                .pwrsel()
+                .variant(config.power_level_mode)
+                .tprictrl()
+                .variant(match config.trigger_priority_policy {
+                    TriggerPriorityPolicy::ConvPreemptSoftlyNotAutoResumed
+                    | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted
+                    | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => Tprictrl::FinishCurrentOnPriority,
+                    TriggerPriorityPolicy::ConvPreemptSubsequentlyNotAutoResumed
+                    | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted
+                    | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tprictrl::FinishSequenceOnPriority,
+                    _ => Tprictrl::AbortCurrentOnPriority,
+                })
+                .tres()
+                .variant(match config.trigger_priority_policy {
+                    TriggerPriorityPolicy::ConvPreemptImmediatelyAutoRestarted
+                    | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted
+                    | TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed
+                    | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed
+                    | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted
+                    | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tres::Enabled,
+                    _ => Tres::Disabled,
+                })
+                .tcmdres()
+                .variant(match config.trigger_priority_policy {
+                    TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed
+                    | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed
+                    | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed
+                    | TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => Tcmdres::Enabled,
+                    _ => Tcmdres::Disabled,
+                })
+                .hpt_exdi()
+                .variant(match config.trigger_priority_policy {
+                    TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => HptExdi::Disabled,
+                    _ => HptExdi::Enabled,
+                })
+        });
+
+        if config.enable_conv_pause {
+            adc.pause()
+                .modify(|_, w| unsafe { w.pauseen().enabled().pausedly().bits(config.conv_pause_delay) });
+        } else {
+            adc.pause().write(|w| unsafe { w.bits(0) });
+        }
+
+        adc.fctrl0()
+            .write(|w| unsafe { w.fwmark().bits(config.fifo_watermark) });
+
+        // Enable ADC
+        adc.ctrl().modify(|_, w| w.adcen().enabled());
+
+        Ok(Self {
+            _inst: PhantomData,
+            _phantom: PhantomData,
+        })
+    }
+
+    /// Deinitialize the ADC peripheral.
+    pub fn deinit(&self) {
+        let adc = I::ptr();
+        adc.ctrl().modify(|_, w| w.adcen().disabled());
+    }
+
+    /// Perform offset calibration.
+    /// Waits for calibration to complete before returning.
+    pub fn do_offset_calibration(&self) {
+        let adc = I::ptr();
+        // Enable calibration mode
+        adc.ctrl()
+            .modify(|_, w| w.calofs().offset_calibration_request_pending());
+
+        // Wait for calibration to complete (polling status register)
+        while adc.stat().read().cal_rdy().is_not_set() {}
+    }
+
+    /// Calculate gain conversion result from gain adjustment factor.
+    ///
+    /// # Arguments
+    /// * `gain_adjustment` - Gain adjustment factor
+    ///
+    /// # Returns
+    /// Gain calibration register value
+    pub fn get_gain_conv_result(&self, mut gain_adjustment: f32) -> u32 {
+        let mut gcra_array = [0u32; 17];
+        let mut gcalr: u32 = 0;
+
+        for i in (1..=17).rev() {
+            let shift = 16 - (i - 1);
+            let step = 1.0 / (1u32 << shift) as f32;
+            let tmp = (gain_adjustment / step) as u32;
+            gcra_array[i - 1] = tmp;
+            gain_adjustment -= tmp as f32 * step;
+        }
+
+        for i in (1..=17).rev() {
+            gcalr += gcra_array[i - 1] << (i - 1);
+        }
+        gcalr
+    }
+
+    /// Perform automatic gain calibration.
+    pub fn do_auto_calibration(&self) {
+        let adc = I::ptr();
+        adc.ctrl().modify(|_, w| w.cal_req().calibration_request_pending());
+
+        while adc.gcc0().read().rdy().is_gain_cal_not_valid() {}
+
+        let mut gcca = adc.gcc0().read().gain_cal().bits() as u32;
+        if gcca & ((0xFFFF + 1) >> 1) != 0 {
+            gcca |= !0xFFFF;
+        }
+
+        let gcra = 131072.0 / (131072.0 - gcca as f32);
+
+        // Write to GCR0
+        adc.gcr0().write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) });
+
+        adc.gcr0().modify(|_, w| w.rdy().set_bit());
+
+        // Wait for calibration to complete (polling status register)
+        while adc.stat().read().cal_rdy().is_not_set() {}
+    }
+
+    /// Trigger ADC conversion(s) via software.
+    ///
+    /// Initiates conversion(s) for the trigger(s) specified in the bitmask.
+    /// Each bit in the mask corresponds to a trigger ID (bit 0 = trigger 0, etc.).
+    ///
+    /// # Arguments
+    /// * `trigger_id_mask` - Bitmask of trigger IDs to activate (bit N = trigger N)
+    pub fn do_software_trigger(&self, trigger_id_mask: u32) {
+        let adc = I::ptr();
+        adc.swtrig().write(|w| unsafe { w.bits(trigger_id_mask) });
+    }
+
+    /// Get default conversion command configuration.
+    /// # Returns
+    /// Default conversion command configuration
+    pub fn get_default_conv_command_config(&self) -> ConvCommandConfig {
+        ConvCommandConfig {
+            channel_number: Adch::SelectCh0,
+            chained_next_command_number: Next::NoNextCmdTerminateOnFinish,
+            enable_auto_channel_increment: false,
+            loop_count: 0,
+            hardware_average_mode: Avgs::NoAverage,
+            sample_time_mode: Sts::Sample3p5,
+            hardware_compare_mode: Cmpen::DisabledAlwaysStoreResult,
+            hardware_compare_value_high: 0,
+            hardware_compare_value_low: 0,
+            conversion_resolution_mode: Mode::Data12Bits,
+            enable_wait_trigger: false,
+        }
+    }
+
+    /// Set conversion command configuration.
+    ///
+    /// Configures a conversion command slot with the specified parameters.
+    /// Commands define how conversions are performed (channel, resolution, etc.).
+    ///
+    /// # Arguments
+    /// * `index` - Command index
+    /// * `config` - Command configuration
+    ///
+    /// # Returns
+    /// * `Ok(())` if the command was configured successfully
+    /// * `Err(Error::InvalidConfig)` if the index is out of range
+    pub fn set_conv_command_config(&self, index: u32, config: &ConvCommandConfig) -> Result<()> {
+        let adc = I::ptr();
+
+        if index < 1 || index > 7 {
+            return Err(Error::InvalidConfig);
+        }
+
+        macro_rules! write_cmd {
+            ($idx:expr) => {{
+                paste! {
+                    adc.[<cmdl $idx>]().write(|w| {
+                        w.adch()
+                            .variant(config.channel_number)
+                            .mode()
+                            .variant(config.conversion_resolution_mode)
+                    });
+                    adc.[<cmdh $idx>]().write(|w| unsafe {
+                        w.next()
+                            .variant(config.chained_next_command_number)
+                            .loop_()
+                            .bits(config.loop_count)
+                            .avgs()
+                            .variant(config.hardware_average_mode)
+                            .sts()
+                            .variant(config.sample_time_mode)
+                            .cmpen()
+                            .variant(config.hardware_compare_mode)
+                            .wait_trig()
+                            .bit(config.enable_wait_trigger)
+                            .lwi()
+                            .bit(config.enable_auto_channel_increment)
+                    });
+                }
+            }};
+        }
+
+        match index {
+            1 => write_cmd!(1),
+            2 => write_cmd!(2),
+            3 => write_cmd!(3),
+            4 => write_cmd!(4),
+            5 => write_cmd!(5),
+            6 => write_cmd!(6),
+            7 => write_cmd!(7),
+            _ => unreachable!(),
+        }
+
+        Ok(())
+    }
+
+    /// Get default conversion trigger configuration.
+    ///
+    /// # Returns
+    /// Default conversion trigger configuration
+    pub fn get_default_conv_trigger_config(&self) -> ConvTriggerConfig {
+        ConvTriggerConfig {
+            target_command_id: Tcmd::NotValid,
+            delay_power: 0,
+            priority: Tpri::HighestPriority,
+            enable_hardware_trigger: false,
+        }
+    }
+
+    /// Set conversion trigger configuration.
+    ///
+    /// Configures a trigger to initiate conversions. Triggers can be
+    /// activated by software or hardware signals.
+    ///
+    /// # Arguments
+    /// * `trigger_id` - Trigger index (0-15)
+    /// * `config` - Trigger configuration
+    pub fn set_conv_trigger_config(&self, trigger_id: usize, config: &ConvTriggerConfig) {
+        let adc = I::ptr();
+        let tctrl = &adc.tctrl(trigger_id);
+
+        tctrl.write(|w| unsafe {
+            let w = w.tcmd().variant(config.target_command_id);
+            let w = w.tdly().bits(config.delay_power);
+            w.tpri().variant(config.priority);
+            if config.enable_hardware_trigger {
+                w.hten().enabled()
+            } else {
+                w
+            }
+        });
+    }
+
+    /// Reset the FIFO buffer.
+    ///
+    /// Clears all pending conversion results from the FIFO.
+    pub fn do_reset_fifo(&self) {
+        let adc = I::ptr();
+        adc.ctrl().modify(|_, w| w.rstfifo0().trigger_reset());
+    }
+
+    /// Enable ADC interrupts.
+    ///
+    /// Enables the interrupt sources specified in the bitmask.
+    ///
+    /// # Arguments
+    /// * `mask` - Bitmask of interrupt sources to enable
+    pub fn enable_interrupt(&self, mask: u32) {
+        let adc = I::ptr();
+        adc.ie().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
+    }
+
+    /// Disable ADC interrupts.
+    ///
+    /// Disables the interrupt sources specified in the bitmask.
+    ///
+    /// # Arguments
+    /// * `mask` - Bitmask of interrupt sources to disable
+    pub fn disable_interrupt(&self, mask: u32) {
+        let adc = I::ptr();
+        adc.ie().modify(|r, w| unsafe { w.bits(r.bits() & !mask) });
+    }
+
+    /// Get conversion result from FIFO.
+    ///
+    /// Reads and returns the next conversion result from the FIFO.
+    /// Returns `None` if the FIFO is empty.
+    ///
+    /// # Returns
+    /// - `Some(ConvResult)` if a result is available
+    /// - `Err(Error::FifoEmpty)` if the FIFO is empty
+    pub fn get_conv_result(&self) -> Result<ConvResult> {
+        let adc = I::ptr();
+        let fifo = adc.resfifo0().read();
+        if !fifo.valid().is_valid() {
+            return Err(Error::FifoEmpty);
+        }
+
+        Ok(ConvResult {
+            command_id_source: fifo.cmdsrc().bits(),
+            loop_count_index: fifo.loopcnt().bits(),
+            trigger_id_source: fifo.tsrc().bits(),
+            conv_value: fifo.d().bits(),
+        })
+    }
+}
+
+impl<T: Instance> Handler<T::Interrupt> for InterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        T::ptr().ie().modify(|r, w| w.bits(r.bits() & !0x1));
+        T::wait_cell().wake();
+    }
+}
+
+mod sealed {
+    /// Seal a trait
+    pub trait Sealed {}
+}
+
+impl<I: GpioPin> sealed::Sealed for I {}
+
+trait SealedInstance {
+    fn ptr() -> &'static pac::adc0::RegisterBlock;
+    fn wait_cell() -> &'static WaitCell;
+}
+
+/// ADC Instance
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType + Gate<MrccPeriphConfig = AdcConfig> {
+    /// Interrupt for this ADC instance.
+    type Interrupt: Interrupt;
+}
+
+macro_rules! impl_instance {
+    ($($n:expr),*) => {
+        $(
+            paste!{
+                impl SealedInstance for crate::peripherals::[<ADC $n>] {
+                    fn ptr() -> &'static pac::adc0::RegisterBlock {
+                        unsafe { &*pac::[<Adc $n>]::ptr() }
+                    }
+
+                    fn wait_cell() -> &'static WaitCell {
+                        static WAIT_CELL: WaitCell = WaitCell::new();
+                        &WAIT_CELL
+                    }
+
+                }
+
+                impl Instance for crate::peripherals::[<ADC $n>] {
+                    type Interrupt = crate::interrupt::typelevel::[<ADC $n>];
+                }
+            }
+        )*
+    };
+}
+
+impl_instance!(0, 1, 2, 3);
+
+pub trait AdcPin<Instance>: GpioPin + sealed::Sealed + PeripheralType {
+    /// Set the given pin to the correct muxing state
+    fn mux(&self);
+}
+
+/// Driver mode.
+#[allow(private_bounds)]
+pub trait ModeAdc: sealed::Sealed {}
+
+/// Blocking mode.
+pub struct Blocking;
+impl sealed::Sealed for Blocking {}
+impl ModeAdc for Blocking {}
+
+/// Async mode.
+pub struct Async;
+impl sealed::Sealed for Async {}
+impl ModeAdc for Async {}
+
+macro_rules! impl_pin {
+    ($pin:ident, $peri:ident, $func:ident, $trait:ident) => {
+        impl $trait<crate::peripherals::$peri> for crate::peripherals::$pin {
+            fn mux(&self) {
+                self.set_pull(crate::gpio::Pull::Disabled);
+                self.set_slew_rate(crate::gpio::SlewRate::Fast.into());
+                self.set_drive_strength(crate::gpio::DriveStrength::Normal.into());
+                self.set_function(crate::pac::port0::pcr0::Mux::$func);
+            }
+        }
+    };
+}
+
+impl_pin!(P2_0, ADC0, Mux0, AdcPin);
+impl_pin!(P2_4, ADC0, Mux0, AdcPin);
+impl_pin!(P2_15, ADC0, Mux0, AdcPin);
+impl_pin!(P2_3, ADC0, Mux0, AdcPin);
+impl_pin!(P2_2, ADC0, Mux0, AdcPin);
+impl_pin!(P2_12, ADC0, Mux0, AdcPin);
+impl_pin!(P2_16, ADC0, Mux0, AdcPin);
+impl_pin!(P2_7, ADC0, Mux0, AdcPin);
+impl_pin!(P0_18, ADC0, Mux0, AdcPin);
+impl_pin!(P0_19, ADC0, Mux0, AdcPin);
+impl_pin!(P0_20, ADC0, Mux0, AdcPin);
+impl_pin!(P0_21, ADC0, Mux0, AdcPin);
+impl_pin!(P0_22, ADC0, Mux0, AdcPin);
+impl_pin!(P0_23, ADC0, Mux0, AdcPin);
+impl_pin!(P0_3, ADC0, Mux0, AdcPin);
+impl_pin!(P0_6, ADC0, Mux0, AdcPin);
+impl_pin!(P1_0, ADC0, Mux0, AdcPin);
+impl_pin!(P1_1, ADC0, Mux0, AdcPin);
+impl_pin!(P1_2, ADC0, Mux0, AdcPin);
+impl_pin!(P1_3, ADC0, Mux0, AdcPin);
+impl_pin!(P1_4, ADC0, Mux0, AdcPin);
+impl_pin!(P1_5, ADC0, Mux0, AdcPin);
+impl_pin!(P1_6, ADC0, Mux0, AdcPin);
+impl_pin!(P1_7, ADC0, Mux0, AdcPin);
+impl_pin!(P1_10, ADC0, Mux0, AdcPin);
+
+impl_pin!(P2_1, ADC1, Mux0, AdcPin);
+impl_pin!(P2_5, ADC1, Mux0, AdcPin);
+impl_pin!(P2_19, ADC1, Mux0, AdcPin);
+impl_pin!(P2_6, ADC1, Mux0, AdcPin);
+impl_pin!(P2_3, ADC1, Mux0, AdcPin);
+impl_pin!(P2_13, ADC1, Mux0, AdcPin);
+impl_pin!(P2_17, ADC1, Mux0, AdcPin);
+impl_pin!(P2_7, ADC1, Mux0, AdcPin);
+impl_pin!(P1_10, ADC1, Mux0, AdcPin);
+impl_pin!(P1_11, ADC1, Mux0, AdcPin);
+impl_pin!(P1_12, ADC1, Mux0, AdcPin);
+impl_pin!(P1_13, ADC1, Mux0, AdcPin);
+impl_pin!(P1_14, ADC1, Mux0, AdcPin);
+impl_pin!(P1_15, ADC1, Mux0, AdcPin);
+impl_pin!(P1_16, ADC1, Mux0, AdcPin);
+impl_pin!(P1_17, ADC1, Mux0, AdcPin);
+impl_pin!(P1_18, ADC1, Mux0, AdcPin);
+impl_pin!(P1_19, ADC1, Mux0, AdcPin);
+impl_pin!(P3_31, ADC1, Mux0, AdcPin);
+impl_pin!(P3_30, ADC1, Mux0, AdcPin);
+impl_pin!(P3_29, ADC1, Mux0, AdcPin);
+
+impl_pin!(P2_4, ADC2, Mux0, AdcPin);
+impl_pin!(P2_10, ADC2, Mux0, AdcPin);
+impl_pin!(P4_4, ADC2, Mux0, AdcPin);
+impl_pin!(P2_24, ADC2, Mux0, AdcPin);
+impl_pin!(P2_16, ADC2, Mux0, AdcPin);
+impl_pin!(P2_12, ADC2, Mux0, AdcPin);
+impl_pin!(P2_20, ADC2, Mux0, AdcPin);
+impl_pin!(P2_7, ADC2, Mux0, AdcPin);
+impl_pin!(P0_2, ADC2, Mux0, AdcPin);
+impl_pin!(P0_4, ADC2, Mux0, AdcPin);
+impl_pin!(P0_5, ADC2, Mux0, AdcPin);
+impl_pin!(P0_6, ADC2, Mux0, AdcPin);
+impl_pin!(P0_7, ADC2, Mux0, AdcPin);
+impl_pin!(P0_12, ADC2, Mux0, AdcPin);
+impl_pin!(P0_13, ADC2, Mux0, AdcPin);
+impl_pin!(P0_14, ADC2, Mux0, AdcPin);
+impl_pin!(P0_15, ADC2, Mux0, AdcPin);
+impl_pin!(P4_0, ADC2, Mux0, AdcPin);
+impl_pin!(P4_1, ADC2, Mux0, AdcPin);
+impl_pin!(P4_2, ADC2, Mux0, AdcPin);
+impl_pin!(P4_3, ADC2, Mux0, AdcPin);
+//impl_pin!(P4_4, ADC2, Mux0, AdcPin); // Conflit with ADC2_A3 and ADC2_A20 using the same pin
+impl_pin!(P4_5, ADC2, Mux0, AdcPin);
+impl_pin!(P4_6, ADC2, Mux0, AdcPin);
+impl_pin!(P4_7, ADC2, Mux0, AdcPin);
+
+impl_pin!(P2_5, ADC3, Mux0, AdcPin);
+impl_pin!(P2_11, ADC3, Mux0, AdcPin);
+impl_pin!(P2_23, ADC3, Mux0, AdcPin);
+impl_pin!(P2_25, ADC3, Mux0, AdcPin);
+impl_pin!(P2_17, ADC3, Mux0, AdcPin);
+impl_pin!(P2_13, ADC3, Mux0, AdcPin);
+impl_pin!(P2_21, ADC3, Mux0, AdcPin);
+impl_pin!(P2_7, ADC3, Mux0, AdcPin);
+impl_pin!(P3_2, ADC3, Mux0, AdcPin);
+impl_pin!(P3_3, ADC3, Mux0, AdcPin);
+impl_pin!(P3_4, ADC3, Mux0, AdcPin);
+impl_pin!(P3_5, ADC3, Mux0, AdcPin);
+impl_pin!(P3_6, ADC3, Mux0, AdcPin);
+impl_pin!(P3_7, ADC3, Mux0, AdcPin);
+impl_pin!(P3_12, ADC3, Mux0, AdcPin);
+impl_pin!(P3_13, ADC3, Mux0, AdcPin);
+impl_pin!(P3_14, ADC3, Mux0, AdcPin);
+impl_pin!(P3_15, ADC3, Mux0, AdcPin);
+impl_pin!(P3_20, ADC3, Mux0, AdcPin);
+impl_pin!(P3_21, ADC3, Mux0, AdcPin);
+impl_pin!(P3_22, ADC3, Mux0, AdcPin);
+impl_pin!(P3_23, ADC3, Mux0, AdcPin);
+impl_pin!(P3_24, ADC3, Mux0, AdcPin);
+impl_pin!(P3_25, ADC3, Mux0, AdcPin);
diff --git a/embassy-mcxa/src/clkout.rs b/embassy-mcxa/src/clkout.rs
new file mode 100644
index 000000000..5b21f24b0
--- /dev/null
+++ b/embassy-mcxa/src/clkout.rs
@@ -0,0 +1,169 @@
+//! CLKOUT pseudo-peripheral
+//!
+//! CLKOUT is a part of the clock generation subsystem, and can be used
+//! either to generate arbitrary waveforms, or to debug the state of
+//! internal oscillators.
+
+use core::marker::PhantomData;
+
+use embassy_hal_internal::Peri;
+
+pub use crate::clocks::periph_helpers::Div4;
+use crate::clocks::{ClockError, PoweredClock, with_clocks};
+use crate::pac::mrcc0::mrcc_clkout_clksel::Mux;
+use crate::peripherals::CLKOUT;
+
+/// A peripheral representing the CLKOUT pseudo-peripheral
+pub struct ClockOut<'a> {
+    _p: PhantomData<&'a mut CLKOUT>,
+    freq: u32,
+}
+
+/// Selected clock source to output
+pub enum ClockOutSel {
+    /// 12MHz Internal Oscillator
+    Fro12M,
+    /// FRO180M Internal Oscillator, via divisor
+    FroHfDiv,
+    /// External Oscillator
+    ClkIn,
+    /// 16KHz oscillator
+    Clk16K,
+    /// Output of PLL1
+    Pll1Clk,
+    /// Main System CPU clock, divided by 6
+    SlowClk,
+}
+
+/// Configuration for the ClockOut
+pub struct Config {
+    /// Selected Source Clock
+    pub sel: ClockOutSel,
+    /// Selected division level
+    pub div: Div4,
+    /// Selected power level
+    pub level: PoweredClock,
+}
+
+impl<'a> ClockOut<'a> {
+    /// Create a new ClockOut pin. On success, the clock signal will begin immediately
+    /// on the given pin.
+    pub fn new(
+        _peri: Peri<'a, CLKOUT>,
+        pin: Peri<'a, impl sealed::ClockOutPin>,
+        cfg: Config,
+    ) -> Result<Self, ClockError> {
+        // There's no MRCC enable bit, so we check the validity of the clocks here
+        //
+        // TODO: Should we check that the frequency is suitably low?
+        let (freq, mux) = check_sel(cfg.sel, cfg.level)?;
+
+        // All good! Apply requested config, starting with the pin.
+        pin.mux();
+
+        setup_clkout(mux, cfg.div);
+
+        Ok(Self {
+            _p: PhantomData,
+            freq: freq / cfg.div.into_divisor(),
+        })
+    }
+
+    /// Frequency of the clkout pin
+    #[inline]
+    pub fn frequency(&self) -> u32 {
+        self.freq
+    }
+}
+
+impl Drop for ClockOut<'_> {
+    fn drop(&mut self) {
+        disable_clkout();
+    }
+}
+
+/// Check whether the given clock selection is valid
+fn check_sel(sel: ClockOutSel, level: PoweredClock) -> Result<(u32, Mux), ClockError> {
+    let res = with_clocks(|c| {
+        Ok(match sel {
+            ClockOutSel::Fro12M => (c.ensure_fro_hf_active(&level)?, Mux::Clkroot12m),
+            ClockOutSel::FroHfDiv => (c.ensure_fro_hf_div_active(&level)?, Mux::ClkrootFircDiv),
+            ClockOutSel::ClkIn => (c.ensure_clk_in_active(&level)?, Mux::ClkrootSosc),
+            ClockOutSel::Clk16K => (c.ensure_clk_16k_vdd_core_active(&level)?, Mux::Clkroot16k),
+            ClockOutSel::Pll1Clk => (c.ensure_pll1_clk_active(&level)?, Mux::ClkrootSpll),
+            ClockOutSel::SlowClk => (c.ensure_slow_clk_active(&level)?, Mux::ClkrootSlow),
+        })
+    });
+    let Some(res) = res else {
+        return Err(ClockError::NeverInitialized);
+    };
+    res
+}
+
+/// Set up the clkout pin using the given mux and div settings
+fn setup_clkout(mux: Mux, div: Div4) {
+    let mrcc = unsafe { crate::pac::Mrcc0::steal() };
+
+    mrcc.mrcc_clkout_clksel().write(|w| w.mux().variant(mux));
+
+    // Set up clkdiv
+    mrcc.mrcc_clkout_clkdiv().write(|w| {
+        w.halt().set_bit();
+        w.reset().set_bit();
+        unsafe { w.div().bits(div.into_bits()) };
+        w
+    });
+    mrcc.mrcc_clkout_clkdiv().write(|w| {
+        w.halt().clear_bit();
+        w.reset().clear_bit();
+        unsafe { w.div().bits(div.into_bits()) };
+        w
+    });
+
+    while mrcc.mrcc_clkout_clkdiv().read().unstab().bit_is_set() {}
+}
+
+/// Stop the clkout
+fn disable_clkout() {
+    // Stop the output by selecting the "none" clock
+    //
+    // TODO: restore the pin to hi-z or something?
+    let mrcc = unsafe { crate::pac::Mrcc0::steal() };
+    mrcc.mrcc_clkout_clkdiv().write(|w| {
+        w.reset().set_bit();
+        w.halt().set_bit();
+        unsafe {
+            w.div().bits(0);
+        }
+        w
+    });
+    mrcc.mrcc_clkout_clksel().write(|w| unsafe { w.bits(0b111) });
+}
+
+mod sealed {
+    use embassy_hal_internal::PeripheralType;
+
+    use crate::gpio::{Pull, SealedPin};
+
+    /// Sealed marker trait for clockout pins
+    pub trait ClockOutPin: PeripheralType {
+        /// Set the given pin to the correct muxing state
+        fn mux(&self);
+    }
+
+    macro_rules! impl_pin {
+        ($pin:ident, $func:ident) => {
+            impl ClockOutPin for crate::peripherals::$pin {
+                fn mux(&self) {
+                    self.set_function(crate::pac::port0::pcr0::Mux::$func);
+                    self.set_pull(Pull::Disabled);
+                }
+            }
+        };
+    }
+
+    impl_pin!(P0_6, Mux12);
+    impl_pin!(P3_6, Mux1);
+    impl_pin!(P3_8, Mux12);
+    impl_pin!(P4_2, Mux1);
+}
diff --git a/embassy-mcxa/src/clocks/config.rs b/embassy-mcxa/src/clocks/config.rs
new file mode 100644
index 000000000..0563b8917
--- /dev/null
+++ b/embassy-mcxa/src/clocks/config.rs
@@ -0,0 +1,204 @@
+//! Clock Configuration
+//!
+//! This module holds configuration types used for the system clocks. For
+//! configuration of individual peripherals, see [`super::periph_helpers`].
+
+use super::PoweredClock;
+
+/// This type represents a divider in the range 1..=256.
+///
+/// At a hardware level, this is an 8-bit register from 0..=255,
+/// which adds one.
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub struct Div8(pub(super) u8);
+
+impl Div8 {
+    /// Store a "raw" divisor value that will divide the source by
+    /// `(n + 1)`, e.g. `Div8::from_raw(0)` will divide the source
+    /// by 1, and `Div8::from_raw(255)` will divide the source by
+    /// 256.
+    pub const fn from_raw(n: u8) -> Self {
+        Self(n)
+    }
+
+    /// Divide by one, or no division
+    pub const fn no_div() -> Self {
+        Self(0)
+    }
+
+    /// Store a specific divisor value that will divide the source
+    /// by `n`. e.g. `Div8::from_divisor(1)` will divide the source
+    /// by 1, and `Div8::from_divisor(256)` will divide the source
+    /// by 256.
+    ///
+    /// Will return `None` if `n` is not in the range `1..=256`.
+    /// Consider [`Self::from_raw`] for an infallible version.
+    pub const fn from_divisor(n: u16) -> Option<Self> {
+        let Some(n) = n.checked_sub(1) else {
+            return None;
+        };
+        if n > (u8::MAX as u16) {
+            return None;
+        }
+        Some(Self(n as u8))
+    }
+
+    /// Convert into "raw" bits form
+    #[inline(always)]
+    pub const fn into_bits(self) -> u8 {
+        self.0
+    }
+
+    /// Convert into "divisor" form, as a u32 for convenient frequency math
+    #[inline(always)]
+    pub const fn into_divisor(self) -> u32 {
+        self.0 as u32 + 1
+    }
+}
+
+/// ```text
+///               ┌─────────────────────────────────────────────────────────┐
+///               │                                                         │
+///               │   ┌───────────┐  clk_out   ┌─────────┐                  │
+///    XTAL ──────┼──▷│ System    │───────────▷│         │       clk_in     │
+///               │   │  OSC      │ clkout_byp │   MUX   │──────────────────┼──────▷
+///   EXTAL ──────┼──▷│           │───────────▷│         │                  │
+///               │   └───────────┘            └─────────┘                  │
+///               │                                                         │
+///               │   ┌───────────┐ fro_hf_root  ┌────┐          fro_hf     │
+///               │   │ FRO180    ├───────┬─────▷│ CG │─────────────────────┼──────▷
+///               │   │           │       │      ├────┤         clk_45m     │
+///               │   │           │       └─────▷│ CG │─────────────────────┼──────▷
+///               │   └───────────┘              └────┘                     │
+///               │   ┌───────────┐ fro_12m_root  ┌────┐         fro_12m    │
+///               │   │ FRO12M    │────────┬─────▷│ CG │────────────────────┼──────▷
+///               │   │           │        │      ├────┤          clk_1m    │
+///               │   │           │        └─────▷│1/12│────────────────────┼──────▷
+///               │   └───────────┘               └────┘                    │
+///               │                                                         │
+///               │                  ┌──────────┐                           │
+///               │                  │000       │                           │
+///               │      clk_in      │          │                           │
+///               │  ───────────────▷│001       │                           │
+///               │      fro_12m     │          │                           │
+///               │  ───────────────▷│010       │                           │
+///               │    fro_hf_root   │          │                           │
+///               │  ───────────────▷│011       │              main_clk     │
+///               │                  │          │───────────────────────────┼──────▷
+/// clk_16k ──────┼─────────────────▷│100       │                           │
+///               │       none       │          │                           │
+///               │  ───────────────▷│101       │                           │
+///               │     pll1_clk     │          │                           │
+///               │  ───────────────▷│110       │                           │
+///               │       none       │          │                           │
+///               │  ───────────────▷│111       │                           │
+///               │                  └──────────┘                           │
+///               │                        ▲                                │
+///               │                        │                                │
+///               │                     SCG SCS                             │
+///               │ SCG-Lite                                                │
+///               └─────────────────────────────────────────────────────────┘
+///
+///
+///                      clk_in      ┌─────┐
+///                  ───────────────▷│00   │
+///                      clk_45m     │     │
+///                  ───────────────▷│01   │      ┌───────────┐   pll1_clk
+///                       none       │     │─────▷│   SPLL    │───────────────▷
+///                  ───────────────▷│10   │      └───────────┘
+///                      fro_12m     │     │
+///                  ───────────────▷│11   │
+///                                  └─────┘
+/// ```
+#[non_exhaustive]
+pub struct ClocksConfig {
+    /// FIRC, FRO180, 45/60/90/180M clock source
+    pub firc: Option<FircConfig>,
+    /// SIRC, FRO12M, clk_12m clock source
+    // NOTE: I don't think we *can* disable the SIRC?
+    pub sirc: SircConfig,
+    /// FRO16K clock source
+    pub fro16k: Option<Fro16KConfig>,
+}
+
+// FIRC/FRO180M
+
+/// ```text
+/// ┌───────────┐ fro_hf_root  ┌────┐   fro_hf
+/// │ FRO180M   ├───────┬─────▷│GATE│──────────▷
+/// │           │       │      ├────┤  clk_45m
+/// │           │       └─────▷│GATE│──────────▷
+/// └───────────┘              └────┘
+/// ```
+#[non_exhaustive]
+pub struct FircConfig {
+    /// Selected clock frequency
+    pub frequency: FircFreqSel,
+    /// Selected power state of the clock
+    pub power: PoweredClock,
+    /// Is the "fro_hf" gated clock enabled?
+    pub fro_hf_enabled: bool,
+    /// Is the "clk_45m" gated clock enabled?
+    pub clk_45m_enabled: bool,
+    /// Is the "fro_hf_div" clock enabled? Requires `fro_hf`!
+    pub fro_hf_div: Option<Div8>,
+}
+
+/// Selected FIRC frequency
+pub enum FircFreqSel {
+    /// 45MHz Output
+    Mhz45,
+    /// 60MHz Output
+    Mhz60,
+    /// 90MHz Output
+    Mhz90,
+    /// 180MHz Output
+    Mhz180,
+}
+
+// SIRC/FRO12M
+
+/// ```text
+/// ┌───────────┐ fro_12m_root  ┌────┐ fro_12m
+/// │ FRO12M    │────────┬─────▷│ CG │──────────▷
+/// │           │        │      ├────┤  clk_1m
+/// │           │        └─────▷│1/12│──────────▷
+/// └───────────┘               └────┘
+/// ```
+#[non_exhaustive]
+pub struct SircConfig {
+    pub power: PoweredClock,
+    // peripheral output, aka sirc_12mhz
+    pub fro_12m_enabled: bool,
+    /// Is the "fro_lf_div" clock enabled? Requires `fro_12m`!
+    pub fro_lf_div: Option<Div8>,
+}
+
+#[non_exhaustive]
+pub struct Fro16KConfig {
+    pub vsys_domain_active: bool,
+    pub vdd_core_domain_active: bool,
+}
+
+impl Default for ClocksConfig {
+    fn default() -> Self {
+        Self {
+            firc: Some(FircConfig {
+                frequency: FircFreqSel::Mhz45,
+                power: PoweredClock::NormalEnabledDeepSleepDisabled,
+                fro_hf_enabled: true,
+                clk_45m_enabled: true,
+                fro_hf_div: None,
+            }),
+            sirc: SircConfig {
+                power: PoweredClock::AlwaysEnabled,
+                fro_12m_enabled: true,
+                fro_lf_div: None,
+            },
+            fro16k: Some(Fro16KConfig {
+                vsys_domain_active: true,
+                vdd_core_domain_active: true,
+            }),
+        }
+    }
+}
diff --git a/embassy-mcxa/src/clocks/mod.rs b/embassy-mcxa/src/clocks/mod.rs
new file mode 100644
index 000000000..667d79536
--- /dev/null
+++ b/embassy-mcxa/src/clocks/mod.rs
@@ -0,0 +1,955 @@
+//! # Clock Module
+//!
+//! For the MCX-A, we separate clock and peripheral control into two main stages:
+//!
+//! 1. At startup, e.g. when `embassy_mcxa::init()` is called, we configure the
+//!    core system clocks, including external and internal oscillators. This
+//!    configuration is then largely static for the duration of the program.
+//! 2. When HAL drivers are created, e.g. `Lpuart::new()` is called, the driver
+//!    is responsible for two main things:
+//!     * Ensuring that any required "upstream" core system clocks necessary for
+//!       clocking the peripheral is active and configured to a reasonable value
+//!     * Enabling the clock gates for that peripheral, and resetting the peripheral
+//!
+//! From a user perspective, only step 1 is visible. Step 2 is automatically handled
+//! by HAL drivers, using interfaces defined in this module.
+//!
+//! It is also possible to *view* the state of the clock configuration after [`init()`]
+//! has been called, using the [`with_clocks()`] function, which provides a view of the
+//! [`Clocks`] structure.
+//!
+//! ## For HAL driver implementors
+//!
+//! The majority of peripherals in the MCXA chip are fed from either a "hard-coded" or
+//! configurable clock source, e.g. selecting the FROM12M or `clk_1m` as a source. This
+//! selection, as well as often any pre-scaler division from that source clock, is made
+//! through MRCC registers.
+//!
+//! Any peripheral that is controlled through the MRCC register can automatically implement
+//! the necessary APIs using the `impl_cc_gate!` macro in this module. You will also need
+//! to define the configuration surface and steps necessary to fully configure that peripheral
+//! from a clocks perspective by:
+//!
+//! 1. Defining a configuration type in the [`periph_helpers`] module that contains any selects
+//!    or divisions available to the HAL driver
+//! 2. Implementing the [`periph_helpers::SPConfHelper`] trait, which should check that the
+//!    necessary input clocks are reasonable
+
+use core::cell::RefCell;
+
+use config::{ClocksConfig, FircConfig, FircFreqSel, Fro16KConfig, SircConfig};
+use mcxa_pac::scg0::firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten};
+use mcxa_pac::scg0::sirccsr::{SircClkPeriphEn, Sircsten};
+use periph_helpers::SPConfHelper;
+
+use crate::pac;
+pub mod config;
+pub mod periph_helpers;
+
+//
+// Statics/Consts
+//
+
+/// The state of system core clocks.
+///
+/// Initialized by [`init()`], and then unchanged for the remainder of the program.
+static CLOCKS: critical_section::Mutex<RefCell<Option<Clocks>>> = critical_section::Mutex::new(RefCell::new(None));
+
+//
+// Free functions
+//
+
+/// Initialize the core system clocks with the given [`ClocksConfig`].
+///
+/// This function should be called EXACTLY once at start-up, usually via a
+/// call to [`embassy_mcxa::init()`](crate::init()). Subsequent calls will
+/// return an error.
+pub fn init(settings: ClocksConfig) -> Result<(), ClockError> {
+    critical_section::with(|cs| {
+        if CLOCKS.borrow_ref(cs).is_some() {
+            Err(ClockError::AlreadyInitialized)
+        } else {
+            Ok(())
+        }
+    })?;
+
+    let mut clocks = Clocks::default();
+    let mut operator = ClockOperator {
+        clocks: &mut clocks,
+        config: &settings,
+
+        _mrcc0: unsafe { pac::Mrcc0::steal() },
+        scg0: unsafe { pac::Scg0::steal() },
+        syscon: unsafe { pac::Syscon::steal() },
+        vbat0: unsafe { pac::Vbat0::steal() },
+    };
+
+    operator.configure_firc_clocks()?;
+    operator.configure_sirc_clocks()?;
+    operator.configure_fro16k_clocks()?;
+
+    // For now, just use FIRC as the main/cpu clock, which should already be
+    // the case on reset
+    assert!(operator.scg0.rccr().read().scs().is_firc());
+    let input = operator.clocks.fro_hf_root.clone().unwrap();
+    operator.clocks.main_clk = Some(input.clone());
+    // We can also assume cpu/system clk == fro_hf because div is /1.
+    assert_eq!(operator.syscon.ahbclkdiv().read().div().bits(), 0);
+    operator.clocks.cpu_system_clk = Some(input);
+
+    critical_section::with(|cs| {
+        let mut clks = CLOCKS.borrow_ref_mut(cs);
+        assert!(clks.is_none(), "Clock setup race!");
+        *clks = Some(clocks);
+    });
+
+    Ok(())
+}
+
+/// Obtain the full clocks structure, calling the given closure in a critical section.
+///
+/// The given closure will be called with read-only access to the state of the system
+/// clocks. This can be used to query and return the state of a given clock.
+///
+/// As the caller's closure will be called in a critical section, care must be taken
+/// not to block or cause any other undue delays while accessing.
+///
+/// Calls to this function will not succeed until after a successful call to `init()`,
+/// and will always return None.
+pub fn with_clocks<R: 'static, F: FnOnce(&Clocks) -> R>(f: F) -> Option<R> {
+    critical_section::with(|cs| {
+        let c = CLOCKS.borrow_ref(cs);
+        let c = c.as_ref()?;
+        Some(f(c))
+    })
+}
+
+//
+// Structs/Enums
+//
+
+/// The `Clocks` structure contains the initialized state of the core system clocks
+///
+/// These values are configured by providing [`config::ClocksConfig`] to the [`init()`] function
+/// at boot time.
+#[derive(Default, Debug, Clone)]
+#[non_exhaustive]
+pub struct Clocks {
+    /// The `clk_in` is a clock provided by an external oscillator
+    pub clk_in: Option<Clock>,
+
+    // FRO180M stuff
+    //
+    /// `fro_hf_root` is the direct output of the `FRO180M` internal oscillator
+    ///
+    /// It is used to feed downstream clocks, such as `fro_hf`, `clk_45m`,
+    /// and `fro_hf_div`.
+    pub fro_hf_root: Option<Clock>,
+
+    /// `fro_hf` is the same frequency as `fro_hf_root`, but behind a gate.
+    pub fro_hf: Option<Clock>,
+
+    /// `clk_45` is a 45MHz clock, sourced from `fro_hf`.
+    pub clk_45m: Option<Clock>,
+
+    /// `fro_hf_div` is a configurable frequency clock, sourced from `fro_hf`.
+    pub fro_hf_div: Option<Clock>,
+
+    //
+    // End FRO180M
+
+    // FRO12M stuff
+    //
+    /// `fro_12m_root` is the direct output of the `FRO12M` internal oscillator
+    ///
+    /// It is used to feed downstream clocks, such as `fro_12m`, `clk_1m`,
+    /// `and `fro_lf_div`.
+    pub fro_12m_root: Option<Clock>,
+
+    /// `fro_12m` is the same frequency as `fro_12m_root`, but behind a gate.
+    pub fro_12m: Option<Clock>,
+
+    /// `clk_1m` is a 1MHz clock, sourced from `fro_12m`
+    pub clk_1m: Option<Clock>,
+
+    /// `fro_lf_div` is a configurable frequency clock, sourced from `fro_12m`
+    pub fro_lf_div: Option<Clock>,
+    //
+    // End FRO12M stuff
+    /// `clk_16k_vsys` is one of two outputs of the `FRO16K` internal oscillator.
+    ///
+    /// Also referred to as `clk_16k[0]` in the datasheet, it feeds peripherals in
+    /// the system domain, such as the CMP and RTC.
+    pub clk_16k_vsys: Option<Clock>,
+
+    /// `clk_16k_vdd_core` is one of two outputs of the `FRO16K` internal oscillator.
+    ///
+    /// Also referred to as `clk_16k[1]` in the datasheet, it feeds peripherals in
+    /// the VDD Core domain, such as the OSTimer or LPUarts.
+    pub clk_16k_vdd_core: Option<Clock>,
+
+    /// `main_clk` is the main clock used by the CPU, AHB, APB, IPS bus, and some
+    /// peripherals.
+    pub main_clk: Option<Clock>,
+
+    /// `CPU_CLK` or `SYSTEM_CLK` is the output of `main_clk`, run through the `AHBCLKDIV`
+    pub cpu_system_clk: Option<Clock>,
+
+    /// `pll1_clk` is the output of the main system PLL, `pll1`.
+    pub pll1_clk: Option<Clock>,
+}
+
+/// `ClockError` is the main error returned when configuring or checking clock state
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum ClockError {
+    /// The system clocks were never initialized by calling [`init()`]
+    NeverInitialized,
+    /// The [`init()`] function was called more than once
+    AlreadyInitialized,
+    /// The requested configuration was not possible to fulfill, as the system clocks
+    /// were not configured in a compatible way
+    BadConfig { clock: &'static str, reason: &'static str },
+    /// The requested configuration was not possible to fulfill, as the required system
+    /// clocks have not yet been implemented.
+    NotImplemented { clock: &'static str },
+    /// The requested peripheral could not be configured, as the steps necessary to
+    /// enable it have not yet been implemented.
+    UnimplementedConfig,
+}
+
+/// Information regarding a system clock
+#[derive(Debug, Clone)]
+pub struct Clock {
+    /// The frequency, in Hz, of the given clock
+    pub frequency: u32,
+    /// The power state of the clock, e.g. whether it is active in deep sleep mode
+    /// or not.
+    pub power: PoweredClock,
+}
+
+/// The power state of a given clock.
+///
+/// On the MCX-A, when Deep-Sleep is entered, any clock not configured for Deep Sleep
+/// mode will be stopped. This means that any downstream usage, e.g. by peripherals,
+/// will also stop.
+///
+/// In the future, we will provide an API for entering Deep Sleep, and if there are
+/// any peripherals that are NOT using an `AlwaysEnabled` clock active, entry into
+/// Deep Sleep will be prevented, in order to avoid misbehaving peripherals.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum PoweredClock {
+    /// The given clock will NOT continue running in Deep Sleep mode
+    NormalEnabledDeepSleepDisabled,
+    /// The given clock WILL continue running in Deep Sleep mode
+    AlwaysEnabled,
+}
+
+/// The ClockOperator is a private helper type that contains the methods used
+/// during system clock initialization.
+///
+/// # SAFETY
+///
+/// Concurrent access to clock-relevant peripheral registers, such as `MRCC`, `SCG`,
+/// `SYSCON`, and `VBAT` should not be allowed for the duration of the [`init()`] function.
+struct ClockOperator<'a> {
+    /// A mutable reference to the current state of system clocks
+    clocks: &'a mut Clocks,
+    /// A reference to the requested configuration provided by the caller of [`init()`]
+    config: &'a ClocksConfig,
+
+    // We hold on to stolen peripherals
+    _mrcc0: pac::Mrcc0,
+    scg0: pac::Scg0,
+    syscon: pac::Syscon,
+    vbat0: pac::Vbat0,
+}
+
+/// Trait describing an AHB clock gate that can be toggled through MRCC.
+pub trait Gate {
+    type MrccPeriphConfig: SPConfHelper;
+
+    /// Enable the clock gate.
+    ///
+    /// # SAFETY
+    ///
+    /// The current peripheral must be disabled prior to calling this method
+    unsafe fn enable_clock();
+
+    /// Disable the clock gate.
+    ///
+    /// # SAFETY
+    ///
+    /// There must be no active user of this peripheral when calling this method
+    unsafe fn disable_clock();
+
+    /// Drive the peripheral into reset.
+    ///
+    /// # SAFETY
+    ///
+    /// There must be no active user of this peripheral when calling this method
+    unsafe fn assert_reset();
+
+    /// Drive the peripheral out of reset.
+    ///
+    /// # SAFETY
+    ///
+    /// There must be no active user of this peripheral when calling this method
+    unsafe fn release_reset();
+
+    /// Return whether the clock gate for this peripheral is currently enabled.
+    fn is_clock_enabled() -> bool;
+
+    /// Return whether the peripheral is currently held in reset.
+    fn is_reset_released() -> bool;
+}
+
+/// This is the primary helper method HAL drivers are expected to call when creating
+/// an instance of the peripheral.
+///
+/// This method:
+///
+/// 1. Enables the MRCC clock gate for this peripheral
+/// 2. Calls the `G::MrccPeriphConfig::post_enable_config()` method, returning an error
+///    and re-disabling the peripheral if this fails.
+/// 3. Pulses the MRCC reset line, to reset the peripheral to the default state
+/// 4. Returns the frequency, in Hz that is fed into the peripheral, taking into account
+///    the selected upstream clock, as well as any division specified by `cfg`.
+///
+/// NOTE: if a clock is disabled, sourced from an "ambient" clock source, this method
+/// may return `Ok(0)`. In the future, this might be updated to return the correct
+/// "ambient" clock, e.g. the AHB/APB frequency.
+///
+/// # SAFETY
+///
+/// This peripheral must not yet be in use prior to calling `enable_and_reset`.
+#[inline]
+pub unsafe fn enable_and_reset<G: Gate>(cfg: &G::MrccPeriphConfig) -> Result<u32, ClockError> {
+    let freq = enable::<G>(cfg).inspect_err(|_| disable::<G>())?;
+    pulse_reset::<G>();
+    Ok(freq)
+}
+
+/// Enable the clock gate for the given peripheral.
+///
+/// Prefer [`enable_and_reset`] unless you are specifically avoiding a pulse of the reset, or need
+/// to control the duration of the pulse more directly.
+///
+/// # SAFETY
+///
+/// This peripheral must not yet be in use prior to calling `enable`.
+#[inline]
+pub unsafe fn enable<G: Gate>(cfg: &G::MrccPeriphConfig) -> Result<u32, ClockError> {
+    G::enable_clock();
+    while !G::is_clock_enabled() {}
+    core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags));
+
+    let freq = critical_section::with(|cs| {
+        let clocks = CLOCKS.borrow_ref(cs);
+        let clocks = clocks.as_ref().ok_or(ClockError::NeverInitialized)?;
+        cfg.post_enable_config(clocks)
+    });
+
+    freq.inspect_err(|_e| {
+        G::disable_clock();
+    })
+}
+
+/// Disable the clock gate for the given peripheral.
+///
+/// # SAFETY
+///
+/// This peripheral must no longer be in use prior to calling `enable`.
+#[allow(dead_code)]
+#[inline]
+pub unsafe fn disable<G: Gate>() {
+    G::disable_clock();
+}
+
+/// Check whether a gate is currently enabled.
+#[allow(dead_code)]
+#[inline]
+pub fn is_clock_enabled<G: Gate>() -> bool {
+    G::is_clock_enabled()
+}
+
+/// Release a reset line for the given peripheral set.
+///
+/// Prefer [`enable_and_reset`].
+///
+/// # SAFETY
+///
+/// This peripheral must not yet be in use prior to calling `release_reset`.
+#[inline]
+pub unsafe fn release_reset<G: Gate>() {
+    G::release_reset();
+}
+
+/// Assert a reset line for the given peripheral set.
+///
+/// Prefer [`enable_and_reset`].
+///
+/// # SAFETY
+///
+/// This peripheral must not yet be in use prior to calling `assert_reset`.
+#[inline]
+pub unsafe fn assert_reset<G: Gate>() {
+    G::assert_reset();
+}
+
+/// Check whether the peripheral is held in reset.
+///
+/// # Safety
+///
+/// Must be called with a valid peripheral gate type.
+#[inline]
+pub unsafe fn is_reset_released<G: Gate>() -> bool {
+    G::is_reset_released()
+}
+
+/// Pulse a reset line (assert then release) with a short delay.
+///
+/// Prefer [`enable_and_reset`].
+///
+/// # SAFETY
+///
+/// This peripheral must not yet be in use prior to calling `release_reset`.
+#[inline]
+pub unsafe fn pulse_reset<G: Gate>() {
+    G::assert_reset();
+    cortex_m::asm::nop();
+    cortex_m::asm::nop();
+    G::release_reset();
+}
+
+//
+// `impl`s for structs/enums
+//
+
+/// The [`Clocks`] type's methods generally take the form of "ensure X clock is active".
+///
+/// These methods are intended to be used by HAL peripheral implementors to ensure that their
+/// selected clocks are active at a suitable level at time of construction. These methods
+/// return the frequency of the requested clock, in Hertz, or a [`ClockError`].
+impl Clocks {
+    /// Ensure the `fro_lf_div` clock is active and valid at the given power state.
+    pub fn ensure_fro_lf_div_active(&self, at_level: &PoweredClock) -> Result<u32, ClockError> {
+        let Some(clk) = self.fro_lf_div.as_ref() else {
+            return Err(ClockError::BadConfig {
+                clock: "fro_lf_div",
+                reason: "required but not active",
+            });
+        };
+        if !clk.power.meets_requirement_of(at_level) {
+            return Err(ClockError::BadConfig {
+                clock: "fro_lf_div",
+                reason: "not low power active",
+            });
+        }
+        Ok(clk.frequency)
+    }
+
+    /// Ensure the `fro_hf` clock is active and valid at the given power state.
+    pub fn ensure_fro_hf_active(&self, at_level: &PoweredClock) -> Result<u32, ClockError> {
+        let Some(clk) = self.fro_hf.as_ref() else {
+            return Err(ClockError::BadConfig {
+                clock: "fro_hf",
+                reason: "required but not active",
+            });
+        };
+        if !clk.power.meets_requirement_of(at_level) {
+            return Err(ClockError::BadConfig {
+                clock: "fro_hf",
+                reason: "not low power active",
+            });
+        }
+        Ok(clk.frequency)
+    }
+
+    /// Ensure the `fro_hf_div` clock is active and valid at the given power state.
+    pub fn ensure_fro_hf_div_active(&self, at_level: &PoweredClock) -> Result<u32, ClockError> {
+        let Some(clk) = self.fro_hf_div.as_ref() else {
+            return Err(ClockError::BadConfig {
+                clock: "fro_hf_div",
+                reason: "required but not active",
+            });
+        };
+        if !clk.power.meets_requirement_of(at_level) {
+            return Err(ClockError::BadConfig {
+                clock: "fro_hf_div",
+                reason: "not low power active",
+            });
+        }
+        Ok(clk.frequency)
+    }
+
+    /// Ensure the `clk_in` clock is active and valid at the given power state.
+    pub fn ensure_clk_in_active(&self, _at_level: &PoweredClock) -> Result<u32, ClockError> {
+        Err(ClockError::NotImplemented { clock: "clk_in" })
+    }
+
+    /// Ensure the `clk_16k_vsys` clock is active and valid at the given power state.
+    pub fn ensure_clk_16k_vsys_active(&self, _at_level: &PoweredClock) -> Result<u32, ClockError> {
+        // NOTE: clk_16k is always active in low power mode
+        Ok(self
+            .clk_16k_vsys
+            .as_ref()
+            .ok_or(ClockError::BadConfig {
+                clock: "clk_16k_vsys",
+                reason: "required but not active",
+            })?
+            .frequency)
+    }
+
+    /// Ensure the `clk_16k_vdd_core` clock is active and valid at the given power state.
+    pub fn ensure_clk_16k_vdd_core_active(&self, _at_level: &PoweredClock) -> Result<u32, ClockError> {
+        // NOTE: clk_16k is always active in low power mode
+        Ok(self
+            .clk_16k_vdd_core
+            .as_ref()
+            .ok_or(ClockError::BadConfig {
+                clock: "clk_16k_vdd_core",
+                reason: "required but not active",
+            })?
+            .frequency)
+    }
+
+    /// Ensure the `clk_1m` clock is active and valid at the given power state.
+    pub fn ensure_clk_1m_active(&self, at_level: &PoweredClock) -> Result<u32, ClockError> {
+        let Some(clk) = self.clk_1m.as_ref() else {
+            return Err(ClockError::BadConfig {
+                clock: "clk_1m",
+                reason: "required but not active",
+            });
+        };
+        if !clk.power.meets_requirement_of(at_level) {
+            return Err(ClockError::BadConfig {
+                clock: "clk_1m",
+                reason: "not low power active",
+            });
+        }
+        Ok(clk.frequency)
+    }
+
+    /// Ensure the `pll1_clk` clock is active and valid at the given power state.
+    pub fn ensure_pll1_clk_active(&self, _at_level: &PoweredClock) -> Result<u32, ClockError> {
+        Err(ClockError::NotImplemented { clock: "pll1_clk" })
+    }
+
+    /// Ensure the `pll1_clk_div` clock is active and valid at the given power state.
+    pub fn ensure_pll1_clk_div_active(&self, _at_level: &PoweredClock) -> Result<u32, ClockError> {
+        Err(ClockError::NotImplemented { clock: "pll1_clk_div" })
+    }
+
+    /// Ensure the `CPU_CLK` or `SYSTEM_CLK` is active
+    pub fn ensure_cpu_system_clk_active(&self, at_level: &PoweredClock) -> Result<u32, ClockError> {
+        let Some(clk) = self.cpu_system_clk.as_ref() else {
+            return Err(ClockError::BadConfig {
+                clock: "cpu_system_clk",
+                reason: "required but not active",
+            });
+        };
+        // Can the main_clk ever be active in deep sleep? I think it is gated?
+        match at_level {
+            PoweredClock::NormalEnabledDeepSleepDisabled => {}
+            PoweredClock::AlwaysEnabled => {
+                return Err(ClockError::BadConfig {
+                    clock: "main_clk",
+                    reason: "not low power active",
+                });
+            }
+        }
+
+        Ok(clk.frequency)
+    }
+
+    pub fn ensure_slow_clk_active(&self, at_level: &PoweredClock) -> Result<u32, ClockError> {
+        let freq = self.ensure_cpu_system_clk_active(at_level)?;
+
+        Ok(freq / 6)
+    }
+}
+
+impl PoweredClock {
+    /// Does THIS clock meet the power requirements of the OTHER clock?
+    pub fn meets_requirement_of(&self, other: &Self) -> bool {
+        match (self, other) {
+            (PoweredClock::NormalEnabledDeepSleepDisabled, PoweredClock::AlwaysEnabled) => false,
+            (PoweredClock::NormalEnabledDeepSleepDisabled, PoweredClock::NormalEnabledDeepSleepDisabled) => true,
+            (PoweredClock::AlwaysEnabled, PoweredClock::NormalEnabledDeepSleepDisabled) => true,
+            (PoweredClock::AlwaysEnabled, PoweredClock::AlwaysEnabled) => true,
+        }
+    }
+}
+
+impl ClockOperator<'_> {
+    /// Configure the FIRC/FRO180M clock family
+    ///
+    /// NOTE: Currently we require this to be a fairly hardcoded value, as this clock is used
+    /// as the main clock used for the CPU, AHB, APB, etc.
+    fn configure_firc_clocks(&mut self) -> Result<(), ClockError> {
+        const HARDCODED_ERR: Result<(), ClockError> = Err(ClockError::BadConfig {
+            clock: "firc",
+            reason: "For now, FIRC must be enabled and in default state!",
+        });
+
+        // Did the user give us a FIRC config?
+        let Some(firc) = self.config.firc.as_ref() else {
+            return HARDCODED_ERR;
+        };
+        // Is the FIRC set to 45MHz (should be reset default)
+        if !matches!(firc.frequency, FircFreqSel::Mhz45) {
+            return HARDCODED_ERR;
+        }
+        let base_freq = 45_000_000;
+
+        // Now, check if the FIRC as expected for our hardcoded value
+        let mut firc_ok = true;
+
+        // Is the hardware currently set to the default 45MHz?
+        //
+        // NOTE: the SVD currently has the wrong(?) values for these:
+        // 45 -> 48
+        // 60 -> 64
+        // 90 -> 96
+        // 180 -> 192
+        // Probably correct-ish, but for a different trim value?
+        firc_ok &= self.scg0.firccfg().read().freq_sel().is_firc_48mhz_192s();
+
+        // Check some values in the CSR
+        let csr = self.scg0.firccsr().read();
+        // Is it enabled?
+        firc_ok &= csr.fircen().is_enabled();
+        // Is it accurate?
+        firc_ok &= csr.fircacc().is_enabled_and_valid();
+        // Is there no error?
+        firc_ok &= csr.fircerr().is_error_not_detected();
+        // Is the FIRC the system clock?
+        firc_ok &= csr.fircsel().is_firc();
+        // Is it valid?
+        firc_ok &= csr.fircvld().is_enabled_and_valid();
+
+        // Are we happy with the current (hardcoded) state?
+        if !firc_ok {
+            return HARDCODED_ERR;
+        }
+
+        // Note that the fro_hf_root is active
+        self.clocks.fro_hf_root = Some(Clock {
+            frequency: base_freq,
+            power: firc.power,
+        });
+
+        // Okay! Now we're past that, let's enable all the downstream clocks.
+        let FircConfig {
+            frequency: _,
+            power,
+            fro_hf_enabled,
+            clk_45m_enabled,
+            fro_hf_div,
+        } = firc;
+
+        // When is the FRO enabled?
+        let pow_set = match power {
+            PoweredClock::NormalEnabledDeepSleepDisabled => Fircsten::DisabledInStopModes,
+            PoweredClock::AlwaysEnabled => Fircsten::EnabledInStopModes,
+        };
+
+        // Do we enable the `fro_hf` output?
+        let fro_hf_set = if *fro_hf_enabled {
+            self.clocks.fro_hf = Some(Clock {
+                frequency: base_freq,
+                power: *power,
+            });
+            FircFclkPeriphEn::Enabled
+        } else {
+            FircFclkPeriphEn::Disabled
+        };
+
+        // Do we enable the `clk_45m` output?
+        let clk_45m_set = if *clk_45m_enabled {
+            self.clocks.clk_45m = Some(Clock {
+                frequency: 45_000_000,
+                power: *power,
+            });
+            FircSclkPeriphEn::Enabled
+        } else {
+            FircSclkPeriphEn::Disabled
+        };
+
+        self.scg0.firccsr().modify(|_r, w| {
+            w.fircsten().variant(pow_set);
+            w.firc_fclk_periph_en().variant(fro_hf_set);
+            w.firc_sclk_periph_en().variant(clk_45m_set);
+            w
+        });
+
+        // Do we enable the `fro_hf_div` output?
+        if let Some(d) = fro_hf_div.as_ref() {
+            // We need `fro_hf` to be enabled
+            if !*fro_hf_enabled {
+                return Err(ClockError::BadConfig {
+                    clock: "fro_hf_div",
+                    reason: "fro_hf not enabled",
+                });
+            }
+
+            // Halt and reset the div; then set our desired div.
+            self.syscon.frohfdiv().write(|w| {
+                w.halt().halt();
+                w.reset().asserted();
+                unsafe { w.div().bits(d.into_bits()) };
+                w
+            });
+            // Then unhalt it, and reset it
+            self.syscon.frohfdiv().write(|w| {
+                w.halt().run();
+                w.reset().released();
+                w
+            });
+
+            // Wait for clock to stabilize
+            while self.syscon.frohfdiv().read().unstab().is_ongoing() {}
+
+            // Store off the clock info
+            self.clocks.fro_hf_div = Some(Clock {
+                frequency: base_freq / d.into_divisor(),
+                power: *power,
+            });
+        }
+
+        Ok(())
+    }
+
+    /// Configure the SIRC/FRO12M clock family
+    fn configure_sirc_clocks(&mut self) -> Result<(), ClockError> {
+        let SircConfig {
+            power,
+            fro_12m_enabled,
+            fro_lf_div,
+        } = &self.config.sirc;
+        let base_freq = 12_000_000;
+
+        // Allow writes
+        self.scg0.sirccsr().modify(|_r, w| w.lk().write_enabled());
+        self.clocks.fro_12m_root = Some(Clock {
+            frequency: base_freq,
+            power: *power,
+        });
+
+        let deep = match power {
+            PoweredClock::NormalEnabledDeepSleepDisabled => Sircsten::Disabled,
+            PoweredClock::AlwaysEnabled => Sircsten::Enabled,
+        };
+        let pclk = if *fro_12m_enabled {
+            self.clocks.fro_12m = Some(Clock {
+                frequency: base_freq,
+                power: *power,
+            });
+            self.clocks.clk_1m = Some(Clock {
+                frequency: base_freq / 12,
+                power: *power,
+            });
+            SircClkPeriphEn::Enabled
+        } else {
+            SircClkPeriphEn::Disabled
+        };
+
+        // Set sleep/peripheral usage
+        self.scg0.sirccsr().modify(|_r, w| {
+            w.sircsten().variant(deep);
+            w.sirc_clk_periph_en().variant(pclk);
+            w
+        });
+
+        while self.scg0.sirccsr().read().sircvld().is_disabled_or_not_valid() {}
+        if self.scg0.sirccsr().read().sircerr().is_error_detected() {
+            return Err(ClockError::BadConfig {
+                clock: "sirc",
+                reason: "error set",
+            });
+        }
+
+        // reset lock
+        self.scg0.sirccsr().modify(|_r, w| w.lk().write_disabled());
+
+        // Do we enable the `fro_lf_div` output?
+        if let Some(d) = fro_lf_div.as_ref() {
+            // We need `fro_lf` to be enabled
+            if !*fro_12m_enabled {
+                return Err(ClockError::BadConfig {
+                    clock: "fro_lf_div",
+                    reason: "fro_12m not enabled",
+                });
+            }
+
+            // Halt and reset the div; then set our desired div.
+            self.syscon.frolfdiv().write(|w| {
+                w.halt().halt();
+                w.reset().asserted();
+                unsafe { w.div().bits(d.into_bits()) };
+                w
+            });
+            // Then unhalt it, and reset it
+            self.syscon.frolfdiv().modify(|_r, w| {
+                w.halt().run();
+                w.reset().released();
+                w
+            });
+
+            // Wait for clock to stabilize
+            while self.syscon.frolfdiv().read().unstab().is_ongoing() {}
+
+            // Store off the clock info
+            self.clocks.fro_lf_div = Some(Clock {
+                frequency: base_freq / d.into_divisor(),
+                power: *power,
+            });
+        }
+
+        Ok(())
+    }
+
+    /// Configure the FRO16K/clk_16k clock family
+    fn configure_fro16k_clocks(&mut self) -> Result<(), ClockError> {
+        let Some(fro16k) = self.config.fro16k.as_ref() else {
+            return Ok(());
+        };
+        // Enable FRO16K oscillator
+        self.vbat0.froctla().modify(|_, w| w.fro_en().set_bit());
+
+        // Lock the control register
+        self.vbat0.frolcka().modify(|_, w| w.lock().set_bit());
+
+        let Fro16KConfig {
+            vsys_domain_active,
+            vdd_core_domain_active,
+        } = fro16k;
+
+        // Enable clock outputs to both VSYS and VDD_CORE domains
+        // Bit 0: clk_16k0 to VSYS domain
+        // Bit 1: clk_16k1 to VDD_CORE domain
+        //
+        // TODO: Define sub-fields for this register with a PAC patch?
+        let mut bits = 0;
+        if *vsys_domain_active {
+            bits |= 0b01;
+            self.clocks.clk_16k_vsys = Some(Clock {
+                frequency: 16_384,
+                power: PoweredClock::AlwaysEnabled,
+            });
+        }
+        if *vdd_core_domain_active {
+            bits |= 0b10;
+            self.clocks.clk_16k_vdd_core = Some(Clock {
+                frequency: 16_384,
+                power: PoweredClock::AlwaysEnabled,
+            });
+        }
+        self.vbat0.froclke().modify(|_r, w| unsafe { w.clke().bits(bits) });
+
+        Ok(())
+    }
+}
+
+//
+// Macros/macro impls
+//
+
+/// This macro is used to implement the [`Gate`] trait for a given peripheral
+/// that is controlled by the MRCC peripheral.
+macro_rules! impl_cc_gate {
+    ($name:ident, $clk_reg:ident, $rst_reg:ident, $field:ident, $config:ty) => {
+        impl Gate for crate::peripherals::$name {
+            type MrccPeriphConfig = $config;
+
+            #[inline]
+            unsafe fn enable_clock() {
+                let mrcc = unsafe { pac::Mrcc0::steal() };
+                mrcc.$clk_reg().modify(|_, w| w.$field().enabled());
+            }
+
+            #[inline]
+            unsafe fn disable_clock() {
+                let mrcc = unsafe { pac::Mrcc0::steal() };
+                mrcc.$clk_reg().modify(|_r, w| w.$field().disabled());
+            }
+
+            #[inline]
+            fn is_clock_enabled() -> bool {
+                let mrcc = unsafe { pac::Mrcc0::steal() };
+                mrcc.$clk_reg().read().$field().is_enabled()
+            }
+
+            #[inline]
+            unsafe fn release_reset() {
+                let mrcc = unsafe { pac::Mrcc0::steal() };
+                mrcc.$rst_reg().modify(|_, w| w.$field().enabled());
+            }
+
+            #[inline]
+            unsafe fn assert_reset() {
+                let mrcc = unsafe { pac::Mrcc0::steal() };
+                mrcc.$rst_reg().modify(|_, w| w.$field().disabled());
+            }
+
+            #[inline]
+            fn is_reset_released() -> bool {
+                let mrcc = unsafe { pac::Mrcc0::steal() };
+                mrcc.$rst_reg().read().$field().is_enabled()
+            }
+        }
+    };
+}
+
+/// This module contains implementations of MRCC APIs, specifically of the [`Gate`] trait,
+/// for various low level peripherals.
+pub(crate) mod gate {
+    #[cfg(not(feature = "time"))]
+    use super::periph_helpers::OsTimerConfig;
+    use super::periph_helpers::{AdcConfig, Lpi2cConfig, LpuartConfig, NoConfig};
+    use super::*;
+
+    // These peripherals have no additional upstream clocks or configuration required
+    // other than enabling through the MRCC gate. Currently, these peripherals will
+    // ALWAYS return `Ok(0)` when calling [`enable_and_reset()`] and/or
+    // [`SPConfHelper::post_enable_config()`].
+    impl_cc_gate!(PORT0, mrcc_glb_cc1, mrcc_glb_rst1, port0, NoConfig);
+    impl_cc_gate!(PORT1, mrcc_glb_cc1, mrcc_glb_rst1, port1, NoConfig);
+    impl_cc_gate!(PORT2, mrcc_glb_cc1, mrcc_glb_rst1, port2, NoConfig);
+    impl_cc_gate!(PORT3, mrcc_glb_cc1, mrcc_glb_rst1, port3, NoConfig);
+    impl_cc_gate!(PORT4, mrcc_glb_cc1, mrcc_glb_rst1, port4, NoConfig);
+
+    impl_cc_gate!(GPIO0, mrcc_glb_cc2, mrcc_glb_rst2, gpio0, NoConfig);
+    impl_cc_gate!(GPIO1, mrcc_glb_cc2, mrcc_glb_rst2, gpio1, NoConfig);
+    impl_cc_gate!(GPIO2, mrcc_glb_cc2, mrcc_glb_rst2, gpio2, NoConfig);
+    impl_cc_gate!(GPIO3, mrcc_glb_cc2, mrcc_glb_rst2, gpio3, NoConfig);
+    impl_cc_gate!(GPIO4, mrcc_glb_cc2, mrcc_glb_rst2, gpio4, NoConfig);
+
+    impl_cc_gate!(CRC0, mrcc_glb_cc0, mrcc_glb_rst0, crc0, NoConfig);
+
+    // These peripherals DO have meaningful configuration, and could fail if the system
+    // clocks do not match their needs.
+    #[cfg(not(feature = "time"))]
+    impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, mrcc_glb_rst1, ostimer0, OsTimerConfig);
+
+    impl_cc_gate!(LPI2C0, mrcc_glb_cc0, mrcc_glb_rst0, lpi2c0, Lpi2cConfig);
+    impl_cc_gate!(LPI2C1, mrcc_glb_cc0, mrcc_glb_rst0, lpi2c1, Lpi2cConfig);
+    impl_cc_gate!(LPI2C2, mrcc_glb_cc1, mrcc_glb_rst1, lpi2c2, Lpi2cConfig);
+    impl_cc_gate!(LPI2C3, mrcc_glb_cc1, mrcc_glb_rst1, lpi2c3, Lpi2cConfig);
+
+    impl_cc_gate!(LPUART0, mrcc_glb_cc0, mrcc_glb_rst0, lpuart0, LpuartConfig);
+    impl_cc_gate!(LPUART1, mrcc_glb_cc0, mrcc_glb_rst0, lpuart1, LpuartConfig);
+    impl_cc_gate!(LPUART2, mrcc_glb_cc0, mrcc_glb_rst0, lpuart2, LpuartConfig);
+    impl_cc_gate!(LPUART3, mrcc_glb_cc0, mrcc_glb_rst0, lpuart3, LpuartConfig);
+    impl_cc_gate!(LPUART4, mrcc_glb_cc0, mrcc_glb_rst0, lpuart4, LpuartConfig);
+    impl_cc_gate!(LPUART5, mrcc_glb_cc1, mrcc_glb_rst1, lpuart5, LpuartConfig);
+    impl_cc_gate!(ADC0, mrcc_glb_cc1, mrcc_glb_rst1, adc0, AdcConfig);
+    impl_cc_gate!(ADC1, mrcc_glb_cc1, mrcc_glb_rst1, adc1, AdcConfig);
+    impl_cc_gate!(ADC2, mrcc_glb_cc1, mrcc_glb_rst1, adc2, AdcConfig);
+    impl_cc_gate!(ADC3, mrcc_glb_cc1, mrcc_glb_rst1, adc3, AdcConfig);
+
+    // DMA0 peripheral - uses NoConfig since it has no selectable clock source
+    impl_cc_gate!(DMA0, mrcc_glb_cc0, mrcc_glb_rst0, dma0, NoConfig);
+}
diff --git a/embassy-mcxa/src/clocks/periph_helpers.rs b/embassy-mcxa/src/clocks/periph_helpers.rs
new file mode 100644
index 000000000..f2f51c60c
--- /dev/null
+++ b/embassy-mcxa/src/clocks/periph_helpers.rs
@@ -0,0 +1,499 @@
+//! Peripheral Helpers
+//!
+//! The purpose of this module is to define the per-peripheral special handling
+//! required from a clocking perspective. Different peripherals have different
+//! selectable source clocks, and some peripherals have additional pre-dividers
+//! that can be used.
+//!
+//! See the docs of [`SPConfHelper`] for more details.
+
+use super::{ClockError, Clocks, PoweredClock};
+use crate::pac;
+
+/// Sealed Peripheral Configuration Helper
+///
+/// NOTE: the name "sealed" doesn't *totally* make sense because its not sealed yet in the
+/// embassy-mcxa project, but it derives from embassy-imxrt where it is. We should
+/// fix the name, or actually do the sealing of peripherals.
+///
+/// This trait serves to act as a per-peripheral customization for clocking behavior.
+///
+/// This trait should be implemented on a configuration type for a given peripheral, and
+/// provide the methods that will be called by the higher level operations like
+/// `embassy_mcxa::clocks::enable_and_reset()`.
+pub trait SPConfHelper {
+    /// This method is called AFTER a given MRCC peripheral has been enabled (e.g. un-gated),
+    /// but BEFORE the peripheral reset line is reset.
+    ///
+    /// This function should check that any relevant upstream clocks are enabled, are in a
+    /// reasonable power state, and that the requested configuration can be made. If any of
+    /// these checks fail, an `Err(ClockError)` should be returned, likely `ClockError::BadConfig`.
+    ///
+    /// This function SHOULD NOT make any changes to the system clock configuration, even
+    /// unsafely, as this should remain static for the duration of the program.
+    ///
+    /// This function WILL be called in a critical section, care should be taken not to delay
+    /// for an unreasonable amount of time.
+    ///
+    /// On success, this function MUST return an `Ok(freq)`, where `freq` is the frequency
+    /// fed into the peripheral, taking into account the selected source clock, as well as
+    /// any pre-divisors.
+    fn post_enable_config(&self, clocks: &Clocks) -> Result<u32, ClockError>;
+}
+
+/// Copy and paste macro that:
+///
+/// * Sets the clocksel mux to `$selvar`
+/// * Resets and halts the div, and applies the calculated div4 bits
+/// * Releases reset + halt
+/// * Waits for the div to stabilize
+/// * Returns `Ok($freq / $conf.div.into_divisor())`
+///
+/// Assumes:
+///
+/// * self is a configuration struct that has a field called `div`, which
+///   is a `Div4`
+///
+/// usage:
+///
+/// ```rust
+/// apply_div4!(self, clksel, clkdiv, variant, freq)
+/// ```
+///
+/// In the future if we make all the clksel+clkdiv pairs into commonly derivedFrom
+/// registers, or if we put some kind of simple trait around those regs, we could
+/// do this with something other than a macro, but for now, this is harm-reduction
+/// to avoid incorrect copy + paste
+macro_rules! apply_div4 {
+    ($conf:ident, $selreg:ident, $divreg:ident, $selvar:ident, $freq:ident) => {{
+        // set clksel
+        $selreg.modify(|_r, w| w.mux().variant($selvar));
+
+        // Set up clkdiv
+        $divreg.modify(|_r, w| {
+            unsafe { w.div().bits($conf.div.into_bits()) }
+                .halt()
+                .asserted()
+                .reset()
+                .asserted()
+        });
+        $divreg.modify(|_r, w| w.halt().deasserted().reset().deasserted());
+
+        while $divreg.read().unstab().is_unstable() {}
+
+        Ok($freq / $conf.div.into_divisor())
+    }};
+}
+
+// config types
+
+/// This type represents a divider in the range 1..=16.
+///
+/// At a hardware level, this is an 8-bit register from 0..=15,
+/// which adds one.
+///
+/// While the *clock* domain seems to use 8-bit dividers, the *peripheral* domain
+/// seems to use 4 bit dividers!
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub struct Div4(pub(super) u8);
+
+impl Div4 {
+    /// Divide by one, or no division
+    pub const fn no_div() -> Self {
+        Self(0)
+    }
+
+    /// Store a "raw" divisor value that will divide the source by
+    /// `(n + 1)`, e.g. `Div4::from_raw(0)` will divide the source
+    /// by 1, and `Div4::from_raw(15)` will divide the source by
+    /// 16.
+    pub const fn from_raw(n: u8) -> Option<Self> {
+        if n > 0b1111 { None } else { Some(Self(n)) }
+    }
+
+    /// Store a specific divisor value that will divide the source
+    /// by `n`. e.g. `Div4::from_divisor(1)` will divide the source
+    /// by 1, and `Div4::from_divisor(16)` will divide the source
+    /// by 16.
+    ///
+    /// Will return `None` if `n` is not in the range `1..=16`.
+    /// Consider [`Self::from_raw`] for an infallible version.
+    pub const fn from_divisor(n: u8) -> Option<Self> {
+        let Some(n) = n.checked_sub(1) else {
+            return None;
+        };
+        if n > 0b1111 {
+            return None;
+        }
+        Some(Self(n))
+    }
+
+    /// Convert into "raw" bits form
+    #[inline(always)]
+    pub const fn into_bits(self) -> u8 {
+        self.0
+    }
+
+    /// Convert into "divisor" form, as a u32 for convenient frequency math
+    #[inline(always)]
+    pub const fn into_divisor(self) -> u32 {
+        self.0 as u32 + 1
+    }
+}
+
+/// A basic type that always returns an error when `post_enable_config` is called.
+///
+/// Should only be used as a placeholder.
+pub struct UnimplementedConfig;
+
+impl SPConfHelper for UnimplementedConfig {
+    fn post_enable_config(&self, _clocks: &Clocks) -> Result<u32, ClockError> {
+        Err(ClockError::UnimplementedConfig)
+    }
+}
+
+/// A basic type that always returns `Ok(0)` when `post_enable_config` is called.
+///
+/// This should only be used for peripherals that are "ambiently" clocked, like `PORTn`
+/// peripherals, which have no selectable/configurable source clock.
+pub struct NoConfig;
+impl SPConfHelper for NoConfig {
+    fn post_enable_config(&self, _clocks: &Clocks) -> Result<u32, ClockError> {
+        Ok(0)
+    }
+}
+
+//
+// LPI2c
+//
+
+/// Selectable clocks for `Lpi2c` peripherals
+#[derive(Debug, Clone, Copy)]
+pub enum Lpi2cClockSel {
+    /// FRO12M/FRO_LF/SIRC clock source, passed through divider
+    /// "fro_lf_div"
+    FroLfDiv,
+    /// FRO180M/FRO_HF/FIRC clock source, passed through divider
+    /// "fro_hf_div"
+    FroHfDiv,
+    /// SOSC/XTAL/EXTAL clock source
+    ClkIn,
+    /// clk_1m/FRO_LF divided by 12
+    Clk1M,
+    /// Output of PLL1, passed through clock divider,
+    /// "pll1_clk_div", maybe "pll1_lf_div"?
+    Pll1ClkDiv,
+    /// Disabled
+    None,
+}
+
+/// Which instance of the `Lpi2c` is this?
+///
+/// Should not be directly selectable by end-users.
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum Lpi2cInstance {
+    /// Instance 0
+    Lpi2c0,
+    /// Instance 1
+    Lpi2c1,
+    /// Instance 2
+    Lpi2c2,
+    /// Instance 3
+    Lpi2c3,
+}
+
+/// Top level configuration for `Lpi2c` instances.
+pub struct Lpi2cConfig {
+    /// Power state required for this peripheral
+    pub power: PoweredClock,
+    /// Clock source
+    pub source: Lpi2cClockSel,
+    /// Clock divisor
+    pub div: Div4,
+    /// Which instance is this?
+    // NOTE: should not be user settable
+    pub(crate) instance: Lpi2cInstance,
+}
+
+impl SPConfHelper for Lpi2cConfig {
+    fn post_enable_config(&self, clocks: &Clocks) -> Result<u32, ClockError> {
+        // check that source is suitable
+        let mrcc0 = unsafe { pac::Mrcc0::steal() };
+        use mcxa_pac::mrcc0::mrcc_lpi2c0_clksel::Mux;
+
+        let (clkdiv, clksel) = match self.instance {
+            Lpi2cInstance::Lpi2c0 => (mrcc0.mrcc_lpi2c0_clkdiv(), mrcc0.mrcc_lpi2c0_clksel()),
+            Lpi2cInstance::Lpi2c1 => (mrcc0.mrcc_lpi2c1_clkdiv(), mrcc0.mrcc_lpi2c1_clksel()),
+            Lpi2cInstance::Lpi2c2 => (mrcc0.mrcc_lpi2c2_clkdiv(), mrcc0.mrcc_lpi2c2_clksel()),
+            Lpi2cInstance::Lpi2c3 => (mrcc0.mrcc_lpi2c3_clkdiv(), mrcc0.mrcc_lpi2c3_clksel()),
+        };
+
+        let (freq, variant) = match self.source {
+            Lpi2cClockSel::FroLfDiv => {
+                let freq = clocks.ensure_fro_lf_div_active(&self.power)?;
+                (freq, Mux::ClkrootFunc0)
+            }
+            Lpi2cClockSel::FroHfDiv => {
+                let freq = clocks.ensure_fro_hf_div_active(&self.power)?;
+                (freq, Mux::ClkrootFunc2)
+            }
+            Lpi2cClockSel::ClkIn => {
+                let freq = clocks.ensure_clk_in_active(&self.power)?;
+                (freq, Mux::ClkrootFunc3)
+            }
+            Lpi2cClockSel::Clk1M => {
+                let freq = clocks.ensure_clk_1m_active(&self.power)?;
+                (freq, Mux::ClkrootFunc5)
+            }
+            Lpi2cClockSel::Pll1ClkDiv => {
+                let freq = clocks.ensure_pll1_clk_div_active(&self.power)?;
+                (freq, Mux::ClkrootFunc6)
+            }
+            Lpi2cClockSel::None => unsafe {
+                // no ClkrootFunc7, just write manually for now
+                clksel.write(|w| w.bits(0b111));
+                clkdiv.modify(|_r, w| w.reset().asserted().halt().asserted());
+                return Ok(0);
+            },
+        };
+
+        apply_div4!(self, clksel, clkdiv, variant, freq)
+    }
+}
+
+//
+// LPUart
+//
+
+/// Selectable clocks for Lpuart peripherals
+#[derive(Debug, Clone, Copy)]
+pub enum LpuartClockSel {
+    /// FRO12M/FRO_LF/SIRC clock source, passed through divider
+    /// "fro_lf_div"
+    FroLfDiv,
+    /// FRO180M/FRO_HF/FIRC clock source, passed through divider
+    /// "fro_hf_div"
+    FroHfDiv,
+    /// SOSC/XTAL/EXTAL clock source
+    ClkIn,
+    /// FRO16K/clk_16k source
+    Clk16K,
+    /// clk_1m/FRO_LF divided by 12
+    Clk1M,
+    /// Output of PLL1, passed through clock divider,
+    /// "pll1_clk_div", maybe "pll1_lf_div"?
+    Pll1ClkDiv,
+    /// Disabled
+    None,
+}
+
+/// Which instance of the Lpuart is this?
+///
+/// Should not be directly selectable by end-users.
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum LpuartInstance {
+    /// Instance 0
+    Lpuart0,
+    /// Instance 1
+    Lpuart1,
+    /// Instance 2
+    Lpuart2,
+    /// Instance 3
+    Lpuart3,
+    /// Instance 4
+    Lpuart4,
+    /// Instance 5
+    Lpuart5,
+}
+
+/// Top level configuration for `Lpuart` instances.
+pub struct LpuartConfig {
+    /// Power state required for this peripheral
+    pub power: PoweredClock,
+    /// Clock source
+    pub source: LpuartClockSel,
+    /// Clock divisor
+    pub div: Div4,
+    /// Which instance is this?
+    // NOTE: should not be user settable
+    pub(crate) instance: LpuartInstance,
+}
+
+impl SPConfHelper for LpuartConfig {
+    fn post_enable_config(&self, clocks: &Clocks) -> Result<u32, ClockError> {
+        // check that source is suitable
+        let mrcc0 = unsafe { pac::Mrcc0::steal() };
+        use mcxa_pac::mrcc0::mrcc_lpuart0_clksel::Mux;
+
+        let (clkdiv, clksel) = match self.instance {
+            LpuartInstance::Lpuart0 => (mrcc0.mrcc_lpuart0_clkdiv(), mrcc0.mrcc_lpuart0_clksel()),
+            LpuartInstance::Lpuart1 => (mrcc0.mrcc_lpuart1_clkdiv(), mrcc0.mrcc_lpuart1_clksel()),
+            LpuartInstance::Lpuart2 => (mrcc0.mrcc_lpuart2_clkdiv(), mrcc0.mrcc_lpuart2_clksel()),
+            LpuartInstance::Lpuart3 => (mrcc0.mrcc_lpuart3_clkdiv(), mrcc0.mrcc_lpuart3_clksel()),
+            LpuartInstance::Lpuart4 => (mrcc0.mrcc_lpuart4_clkdiv(), mrcc0.mrcc_lpuart4_clksel()),
+            LpuartInstance::Lpuart5 => (mrcc0.mrcc_lpuart5_clkdiv(), mrcc0.mrcc_lpuart5_clksel()),
+        };
+
+        let (freq, variant) = match self.source {
+            LpuartClockSel::FroLfDiv => {
+                let freq = clocks.ensure_fro_lf_div_active(&self.power)?;
+                (freq, Mux::ClkrootFunc0)
+            }
+            LpuartClockSel::FroHfDiv => {
+                let freq = clocks.ensure_fro_hf_div_active(&self.power)?;
+                (freq, Mux::ClkrootFunc2)
+            }
+            LpuartClockSel::ClkIn => {
+                let freq = clocks.ensure_clk_in_active(&self.power)?;
+                (freq, Mux::ClkrootFunc3)
+            }
+            LpuartClockSel::Clk16K => {
+                let freq = clocks.ensure_clk_16k_vdd_core_active(&self.power)?;
+                (freq, Mux::ClkrootFunc4)
+            }
+            LpuartClockSel::Clk1M => {
+                let freq = clocks.ensure_clk_1m_active(&self.power)?;
+                (freq, Mux::ClkrootFunc5)
+            }
+            LpuartClockSel::Pll1ClkDiv => {
+                let freq = clocks.ensure_pll1_clk_div_active(&self.power)?;
+                (freq, Mux::ClkrootFunc6)
+            }
+            LpuartClockSel::None => unsafe {
+                // no ClkrootFunc7, just write manually for now
+                clksel.write(|w| w.bits(0b111));
+                clkdiv.modify(|_r, w| {
+                    w.reset().asserted();
+                    w.halt().asserted();
+                    w
+                });
+                return Ok(0);
+            },
+        };
+
+        // set clksel
+        apply_div4!(self, clksel, clkdiv, variant, freq)
+    }
+}
+
+//
+// OSTimer
+//
+
+/// Selectable clocks for the OSTimer peripheral
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum OstimerClockSel {
+    /// 16k clock, sourced from FRO16K (Vdd Core)
+    Clk16kVddCore,
+    /// 1 MHz Clock sourced from FRO12M
+    Clk1M,
+    /// Disabled
+    None,
+}
+
+/// Top level configuration for the `OSTimer` peripheral
+pub struct OsTimerConfig {
+    /// Power state required for this peripheral
+    pub power: PoweredClock,
+    /// Selected clock source for this peripheral
+    pub source: OstimerClockSel,
+}
+
+impl SPConfHelper for OsTimerConfig {
+    fn post_enable_config(&self, clocks: &Clocks) -> Result<u32, ClockError> {
+        let mrcc0 = unsafe { pac::Mrcc0::steal() };
+        Ok(match self.source {
+            OstimerClockSel::Clk16kVddCore => {
+                let freq = clocks.ensure_clk_16k_vdd_core_active(&self.power)?;
+                mrcc0.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_16k());
+                freq
+            }
+            OstimerClockSel::Clk1M => {
+                let freq = clocks.ensure_clk_1m_active(&self.power)?;
+                mrcc0.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m());
+                freq
+            }
+            OstimerClockSel::None => {
+                mrcc0.mrcc_ostimer0_clksel().write(|w| unsafe { w.mux().bits(0b11) });
+                0
+            }
+        })
+    }
+}
+
+//
+// Adc
+//
+
+/// Selectable clocks for the ADC peripheral
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum AdcClockSel {
+    /// Divided `fro_lf`/`clk_12m`/FRO12M source
+    FroLfDiv,
+    /// Gated `fro_hf`/`FRO180M` source
+    FroHf,
+    /// External Clock Source
+    ClkIn,
+    /// 1MHz clock sourced by a divided `fro_lf`/`clk_12m`
+    Clk1M,
+    /// Internal PLL output, with configurable divisor
+    Pll1ClkDiv,
+    /// No clock/disabled
+    None,
+}
+
+/// Top level configuration for the ADC peripheral
+pub struct AdcConfig {
+    /// Power state required for this peripheral
+    pub power: PoweredClock,
+    /// Selected clock-source for this peripheral
+    pub source: AdcClockSel,
+    /// Pre-divisor, applied to the upstream clock output
+    pub div: Div4,
+}
+
+impl SPConfHelper for AdcConfig {
+    fn post_enable_config(&self, clocks: &Clocks) -> Result<u32, ClockError> {
+        use mcxa_pac::mrcc0::mrcc_adc_clksel::Mux;
+        let mrcc0 = unsafe { pac::Mrcc0::steal() };
+        let (freq, variant) = match self.source {
+            AdcClockSel::FroLfDiv => {
+                let freq = clocks.ensure_fro_lf_div_active(&self.power)?;
+                (freq, Mux::ClkrootFunc0)
+            }
+            AdcClockSel::FroHf => {
+                let freq = clocks.ensure_fro_hf_active(&self.power)?;
+                (freq, Mux::ClkrootFunc1)
+            }
+            AdcClockSel::ClkIn => {
+                let freq = clocks.ensure_clk_in_active(&self.power)?;
+                (freq, Mux::ClkrootFunc3)
+            }
+            AdcClockSel::Clk1M => {
+                let freq = clocks.ensure_clk_1m_active(&self.power)?;
+                (freq, Mux::ClkrootFunc5)
+            }
+            AdcClockSel::Pll1ClkDiv => {
+                let freq = clocks.ensure_pll1_clk_div_active(&self.power)?;
+                (freq, Mux::ClkrootFunc6)
+            }
+            AdcClockSel::None => {
+                mrcc0.mrcc_adc_clksel().write(|w| unsafe {
+                    // no ClkrootFunc7, just write manually for now
+                    w.mux().bits(0b111)
+                });
+                mrcc0.mrcc_adc_clkdiv().modify(|_r, w| {
+                    w.reset().asserted();
+                    w.halt().asserted();
+                    w
+                });
+                return Ok(0);
+            }
+        };
+        let clksel = mrcc0.mrcc_adc_clksel();
+        let clkdiv = mrcc0.mrcc_adc_clkdiv();
+
+        apply_div4!(self, clksel, clkdiv, variant, freq)
+    }
+}
diff --git a/embassy-mcxa/src/config.rs b/embassy-mcxa/src/config.rs
new file mode 100644
index 000000000..8d52a1d44
--- /dev/null
+++ b/embassy-mcxa/src/config.rs
@@ -0,0 +1,27 @@
+// HAL configuration (minimal), mirroring embassy-imxrt style
+
+use crate::clocks::config::ClocksConfig;
+use crate::interrupt::Priority;
+
+#[non_exhaustive]
+pub struct Config {
+    #[cfg(feature = "time")]
+    pub time_interrupt_priority: Priority,
+    pub rtc_interrupt_priority: Priority,
+    pub adc_interrupt_priority: Priority,
+    pub gpio_interrupt_priority: Priority,
+    pub clock_cfg: ClocksConfig,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            #[cfg(feature = "time")]
+            time_interrupt_priority: Priority::from(0),
+            rtc_interrupt_priority: Priority::from(0),
+            adc_interrupt_priority: Priority::from(0),
+            gpio_interrupt_priority: Priority::from(0),
+            clock_cfg: ClocksConfig::default(),
+        }
+    }
+}
diff --git a/embassy-mcxa/src/crc.rs b/embassy-mcxa/src/crc.rs
new file mode 100644
index 000000000..753a59122
--- /dev/null
+++ b/embassy-mcxa/src/crc.rs
@@ -0,0 +1,758 @@
+//! Cyclic Redundancy Check (CRC)
+
+use core::marker::PhantomData;
+
+use embassy_hal_internal::Peri;
+use mcxa_pac::crc0::ctrl::{Fxor, Tcrc, Tot, Totr};
+
+use crate::clocks::enable_and_reset;
+use crate::clocks::periph_helpers::NoConfig;
+use crate::peripherals::CRC0;
+
+/// CRC driver.
+pub struct Crc<'d, M> {
+    _peri: Peri<'d, CRC0>,
+    _phantom: PhantomData<M>,
+}
+
+impl<'d, M: Mode> Crc<'d, M> {
+    fn new_inner(_peri: Peri<'d, CRC0>) -> Self {
+        _ = unsafe { enable_and_reset::<CRC0>(&NoConfig) };
+
+        Crc {
+            _peri,
+            _phantom: PhantomData,
+        }
+    }
+
+    // Configure the underlying peripheral according to the reference manual.
+    fn configure(config: Config, width: Tcrc) {
+        Self::regs().ctrl().modify(|_, w| {
+            w.fxor()
+                .variant(config.complement_out.into())
+                .totr()
+                .variant(config.reflect_out.into())
+                .tot()
+                .variant(config.reflect_in.into())
+                .was()
+                .data()
+                .tcrc()
+                .variant(width)
+        });
+
+        Self::regs().gpoly32().write(|w| unsafe { w.bits(config.polynomial) });
+
+        Self::regs().ctrl().modify(|_, w| w.was().seed());
+        Self::regs().data32().write(|w| unsafe { w.bits(config.seed) });
+        Self::regs().ctrl().modify(|_, w| w.was().data());
+    }
+
+    fn regs() -> &'static crate::pac::crc0::RegisterBlock {
+        unsafe { &*crate::pac::Crc0::ptr() }
+    }
+
+    /// Read the computed CRC value
+    fn finalize_inner<W: Word>(self) -> W {
+        // Reference manual states:
+        //
+        // "After writing all the data, you must wait for at least two
+        // clock cycles to read the data from CRC Data (DATA)
+        // register."
+        cortex_m::asm::delay(2);
+        W::read(Self::regs())
+    }
+
+    fn feed_word<W: Word>(&mut self, word: W) {
+        W::write(Self::regs(), word);
+    }
+
+    /// Feeds a slice of `Word`s into the CRC peripheral. Returns the computed
+    /// checksum.
+    ///
+    /// The input is strided efficiently into as many `u32`s as possible,
+    /// falling back to smaller writes for the remainder.
+    fn feed_inner<W: Word>(&mut self, data: &[W]) {
+        let (prefix, aligned, suffix) = unsafe { data.align_to::<u32>() };
+
+        for w in prefix {
+            self.feed_word(*w);
+        }
+
+        for w in aligned {
+            self.feed_word(*w);
+        }
+
+        for w in suffix {
+            self.feed_word(*w);
+        }
+    }
+}
+
+impl<'d> Crc<'d, Crc16> {
+    /// Instantiates a new CRC peripheral driver in 16-bit mode
+    pub fn new_crc16(peri: Peri<'d, CRC0>, config: Config) -> Self {
+        let inst = Self::new_inner(peri);
+        Self::configure(config, Tcrc::B16);
+        inst
+    }
+
+    /// Instantiates a new CRC peripheral driver for the given `Algorithm16`.
+    pub fn new_algorithm16(peri: Peri<'d, CRC0>, algorithm: Algorithm16) -> Self {
+        Self::new_crc16(peri, algorithm.into_config())
+    }
+
+    /// Instantiates a new CRC peripheral for the `A` algorithm.
+    pub fn new_a(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::A)
+    }
+
+    /// Instantiates a new CRC peripheral for the `AugCcitt` algorithm.
+    pub fn new_aug_ccitt(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::AugCcitt)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Arc` algorithm.
+    pub fn new_arc(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Arc)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Buypass` algorithm.
+    pub fn new_buypass(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Buypass)
+    }
+
+    /// Instantiates a new CRC peripheral for the `CcittFalse` algorithm.
+    pub fn new_ccitt_false(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::CcittFalse)
+    }
+
+    /// Instantiates a new CRC peripheral for the `CcittZero` algorithm.
+    pub fn new_ccitt_zero(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::CcittZero)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Cdma2000` algorithm.
+    pub fn new_cdma_2000(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Cdma2000)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Dds110` algorithm.
+    pub fn new_dds_110(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Dds110)
+    }
+
+    /// Instantiates a new CRC peripheral for the `DectX` algorithm.
+    pub fn new_dect_x(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::DectX)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Dnp` algorithm.
+    pub fn new_dnp(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Dnp)
+    }
+
+    /// Instantiates a new CRC peripheral for the `En13757` algorithm.
+    pub fn new_en13757(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::En13757)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Genibus` algorithm.
+    pub fn new_genibus(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Genibus)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Kermit` algorithm.
+    pub fn new_kermit(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Kermit)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Maxim` algorithm.
+    pub fn new_maxim(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Maxim)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Mcrf4xx` algorithm.
+    pub fn new_mcrf4xx(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Mcrf4xx)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Modbus` algorithm.
+    pub fn new_modbus(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Modbus)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Riello` algorithm.
+    pub fn new_riello(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Riello)
+    }
+
+    /// Instantiates a new CRC peripheral for the `T10Dif` algorithm.
+    pub fn new_t10_dif(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::T10Dif)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Teledisk` algorithm.
+    pub fn new_teledisk(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Teledisk)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Tms37157` algorithm.
+    pub fn new_tms_37157(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Tms37157)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Usb` algorithm.
+    pub fn new_usb(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Usb)
+    }
+
+    /// Instantiates a new CRC peripheral for the `X25` algorithm.
+    pub fn new_x25(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::X25)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Xmodem` algorithm.
+    pub fn new_xmodem(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm16(peri, Algorithm16::Xmodem)
+    }
+
+    /// Feeds a slice of `Word`s into the CRC peripheral.
+    ///
+    /// The input is strided efficiently into as many `u32`s as possible,
+    /// falling back to smaller writes for the remainder.
+    pub fn feed<W: Word>(&mut self, data: &[W]) {
+        self.feed_inner(data);
+    }
+
+    /// Finalizes the CRC calculation and reads the resulting CRC from the
+    /// hardware consuming `self`.
+    pub fn finalize(self) -> u16 {
+        self.finalize_inner()
+    }
+}
+
+impl<'d> Crc<'d, Crc32> {
+    /// Instantiates a new CRC peripheral driver in 32-bit mode
+    pub fn new_crc32(peri: Peri<'d, CRC0>, config: Config) -> Self {
+        let inst = Self::new_inner(peri);
+        Self::configure(config, Tcrc::B32);
+        inst
+    }
+
+    /// Instantiates a new CRC peripheral driver for the given `Algorithm32`.
+    pub fn new_algorithm32(peri: Peri<'d, CRC0>, algorithm: Algorithm32) -> Self {
+        Self::new_crc32(peri, algorithm.into_config())
+    }
+
+    /// Instantiates a new CRC peripheral for the `Bzip2` algorithm.
+    pub fn new_bzip2(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm32(peri, Algorithm32::Bzip2)
+    }
+
+    /// Instantiates a new CRC peripheral for the `C` algorithm.
+    pub fn new_c(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm32(peri, Algorithm32::C)
+    }
+
+    /// Instantiates a new CRC peripheral for the `D` algorithm.
+    pub fn new_d(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm32(peri, Algorithm32::D)
+    }
+
+    /// Instantiates a new CRC peripheral for the `IsoHdlc` algorithm.
+    pub fn new_iso_hdlc(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm32(peri, Algorithm32::IsoHdlc)
+    }
+
+    /// Instantiates a new CRC peripheral for the `JamCrc` algorithm.
+    pub fn new_jam_crc(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm32(peri, Algorithm32::JamCrc)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Mpeg2` algorithm.
+    pub fn new_mpeg2(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm32(peri, Algorithm32::Mpeg2)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Posix` algorithm.
+    pub fn new_posix(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm32(peri, Algorithm32::Posix)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Q` algorithm.
+    pub fn new_q(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm32(peri, Algorithm32::Q)
+    }
+
+    /// Instantiates a new CRC peripheral for the `Xfer` algorithm.
+    pub fn new_xfer(peri: Peri<'d, CRC0>) -> Self {
+        Self::new_algorithm32(peri, Algorithm32::Xfer)
+    }
+
+    /// Feeds a slice of `Word`s into the CRC peripheral.
+    ///
+    /// The input is strided efficiently into as many `u32`s as possible,
+    /// falling back to smaller writes for the remainder.
+    pub fn feed<W: Word>(&mut self, data: &[W]) {
+        self.feed_inner(data);
+    }
+
+    /// Finalizes the CRC calculation and reads the resulting CRC from the
+    /// hardware consuming `self`.
+    pub fn finalize(self) -> u32 {
+        self.finalize_inner()
+    }
+}
+
+mod sealed {
+    pub trait SealedMode {}
+
+    pub trait SealedWord: Copy {
+        fn write(regs: &'static crate::pac::crc0::RegisterBlock, word: Self);
+        fn read(regs: &'static crate::pac::crc0::RegisterBlock) -> Self;
+    }
+}
+
+/// Mode of operation: 32 or 16-bit CRC.
+#[allow(private_bounds)]
+pub trait Mode: sealed::SealedMode {}
+
+/// 16-bit CRC.
+pub struct Crc16;
+impl sealed::SealedMode for Crc16 {}
+impl Mode for Crc16 {}
+
+/// 32-bit CRC.
+pub struct Crc32;
+impl sealed::SealedMode for Crc32 {}
+impl Mode for Crc32 {}
+
+/// Word size for the CRC.
+#[allow(private_bounds)]
+pub trait Word: sealed::SealedWord {}
+
+macro_rules! impl_word {
+    ($t:ty, $width:literal, $write:expr, $read:expr) => {
+        impl sealed::SealedWord for $t {
+            #[inline]
+            fn write(regs: &'static crate::pac::crc0::RegisterBlock, word: Self) {
+                $write(regs, word)
+            }
+
+            #[inline]
+            fn read(regs: &'static crate::pac::crc0::RegisterBlock) -> Self {
+                $read(regs)
+            }
+        }
+
+        impl Word for $t {}
+    };
+}
+
+impl_word!(u8, 8, write_u8, read_u8);
+impl_word!(u16, 16, write_u16, read_u16);
+impl_word!(u32, 32, write_u32, read_u32);
+
+fn write_u8(regs: &'static crate::pac::crc0::RegisterBlock, word: u8) {
+    regs.data8().write(|w| unsafe { w.bits(word) });
+}
+
+fn read_u8(regs: &'static crate::pac::crc0::RegisterBlock) -> u8 {
+    regs.data8().read().bits()
+}
+
+fn write_u16(regs: &'static crate::pac::crc0::RegisterBlock, word: u16) {
+    regs.data16().write(|w| unsafe { w.bits(word) });
+}
+
+fn read_u16(regs: &'static crate::pac::crc0::RegisterBlock) -> u16 {
+    let ctrl = regs.ctrl().read();
+
+    // if transposition is enabled, result sits in the upper 16 bits
+    if ctrl.totr().is_byts_trnps() || ctrl.totr().is_byts_bts_trnps() {
+        (regs.data32().read().bits() >> 16) as u16
+    } else {
+        regs.data16().read().bits()
+    }
+}
+
+fn write_u32(regs: &'static crate::pac::crc0::RegisterBlock, word: u32) {
+    regs.data32().write(|w| unsafe { w.bits(word) });
+}
+
+fn read_u32(regs: &'static crate::pac::crc0::RegisterBlock) -> u32 {
+    regs.data32().read().bits()
+}
+
+/// CRC configuration.
+#[derive(Copy, Clone, Debug)]
+#[non_exhaustive]
+pub struct Config {
+    /// The CRC polynomial to be used.
+    pub polynomial: u32,
+
+    /// Reflect bit order of input?
+    pub reflect_in: Reflect,
+
+    /// Reflect CRC bit order?
+    pub reflect_out: Reflect,
+
+    /// 1's complement CRC?
+    pub complement_out: Complement,
+
+    /// CRC Seed
+    pub seed: u32,
+}
+
+impl Config {
+    /// Create a new CRC config.
+    #[must_use]
+    pub fn new(
+        polynomial: u32,
+        reflect_in: Reflect,
+        reflect_out: Reflect,
+        complement_out: Complement,
+        seed: u32,
+    ) -> Self {
+        Config {
+            polynomial,
+            reflect_in,
+            reflect_out,
+            complement_out,
+            seed,
+        }
+    }
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            polynomial: 0,
+            reflect_in: Reflect::No,
+            reflect_out: Reflect::No,
+            complement_out: Complement::No,
+            seed: 0xffff_ffff,
+        }
+    }
+}
+
+/// Supported standard CRC16 algorithms.
+#[derive(Copy, Clone, Debug)]
+pub enum Algorithm16 {
+    A,
+    Arc,
+    AugCcitt,
+    Buypass,
+    CcittFalse,
+    CcittZero,
+    Cdma2000,
+    Dds110,
+    DectX,
+    Dnp,
+    En13757,
+    Genibus,
+    Kermit,
+    Maxim,
+    Mcrf4xx,
+    Modbus,
+    Riello,
+    T10Dif,
+    Teledisk,
+    Tms37157,
+    Usb,
+    X25,
+    Xmodem,
+}
+
+impl Algorithm16 {
+    fn into_config(self) -> Config {
+        match self {
+            Algorithm16::A => Config {
+                polynomial: 0x1021,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::No,
+                seed: 0xc6c6,
+            },
+            Algorithm16::Arc => Config {
+                polynomial: 0x8005,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::No,
+                seed: 0,
+            },
+            Algorithm16::AugCcitt => Config {
+                polynomial: 0x1021,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0x1d0f,
+            },
+            Algorithm16::Buypass => Config {
+                polynomial: 0x8005,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0,
+            },
+            Algorithm16::CcittFalse => Config {
+                polynomial: 0x1021,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0xffff,
+            },
+            Algorithm16::CcittZero => Config {
+                polynomial: 0x1021,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0,
+            },
+            Algorithm16::Cdma2000 => Config {
+                polynomial: 0xc867,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0xffff,
+            },
+            Algorithm16::Dds110 => Config {
+                polynomial: 0x8005,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0x800d,
+            },
+            Algorithm16::DectX => Config {
+                polynomial: 0x0589,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0,
+            },
+            Algorithm16::Dnp => Config {
+                polynomial: 0x3d65,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::Yes,
+                seed: 0,
+            },
+            Algorithm16::En13757 => Config {
+                polynomial: 0x3d65,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::Yes,
+                seed: 0,
+            },
+            Algorithm16::Genibus => Config {
+                polynomial: 0x1021,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::Yes,
+                seed: 0xffff,
+            },
+            Algorithm16::Kermit => Config {
+                polynomial: 0x1021,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::No,
+                seed: 0,
+            },
+            Algorithm16::Maxim => Config {
+                polynomial: 0x8005,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::Yes,
+                seed: 0,
+            },
+            Algorithm16::Mcrf4xx => Config {
+                polynomial: 0x1021,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::No,
+                seed: 0xffff,
+            },
+            Algorithm16::Modbus => Config {
+                polynomial: 0x8005,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::No,
+                seed: 0xffff,
+            },
+            Algorithm16::Riello => Config {
+                polynomial: 0x1021,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::No,
+                seed: 0xb2aa,
+            },
+            Algorithm16::T10Dif => Config {
+                polynomial: 0x8bb7,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0,
+            },
+            Algorithm16::Teledisk => Config {
+                polynomial: 0xa097,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0,
+            },
+            Algorithm16::Tms37157 => Config {
+                polynomial: 0x1021,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::No,
+                seed: 0x89ec,
+            },
+            Algorithm16::Usb => Config {
+                polynomial: 0x8005,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::No,
+                seed: 0xffff,
+            },
+            Algorithm16::X25 => Config {
+                polynomial: 0x1021,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::Yes,
+                seed: 0xffff,
+            },
+            Algorithm16::Xmodem => Config {
+                polynomial: 0x1021,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0,
+            },
+        }
+    }
+}
+
+/// Supported standard CRC32 algorithms.
+#[derive(Copy, Clone, Debug)]
+pub enum Algorithm32 {
+    Bzip2,
+    C,
+    D,
+    IsoHdlc,
+    JamCrc,
+    Mpeg2,
+    Posix,
+    Q,
+    Xfer,
+}
+
+impl Algorithm32 {
+    fn into_config(self) -> Config {
+        match self {
+            Algorithm32::Bzip2 => Config {
+                polynomial: 0x04c1_1db7,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::Yes,
+                seed: 0xffff_ffff,
+            },
+            Algorithm32::C => Config {
+                polynomial: 0x1edc_6f41,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::Yes,
+                seed: 0xffff_ffff,
+            },
+            Algorithm32::D => Config {
+                polynomial: 0xa833_982b,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::Yes,
+                seed: 0xffff_ffff,
+            },
+            Algorithm32::IsoHdlc => Config {
+                polynomial: 0x04c1_1db7,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::Yes,
+                seed: 0xffff_ffff,
+            },
+            Algorithm32::JamCrc => Config {
+                polynomial: 0x04c1_1db7,
+                reflect_in: Reflect::Yes,
+                reflect_out: Reflect::Yes,
+                complement_out: Complement::No,
+                seed: 0xffff_ffff,
+            },
+            Algorithm32::Mpeg2 => Config {
+                polynomial: 0x04c1_1db7,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0xffff_ffff,
+            },
+            Algorithm32::Posix => Config {
+                polynomial: 0x04c1_1db7,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::Yes,
+                seed: 0,
+            },
+            Algorithm32::Q => Config {
+                polynomial: 0x8141_41ab,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0,
+            },
+            Algorithm32::Xfer => Config {
+                polynomial: 0x0000_00af,
+                reflect_in: Reflect::No,
+                reflect_out: Reflect::No,
+                complement_out: Complement::No,
+                seed: 0,
+            },
+        }
+    }
+}
+
+/// Reflect bit order.
+#[derive(Copy, Clone, Debug)]
+pub enum Reflect {
+    No,
+    Yes,
+}
+
+impl From<Reflect> for Tot {
+    fn from(value: Reflect) -> Tot {
+        match value {
+            Reflect::No => Tot::BytsTrnps,
+            Reflect::Yes => Tot::BytsBtsTrnps,
+        }
+    }
+}
+
+impl From<Reflect> for Totr {
+    fn from(value: Reflect) -> Totr {
+        match value {
+            Reflect::No => Totr::Notrnps,
+            Reflect::Yes => Totr::BytsBtsTrnps,
+        }
+    }
+}
+
+/// 1's complement output.
+#[derive(Copy, Clone, Debug)]
+pub enum Complement {
+    No,
+    Yes,
+}
+
+impl From<Complement> for Fxor {
+    fn from(value: Complement) -> Fxor {
+        match value {
+            Complement::No => Fxor::Noxor,
+            Complement::Yes => Fxor::Invert,
+        }
+    }
+}
diff --git a/embassy-mcxa/src/dma.rs b/embassy-mcxa/src/dma.rs
new file mode 100644
index 000000000..8d519d99b
--- /dev/null
+++ b/embassy-mcxa/src/dma.rs
@@ -0,0 +1,2602 @@
+//! DMA driver for MCXA276.
+//!
+//! This module provides a typed channel abstraction over the EDMA_0_TCD0 array
+//! and helpers for configuring the channel MUX. The driver supports both
+//! low-level TCD configuration and higher-level async transfer APIs.
+//!
+//! # Architecture
+//!
+//! The MCXA276 has 8 DMA channels (0-7), each with its own interrupt vector.
+//! Each channel has a Transfer Control Descriptor (TCD) that defines the
+//! transfer parameters.
+//!
+//! # Choosing the Right API
+//!
+//! This module provides several API levels to match different use cases:
+//!
+//! ## High-Level Async API (Recommended for Most Users)
+//!
+//! Use the async methods when you want simple, safe DMA transfers:
+//!
+//! | Method | Description |
+//! |--------|-------------|
+//! | [`DmaChannel::mem_to_mem()`] | Memory-to-memory copy |
+//! | [`DmaChannel::memset()`] | Fill memory with a pattern |
+//! | [`DmaChannel::write()`] | Memory-to-peripheral (TX) |
+//! | [`DmaChannel::read()`] | Peripheral-to-memory (RX) |
+//!
+//! These return a [`Transfer`] future that can be `.await`ed:
+//!
+//! ```no_run
+//! # use embassy_mcxa::dma::{DmaChannel, TransferOptions};
+//! # let dma_ch = DmaChannel::new(p.DMA_CH0);
+//! # let src = [0u32; 4];
+//! # let mut dst = [0u32; 4];
+//! // Simple memory-to-memory transfer
+//! unsafe {
+//!     dma_ch.mem_to_mem(&src, &mut dst, TransferOptions::default()).await;
+//! }
+//! ```
+//!
+//! ## Setup Methods (For Peripheral Drivers)
+//!
+//! Use setup methods when you need manual lifecycle control:
+//!
+//! | Method | Description |
+//! |--------|-------------|
+//! | [`DmaChannel::setup_write()`] | Configure TX without starting |
+//! | [`DmaChannel::setup_read()`] | Configure RX without starting |
+//!
+//! These configure the TCD but don't start the transfer. You control:
+//! 1. When to call [`DmaChannel::enable_request()`]
+//! 2. How to detect completion (polling or interrupts)
+//! 3. When to clean up with [`DmaChannel::clear_done()`]
+//!
+//! ## Circular/Ring Buffer API (For Continuous Reception)
+//!
+//! Use [`DmaChannel::setup_circular_read()`] for continuous data reception:
+//!
+//! ```no_run
+//! # use embassy_mcxa::dma::DmaChannel;
+//! # let dma_ch = DmaChannel::new(p.DMA_CH0);
+//! # let uart_rx_addr = 0x4000_0000 as *const u8;
+//! static mut RX_BUF: [u8; 64] = [0; 64];
+//!
+//! let ring_buf = unsafe {
+//!     dma_ch.setup_circular_read(uart_rx_addr, &mut RX_BUF)
+//! };
+//!
+//! // Read data as it arrives
+//! let mut buf = [0u8; 16];
+//! let n = ring_buf.read(&mut buf).await.unwrap();
+//! ```
+//!
+//! ## Scatter-Gather Builder (For Chained Transfers)
+//!
+//! Use [`ScatterGatherBuilder`] for complex multi-segment transfers:
+//!
+//! ```no_run
+//! # use embassy_mcxa::dma::{DmaChannel, ScatterGatherBuilder};
+//! # let dma_ch = DmaChannel::new(p.DMA_CH0);
+//! let mut builder = ScatterGatherBuilder::<u32>::new();
+//! builder.add_transfer(&src1, &mut dst1);
+//! builder.add_transfer(&src2, &mut dst2);
+//!
+//! let transfer = unsafe { builder.build(&dma_ch).unwrap() };
+//! transfer.await;
+//! ```
+//!
+//! ## Direct TCD Access (For Advanced Use Cases)
+//!
+//! For full control, use the channel's `tcd()` method to access TCD registers directly.
+//! See the `dma_*` examples for patterns.
+//!
+//! # Example
+//!
+//! ```no_run
+//! use embassy_mcxa::dma::{DmaChannel, TransferOptions, Direction};
+//!
+//! let dma_ch = DmaChannel::new(p.DMA_CH0);
+//! // Configure and trigger a transfer...
+//! ```
+
+use core::future::Future;
+use core::marker::PhantomData;
+use core::pin::Pin;
+use core::ptr::NonNull;
+use core::sync::atomic::{AtomicUsize, Ordering, fence};
+use core::task::{Context, Poll};
+
+use embassy_hal_internal::PeripheralType;
+use embassy_sync::waitqueue::AtomicWaker;
+
+use crate::clocks::Gate;
+use crate::pac;
+use crate::pac::Interrupt;
+use crate::peripherals::DMA0;
+
+/// Initialize DMA controller (clock enabled, reset released, controller configured).
+///
+/// This function is intended to be called ONCE during HAL initialization (`hal::init()`).
+///
+/// The function enables the DMA0 clock, releases reset, and configures the controller
+/// for normal operation with round-robin arbitration.
+pub(crate) fn init() {
+    unsafe {
+        // Enable DMA0 clock and release reset
+        DMA0::enable_clock();
+        DMA0::release_reset();
+
+        // Configure DMA controller
+        let dma = &(*pac::Dma0::ptr());
+        dma.mp_csr().modify(|_, w| {
+            w.edbg()
+                .enable()
+                .erca()
+                .enable()
+                .halt()
+                .normal_operation()
+                .gclc()
+                .available()
+                .gmrc()
+                .available()
+        });
+    }
+}
+
+// ============================================================================
+// Phase 1: Foundation Types (Embassy-aligned)
+// ============================================================================
+
+/// DMA transfer direction.
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Direction {
+    /// Transfer from memory to memory.
+    MemoryToMemory,
+    /// Transfer from memory to a peripheral register.
+    MemoryToPeripheral,
+    /// Transfer from a peripheral register to memory.
+    PeripheralToMemory,
+}
+
+/// DMA transfer priority.
+#[derive(Debug, Copy, Clone, PartialEq, Eq, Default)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Priority {
+    /// Low priority (channel priority 7).
+    Low,
+    /// Medium priority (channel priority 4).
+    Medium,
+    /// High priority (channel priority 1).
+    #[default]
+    High,
+    /// Highest priority (channel priority 0).
+    Highest,
+}
+
+impl Priority {
+    /// Convert to hardware priority value (0 = highest, 7 = lowest).
+    pub fn to_hw_priority(self) -> u8 {
+        match self {
+            Priority::Low => 7,
+            Priority::Medium => 4,
+            Priority::High => 1,
+            Priority::Highest => 0,
+        }
+    }
+}
+
+/// DMA transfer data width.
+#[derive(Debug, Copy, Clone, PartialEq, Eq, Default)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum WordSize {
+    /// 8-bit (1 byte) transfers.
+    OneByte,
+    /// 16-bit (2 byte) transfers.
+    TwoBytes,
+    /// 32-bit (4 byte) transfers.
+    #[default]
+    FourBytes,
+}
+
+impl WordSize {
+    /// Size in bytes.
+    pub const fn bytes(self) -> usize {
+        match self {
+            WordSize::OneByte => 1,
+            WordSize::TwoBytes => 2,
+            WordSize::FourBytes => 4,
+        }
+    }
+
+    /// Convert to hardware SSIZE/DSIZE field value.
+    pub const fn to_hw_size(self) -> u8 {
+        match self {
+            WordSize::OneByte => 0,
+            WordSize::TwoBytes => 1,
+            WordSize::FourBytes => 2,
+        }
+    }
+
+    /// Create from byte width (1, 2, or 4).
+    pub const fn from_bytes(bytes: u8) -> Option<Self> {
+        match bytes {
+            1 => Some(WordSize::OneByte),
+            2 => Some(WordSize::TwoBytes),
+            4 => Some(WordSize::FourBytes),
+            _ => None,
+        }
+    }
+}
+
+/// Trait for types that can be transferred via DMA.
+///
+/// This provides compile-time type safety for DMA transfers.
+pub trait Word: Copy + 'static {
+    /// The word size for this type.
+    fn size() -> WordSize;
+}
+
+impl Word for u8 {
+    fn size() -> WordSize {
+        WordSize::OneByte
+    }
+}
+
+impl Word for u16 {
+    fn size() -> WordSize {
+        WordSize::TwoBytes
+    }
+}
+
+impl Word for u32 {
+    fn size() -> WordSize {
+        WordSize::FourBytes
+    }
+}
+
+/// DMA transfer options.
+///
+/// This struct configures various aspects of a DMA transfer.
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub struct TransferOptions {
+    /// Transfer priority.
+    pub priority: Priority,
+    /// Enable circular (continuous) mode.
+    ///
+    /// When enabled, the transfer repeats automatically after completing.
+    pub circular: bool,
+    /// Enable interrupt on half transfer complete.
+    pub half_transfer_interrupt: bool,
+    /// Enable interrupt on transfer complete.
+    pub complete_transfer_interrupt: bool,
+}
+
+impl Default for TransferOptions {
+    fn default() -> Self {
+        Self {
+            priority: Priority::High,
+            circular: false,
+            half_transfer_interrupt: false,
+            complete_transfer_interrupt: true,
+        }
+    }
+}
+
+/// DMA error types.
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    /// The DMA controller reported a bus error.
+    BusError,
+    /// The transfer was aborted.
+    Aborted,
+    /// Configuration error (e.g., invalid parameters).
+    Configuration,
+    /// Buffer overrun (for ring buffers).
+    Overrun,
+}
+
+/// Whether to enable the major loop completion interrupt.
+///
+/// This enum provides better readability than a boolean parameter
+/// for functions that configure DMA interrupt behavior.
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum EnableInterrupt {
+    /// Enable the interrupt on major loop completion.
+    Yes,
+    /// Do not enable the interrupt.
+    No,
+}
+
+// ============================================================================
+// DMA Constants
+// ============================================================================
+
+/// Maximum bytes per DMA transfer (eDMA4 CITER/BITER are 15-bit fields).
+///
+/// This is a hardware limitation of the eDMA4 controller. Transfers larger
+/// than this must be split into multiple DMA operations.
+pub const DMA_MAX_TRANSFER_SIZE: usize = 0x7FFF;
+
+// ============================================================================
+// DMA Request Source Types (Type-Safe API)
+// ============================================================================
+
+/// Trait for type-safe DMA request sources.
+///
+/// Each peripheral that can trigger DMA requests implements this trait
+/// with marker types that encode the correct request source number at
+/// compile time. This prevents using the wrong request source for a
+/// peripheral.
+///
+/// # Example
+///
+/// ```ignore
+/// // The LPUART2 RX request source is automatically derived from the type:
+/// channel.set_request_source::<Lpuart2RxRequest>();
+/// ```
+///
+/// This trait is sealed and cannot be implemented outside this crate.
+#[allow(private_bounds)]
+pub trait DmaRequest: sealed::SealedDmaRequest {
+    /// The hardware request source number for the DMA mux.
+    const REQUEST_NUMBER: u8;
+}
+
+/// Macro to define a DMA request type.
+///
+/// Creates a zero-sized marker type that implements `DmaRequest` with
+/// the specified request number.
+macro_rules! define_dma_request {
+    ($(#[$meta:meta])* $name:ident = $num:expr) => {
+        $(#[$meta])*
+        #[derive(Debug, Copy, Clone)]
+        pub struct $name;
+
+        impl sealed::SealedDmaRequest for $name {}
+
+        impl DmaRequest for $name {
+            const REQUEST_NUMBER: u8 = $num;
+        }
+    };
+}
+
+// LPUART DMA request sources (from MCXA276 reference manual Table 4-8)
+define_dma_request!(
+    /// DMA request source for LPUART0 RX.
+    Lpuart0RxRequest = 21
+);
+define_dma_request!(
+    /// DMA request source for LPUART0 TX.
+    Lpuart0TxRequest = 22
+);
+define_dma_request!(
+    /// DMA request source for LPUART1 RX.
+    Lpuart1RxRequest = 23
+);
+define_dma_request!(
+    /// DMA request source for LPUART1 TX.
+    Lpuart1TxRequest = 24
+);
+define_dma_request!(
+    /// DMA request source for LPUART2 RX.
+    Lpuart2RxRequest = 25
+);
+define_dma_request!(
+    /// DMA request source for LPUART2 TX.
+    Lpuart2TxRequest = 26
+);
+define_dma_request!(
+    /// DMA request source for LPUART3 RX.
+    Lpuart3RxRequest = 27
+);
+define_dma_request!(
+    /// DMA request source for LPUART3 TX.
+    Lpuart3TxRequest = 28
+);
+define_dma_request!(
+    /// DMA request source for LPUART4 RX.
+    Lpuart4RxRequest = 29
+);
+define_dma_request!(
+    /// DMA request source for LPUART4 TX.
+    Lpuart4TxRequest = 30
+);
+define_dma_request!(
+    /// DMA request source for LPUART5 RX.
+    Lpuart5RxRequest = 31
+);
+define_dma_request!(
+    /// DMA request source for LPUART5 TX.
+    Lpuart5TxRequest = 32
+);
+
+// ============================================================================
+// Channel Trait (Sealed Pattern)
+// ============================================================================
+
+mod sealed {
+    use crate::pac::Interrupt;
+
+    /// Sealed trait for DMA channels.
+    pub trait SealedChannel {
+        /// Zero-based channel index into the TCD array.
+        fn index(&self) -> usize;
+        /// Interrupt vector for this channel.
+        fn interrupt(&self) -> Interrupt;
+    }
+
+    /// Sealed trait for DMA request sources.
+    pub trait SealedDmaRequest {}
+}
+
+/// Marker trait implemented by HAL peripheral tokens that map to a DMA0
+/// channel backed by one EDMA_0_TCD0 TCD slot.
+///
+/// This trait is sealed and cannot be implemented outside this crate.
+#[allow(private_bounds)]
+pub trait Channel: sealed::SealedChannel + PeripheralType + Into<AnyChannel> + 'static {
+    /// Zero-based channel index into the TCD array.
+    const INDEX: usize;
+    /// Interrupt vector for this channel.
+    const INTERRUPT: Interrupt;
+}
+
+/// Type-erased DMA channel.
+///
+/// This allows storing DMA channels in a uniform way regardless of their
+/// concrete type, useful for async transfer futures and runtime channel selection.
+#[derive(Debug, Clone, Copy)]
+pub struct AnyChannel {
+    index: usize,
+    interrupt: Interrupt,
+}
+
+impl AnyChannel {
+    /// Get the channel index.
+    #[inline]
+    pub const fn index(&self) -> usize {
+        self.index
+    }
+
+    /// Get the channel interrupt.
+    #[inline]
+    pub const fn interrupt(&self) -> Interrupt {
+        self.interrupt
+    }
+
+    /// Get a reference to the TCD register block for this channel.
+    ///
+    /// This steals the eDMA pointer internally since MCXA276 has only one eDMA instance.
+    #[inline]
+    fn tcd(&self) -> &'static pac::edma_0_tcd0::Tcd {
+        // Safety: MCXA276 has a single eDMA instance, and we're only accessing
+        // the TCD for this specific channel
+        let edma = unsafe { &*pac::Edma0Tcd0::ptr() };
+        edma.tcd(self.index)
+    }
+
+    /// Check if the channel's DONE flag is set.
+    pub fn is_done(&self) -> bool {
+        self.tcd().ch_csr().read().done().bit_is_set()
+    }
+
+    /// Get the waker for this channel.
+    pub fn waker(&self) -> &'static AtomicWaker {
+        &STATES[self.index].waker
+    }
+}
+
+impl sealed::SealedChannel for AnyChannel {
+    fn index(&self) -> usize {
+        self.index
+    }
+
+    fn interrupt(&self) -> Interrupt {
+        self.interrupt
+    }
+}
+
+/// Macro to implement Channel trait for a peripheral.
+macro_rules! impl_channel {
+    ($peri:ident, $index:expr, $irq:ident) => {
+        impl sealed::SealedChannel for crate::peripherals::$peri {
+            fn index(&self) -> usize {
+                $index
+            }
+
+            fn interrupt(&self) -> Interrupt {
+                Interrupt::$irq
+            }
+        }
+
+        impl Channel for crate::peripherals::$peri {
+            const INDEX: usize = $index;
+            const INTERRUPT: Interrupt = Interrupt::$irq;
+        }
+
+        impl From<crate::peripherals::$peri> for AnyChannel {
+            fn from(_: crate::peripherals::$peri) -> Self {
+                AnyChannel {
+                    index: $index,
+                    interrupt: Interrupt::$irq,
+                }
+            }
+        }
+    };
+}
+
+impl_channel!(DMA_CH0, 0, DMA_CH0);
+impl_channel!(DMA_CH1, 1, DMA_CH1);
+impl_channel!(DMA_CH2, 2, DMA_CH2);
+impl_channel!(DMA_CH3, 3, DMA_CH3);
+impl_channel!(DMA_CH4, 4, DMA_CH4);
+impl_channel!(DMA_CH5, 5, DMA_CH5);
+impl_channel!(DMA_CH6, 6, DMA_CH6);
+impl_channel!(DMA_CH7, 7, DMA_CH7);
+
+/// Strongly-typed handle to a DMA0 channel.
+///
+/// The lifetime of this value is tied to the unique peripheral token
+/// supplied by `embassy_hal_internal::peripherals!`, so safe code cannot
+/// create two `DmaChannel` instances for the same hardware channel.
+pub struct DmaChannel<C: Channel> {
+    _ch: core::marker::PhantomData<C>,
+}
+
+// ============================================================================
+// DMA Transfer Methods - API Overview
+// ============================================================================
+//
+// The DMA API provides two categories of methods for configuring transfers:
+//
+// ## 1. Async Methods (Return `Transfer` Future)
+//
+// These methods return a [`Transfer`] Future that must be `.await`ed:
+//
+// - [`write()`](DmaChannel::write) - Memory-to-peripheral using default eDMA TCD block
+// - [`read()`](DmaChannel::read) - Peripheral-to-memory using default eDMA TCD block
+// - [`write_to_peripheral()`](DmaChannel::write_to_peripheral) - Memory-to-peripheral with custom eDMA TCD block
+// - [`read_from_peripheral()`](DmaChannel::read_from_peripheral) - Peripheral-to-memory with custom eDMA TCD block
+// - [`mem_to_mem()`](DmaChannel::mem_to_mem) - Memory-to-memory using default eDMA TCD block
+//
+// The `Transfer` manages the DMA lifecycle automatically:
+// - Enables channel request
+// - Waits for completion via async/await
+// - Cleans up on completion
+//
+// **Important:** `Transfer::Drop` aborts the transfer if dropped before completion.
+// This means you MUST `.await` the Transfer or it will be aborted when it goes out of scope.
+//
+// **Use case:** When you want to use async/await and let the Transfer handle lifecycle management.
+//
+// ## 2. Setup Methods (Configure TCD Only)
+//
+// These methods configure the TCD but do NOT return a `Transfer`:
+//
+// - [`setup_write()`](DmaChannel::setup_write) - Memory-to-peripheral using default eDMA TCD block
+// - [`setup_read()`](DmaChannel::setup_read) - Peripheral-to-memory using default eDMA TCD block
+// - [`setup_write_to_peripheral()`](DmaChannel::setup_write_to_peripheral) - Memory-to-peripheral with custom eDMA TCD block
+// - [`setup_read_from_peripheral()`](DmaChannel::setup_read_from_peripheral) - Peripheral-to-memory with custom eDMA TCD block
+//
+// The caller is responsible for the complete DMA lifecycle:
+// 1. Call [`enable_request()`](DmaChannel::enable_request) to start the transfer
+// 2. Poll [`is_done()`](DmaChannel::is_done) or use interrupts to detect completion
+// 3. Call [`disable_request()`](DmaChannel::disable_request), [`clear_done()`](DmaChannel::clear_done),
+//    [`clear_interrupt()`](DmaChannel::clear_interrupt) for cleanup
+//
+// **Use case:** Peripheral drivers (like LPUART) that need fine-grained control over
+// DMA setup before starting a `Transfer`.
+//
+// ============================================================================
+
+impl<C: Channel> DmaChannel<C> {
+    /// Wrap a DMA channel token (takes ownership of the Peri wrapper).
+    ///
+    /// Note: DMA is initialized during `hal::init()` via `dma::init()`.
+    #[inline]
+    pub fn new(_ch: embassy_hal_internal::Peri<'_, C>) -> Self {
+        unsafe {
+            cortex_m::peripheral::NVIC::unmask(C::INTERRUPT);
+        }
+        Self {
+            _ch: core::marker::PhantomData,
+        }
+    }
+
+    /// Channel index in the EDMA_0_TCD0 array.
+    #[inline]
+    pub const fn index(&self) -> usize {
+        C::INDEX
+    }
+
+    /// Convert this typed channel into a type-erased `AnyChannel`.
+    #[inline]
+    pub fn into_any(self) -> AnyChannel {
+        AnyChannel {
+            index: C::INDEX,
+            interrupt: C::INTERRUPT,
+        }
+    }
+
+    /// Get a reference to the type-erased channel info.
+    #[inline]
+    pub fn as_any(&self) -> AnyChannel {
+        AnyChannel {
+            index: C::INDEX,
+            interrupt: C::INTERRUPT,
+        }
+    }
+
+    /// Return a reference to the underlying TCD register block.
+    ///
+    /// This steals the eDMA pointer internally since MCXA276 has only one eDMA instance.
+    ///
+    /// # Note
+    ///
+    /// This is exposed for advanced use cases that need direct TCD access.
+    /// For most use cases, prefer the higher-level transfer methods.
+    #[inline]
+    pub fn tcd(&self) -> &'static pac::edma_0_tcd0::Tcd {
+        // Safety: MCXA276 has a single eDMA instance
+        let edma = unsafe { &*pac::Edma0Tcd0::ptr() };
+        edma.tcd(C::INDEX)
+    }
+
+    fn clear_tcd(t: &'static pac::edma_0_tcd0::Tcd) {
+        // Full TCD reset following NXP SDK pattern (EDMA_TcdResetExt).
+        // Reset ALL TCD registers to 0 to clear any stale configuration from
+        // previous transfers. This is critical when reusing a channel.
+        t.tcd_saddr().write(|w| unsafe { w.saddr().bits(0) });
+        t.tcd_soff().write(|w| unsafe { w.soff().bits(0) });
+        t.tcd_attr().write(|w| unsafe { w.bits(0) });
+        t.tcd_nbytes_mloffno().write(|w| unsafe { w.nbytes().bits(0) });
+        t.tcd_slast_sda().write(|w| unsafe { w.slast_sda().bits(0) });
+        t.tcd_daddr().write(|w| unsafe { w.daddr().bits(0) });
+        t.tcd_doff().write(|w| unsafe { w.doff().bits(0) });
+        t.tcd_citer_elinkno().write(|w| unsafe { w.bits(0) });
+        t.tcd_dlast_sga().write(|w| unsafe { w.dlast_sga().bits(0) });
+        t.tcd_csr().write(|w| unsafe { w.bits(0) }); // Clear CSR completely
+        t.tcd_biter_elinkno().write(|w| unsafe { w.bits(0) });
+    }
+
+    #[inline]
+    fn set_major_loop_ct_elinkno(t: &'static pac::edma_0_tcd0::Tcd, count: u16) {
+        t.tcd_biter_elinkno().write(|w| unsafe { w.biter().bits(count) });
+        t.tcd_citer_elinkno().write(|w| unsafe { w.citer().bits(count) });
+    }
+
+    #[inline]
+    fn set_minor_loop_ct_no_offsets(t: &'static pac::edma_0_tcd0::Tcd, count: u32) {
+        t.tcd_nbytes_mloffno().write(|w| unsafe { w.nbytes().bits(count) });
+    }
+
+    #[inline]
+    fn set_no_final_adjustments(t: &'static pac::edma_0_tcd0::Tcd) {
+        // No source/dest adjustment after major loop
+        t.tcd_slast_sda().write(|w| unsafe { w.slast_sda().bits(0) });
+        t.tcd_dlast_sga().write(|w| unsafe { w.dlast_sga().bits(0) });
+    }
+
+    #[inline]
+    fn set_source_ptr<T>(t: &'static pac::edma_0_tcd0::Tcd, p: *const T) {
+        t.tcd_saddr().write(|w| unsafe { w.saddr().bits(p as u32) });
+    }
+
+    #[inline]
+    fn set_source_increment(t: &'static pac::edma_0_tcd0::Tcd, sz: WordSize) {
+        t.tcd_soff().write(|w| unsafe { w.soff().bits(sz.bytes() as u16) });
+    }
+
+    #[inline]
+    fn set_source_fixed(t: &'static pac::edma_0_tcd0::Tcd) {
+        t.tcd_soff().write(|w| unsafe { w.soff().bits(0) });
+    }
+
+    #[inline]
+    fn set_dest_ptr<T>(t: &'static pac::edma_0_tcd0::Tcd, p: *mut T) {
+        t.tcd_daddr().write(|w| unsafe { w.daddr().bits(p as u32) });
+    }
+
+    #[inline]
+    fn set_dest_increment(t: &'static pac::edma_0_tcd0::Tcd, sz: WordSize) {
+        t.tcd_doff().write(|w| unsafe { w.doff().bits(sz.bytes() as u16) });
+    }
+
+    #[inline]
+    fn set_dest_fixed(t: &'static pac::edma_0_tcd0::Tcd) {
+        t.tcd_doff().write(|w| unsafe { w.doff().bits(0) });
+    }
+
+    #[inline]
+    fn set_even_transfer_size(t: &'static pac::edma_0_tcd0::Tcd, sz: WordSize) {
+        let hw_size = sz.to_hw_size();
+        t.tcd_attr()
+            .write(|w| unsafe { w.ssize().bits(hw_size).dsize().bits(hw_size) });
+    }
+
+    #[inline]
+    fn reset_channel_state(t: &'static pac::edma_0_tcd0::Tcd) {
+        // CSR: Resets to all zeroes (disabled), "done" is cleared by writing 1
+        t.ch_csr().write(|w| w.done().clear_bit_by_one());
+        // ES: Resets to all zeroes (disabled), "err" is cleared by writing 1
+        t.ch_es().write(|w| w.err().clear_bit_by_one());
+        // INT: Resets to all zeroes (disabled), "int" is cleared by writing 1
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+    }
+
+    /// Start an async transfer.
+    ///
+    /// The channel must already be configured. This enables the channel
+    /// request and returns a `Transfer` future that resolves when the
+    /// DMA transfer completes.
+    ///
+    /// # Safety
+    ///
+    /// The caller must ensure the DMA channel has been properly configured
+    /// and that source/destination buffers remain valid for the duration
+    /// of the transfer.
+    pub unsafe fn start_transfer(&self) -> Transfer<'_> {
+        // Clear any previous DONE/INT flags
+        let t = self.tcd();
+        t.ch_csr().modify(|_, w| w.done().clear_bit_by_one());
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+
+        // Enable the channel request
+        t.ch_csr().modify(|_, w| w.erq().enable());
+
+        Transfer::new(self.as_any())
+    }
+
+    // ========================================================================
+    // Type-Safe Transfer Methods (Embassy-style API)
+    // ========================================================================
+
+    /// Perform a memory-to-memory DMA transfer (simplified API).
+    ///
+    /// This is a type-safe wrapper that uses the `Word` trait to determine
+    /// the correct transfer width automatically. Uses the global eDMA TCD
+    /// register accessor internally.
+    ///
+    /// # Arguments
+    ///
+    /// * `src` - Source buffer
+    /// * `dst` - Destination buffer (must be at least as large as src)
+    /// * `options` - Transfer configuration options
+    ///
+    /// # Safety
+    ///
+    /// The source and destination buffers must remain valid for the
+    /// duration of the transfer.
+    pub fn mem_to_mem<W: Word>(
+        &self,
+        src: &[W],
+        dst: &mut [W],
+        options: TransferOptions,
+    ) -> Result<Transfer<'_>, Error> {
+        let mut invalid = false;
+        invalid |= src.is_empty();
+        invalid |= src.len() > dst.len();
+        invalid |= src.len() > 0x7fff;
+        if invalid {
+            return Err(Error::Configuration);
+        }
+
+        let size = W::size();
+        let byte_count = (src.len() * size.bytes()) as u32;
+
+        let t = self.tcd();
+
+        // Reset channel state - clear DONE, disable requests, clear errors
+        Self::reset_channel_state(t);
+
+        // Memory barrier to ensure channel state is fully reset before touching TCD
+        cortex_m::asm::dsb();
+
+        Self::clear_tcd(t);
+
+        // Memory barrier after TCD reset
+        cortex_m::asm::dsb();
+
+        // Note: Priority is managed by round-robin arbitration (set in init())
+        // Per-channel priority can be configured via ch_pri() if needed
+
+        // Now configure the new transfer
+
+        // Source address and increment
+        Self::set_source_ptr(t, src.as_ptr());
+        Self::set_source_increment(t, size);
+
+        // Destination address and increment
+        Self::set_dest_ptr(t, dst.as_mut_ptr());
+        Self::set_dest_increment(t, size);
+
+        // Transfer attributes (size)
+        Self::set_even_transfer_size(t, size);
+
+        // Minor loop: transfer all bytes in one minor loop
+        Self::set_minor_loop_ct_no_offsets(t, byte_count);
+
+        // No source/dest adjustment after major loop
+        Self::set_no_final_adjustments(t);
+
+        // Major loop count = 1 (single major loop)
+        // Write BITER first, then CITER (CITER must match BITER at start)
+        Self::set_major_loop_ct_elinkno(t, 1);
+
+        // Memory barrier before setting START
+        cortex_m::asm::dsb();
+
+        // Control/status: interrupt on major complete, start
+        // Write this last after all other TCD registers are configured
+        let int_major = options.complete_transfer_interrupt;
+        t.tcd_csr().write(|w| {
+            w.intmajor()
+                .bit(int_major)
+                .inthalf()
+                .bit(options.half_transfer_interrupt)
+                .dreq()
+                .set_bit() // Auto-disable request after major loop
+                .start()
+                .set_bit() // Start the channel
+        });
+
+        Ok(Transfer::new(self.as_any()))
+    }
+
+    /// Fill a memory buffer with a pattern value (memset).
+    ///
+    /// This performs a DMA transfer where the source address remains fixed
+    /// (pattern value) while the destination address increments through the buffer.
+    /// It's useful for quickly filling large memory regions with a constant value.
+    ///
+    /// # Arguments
+    ///
+    /// * `pattern` - Reference to the pattern value (will be read repeatedly)
+    /// * `dst` - Destination buffer to fill
+    /// * `options` - Transfer configuration options
+    ///
+    /// # Example
+    ///
+    /// ```no_run
+    /// use embassy_mcxa::dma::{DmaChannel, TransferOptions};
+    ///
+    /// let dma_ch = DmaChannel::new(p.DMA_CH0);
+    /// let pattern: u32 = 0xDEADBEEF;
+    /// let mut buffer = [0u32; 256];
+    ///
+    /// unsafe {
+    ///     dma_ch.memset(&pattern, &mut buffer, TransferOptions::default()).await;
+    /// }
+    /// // buffer is now filled with 0xDEADBEEF
+    /// ```
+    ///
+    pub fn memset<W: Word>(&self, pattern: &W, dst: &mut [W], options: TransferOptions) -> Transfer<'_> {
+        assert!(!dst.is_empty());
+        assert!(dst.len() <= 0x7fff);
+
+        let size = W::size();
+        let byte_size = size.bytes();
+        // Total bytes to transfer - all in one minor loop for software-triggered transfers
+        let total_bytes = (dst.len() * byte_size) as u32;
+
+        let t = self.tcd();
+
+        // Reset channel state - clear DONE, disable requests, clear errors
+        Self::reset_channel_state(t);
+
+        // Memory barrier to ensure channel state is fully reset before touching TCD
+        cortex_m::asm::dsb();
+
+        Self::clear_tcd(t);
+
+        // Memory barrier after TCD reset
+        cortex_m::asm::dsb();
+
+        // Now configure the new transfer
+        //
+        // For software-triggered memset, we use a SINGLE minor loop that transfers
+        // all bytes at once. The source address stays fixed (SOFF=0) while the
+        // destination increments (DOFF=byte_size). The eDMA will read from the
+        // same source address for each destination word.
+        //
+        // This is necessary because the START bit only triggers ONE minor loop
+        // iteration. Using CITER>1 with software trigger would require multiple
+        // START triggers.
+
+        // Source: pattern address, fixed (soff=0)
+        Self::set_source_ptr(t, pattern);
+        Self::set_source_fixed(t);
+
+        // Destination: memory buffer, incrementing by word size
+        Self::set_dest_ptr(t, dst.as_mut_ptr());
+        Self::set_dest_increment(t, size);
+
+        // Transfer attributes - source and dest are same word size
+        Self::set_even_transfer_size(t, size);
+
+        // Minor loop: transfer ALL bytes in one minor loop (like mem_to_mem)
+        // This allows the entire transfer to complete with a single START trigger
+        Self::set_minor_loop_ct_no_offsets(t, total_bytes);
+
+        // No address adjustment after major loop
+        Self::set_no_final_adjustments(t);
+
+        // Major loop count = 1 (single major loop, all data in minor loop)
+        // Write BITER first, then CITER (CITER must match BITER at start)
+        Self::set_major_loop_ct_elinkno(t, 1);
+
+        // Memory barrier before setting START
+        cortex_m::asm::dsb();
+
+        // Control/status: interrupt on major complete, start immediately
+        // Write this last after all other TCD registers are configured
+        let int_major = options.complete_transfer_interrupt;
+        t.tcd_csr().write(|w| {
+            w.intmajor()
+                .bit(int_major)
+                .inthalf()
+                .bit(options.half_transfer_interrupt)
+                .dreq()
+                .set_bit() // Auto-disable request after major loop
+                .start()
+                .set_bit() // Start the channel
+        });
+
+        Transfer::new(self.as_any())
+    }
+
+    /// Write data from memory to a peripheral register.
+    ///
+    /// The destination address remains fixed (peripheral register) while
+    /// the source address increments through the buffer.
+    ///
+    /// # Arguments
+    ///
+    /// * `buf` - Source buffer to write from
+    /// * `peri_addr` - Peripheral register address
+    /// * `options` - Transfer configuration options
+    ///
+    /// # Safety
+    ///
+    /// - The buffer must remain valid for the duration of the transfer.
+    /// - The peripheral address must be valid for writes.
+    pub unsafe fn write<W: Word>(&self, buf: &[W], peri_addr: *mut W, options: TransferOptions) -> Transfer<'_> {
+        self.write_to_peripheral(buf, peri_addr, options)
+    }
+
+    /// Configure a memory-to-peripheral DMA transfer without starting it.
+    ///
+    /// This is a convenience wrapper around [`setup_write_to_peripheral()`](Self::setup_write_to_peripheral)
+    /// that uses the default eDMA TCD register block.
+    ///
+    /// This method configures the TCD but does NOT return a `Transfer`. The caller
+    /// is responsible for the complete DMA lifecycle:
+    /// 1. Call [`enable_request()`](Self::enable_request) to start the transfer
+    /// 2. Poll [`is_done()`](Self::is_done) or use interrupts to detect completion
+    /// 3. Call [`disable_request()`](Self::disable_request), [`clear_done()`](Self::clear_done),
+    ///    [`clear_interrupt()`](Self::clear_interrupt) for cleanup
+    ///
+    /// # Example
+    ///
+    /// ```no_run
+    /// # use embassy_mcxa::dma::DmaChannel;
+    /// # let dma_ch = DmaChannel::new(p.DMA_CH0);
+    /// # let uart_tx_addr = 0x4000_0000 as *mut u8;
+    /// let data = [0x48, 0x65, 0x6c, 0x6c, 0x6f]; // "Hello"
+    ///
+    /// unsafe {
+    ///     // Configure the transfer
+    ///     dma_ch.setup_write(&data, uart_tx_addr, EnableInterrupt::Yes);
+    ///
+    ///     // Start when peripheral is ready
+    ///     dma_ch.enable_request();
+    ///
+    ///     // Wait for completion (or use interrupt)
+    ///     while !dma_ch.is_done() {}
+    ///
+    ///     // Clean up
+    ///     dma_ch.clear_done();
+    ///     dma_ch.clear_interrupt();
+    /// }
+    /// ```
+    ///
+    /// # Arguments
+    ///
+    /// * `buf` - Source buffer to write from
+    /// * `peri_addr` - Peripheral register address
+    /// * `enable_interrupt` - Whether to enable interrupt on completion
+    ///
+    /// # Safety
+    ///
+    /// - The buffer must remain valid for the duration of the transfer.
+    /// - The peripheral address must be valid for writes.
+    pub unsafe fn setup_write<W: Word>(&self, buf: &[W], peri_addr: *mut W, enable_interrupt: EnableInterrupt) {
+        self.setup_write_to_peripheral(buf, peri_addr, enable_interrupt)
+    }
+
+    /// Write data from memory to a peripheral register.
+    ///
+    /// The destination address remains fixed (peripheral register) while
+    /// the source address increments through the buffer.
+    ///
+    /// # Arguments
+    ///
+    /// * `buf` - Source buffer to write from
+    /// * `peri_addr` - Peripheral register address
+    /// * `options` - Transfer configuration options
+    ///
+    /// # Safety
+    ///
+    /// - The buffer must remain valid for the duration of the transfer.
+    /// - The peripheral address must be valid for writes.
+    pub unsafe fn write_to_peripheral<W: Word>(
+        &self,
+        buf: &[W],
+        peri_addr: *mut W,
+        options: TransferOptions,
+    ) -> Transfer<'_> {
+        assert!(!buf.is_empty());
+        assert!(buf.len() <= 0x7fff);
+
+        let size = W::size();
+        let byte_size = size.bytes();
+
+        let t = self.tcd();
+
+        // Reset channel state
+        Self::reset_channel_state(t);
+
+        // Addresses
+        Self::set_source_ptr(t, buf.as_ptr());
+        Self::set_dest_ptr(t, peri_addr);
+
+        // Offsets: Source increments, Dest fixed
+        Self::set_source_increment(t, size);
+        Self::set_dest_fixed(t);
+
+        // Attributes: set size and explicitly disable modulo
+        Self::set_even_transfer_size(t, size);
+
+        // Minor loop: transfer one word per request (match old: only set nbytes)
+        Self::set_minor_loop_ct_no_offsets(t, byte_size as u32);
+
+        // No final adjustments
+        Self::set_no_final_adjustments(t);
+
+        // Major loop count = number of words
+        let count = buf.len() as u16;
+        Self::set_major_loop_ct_elinkno(t, count);
+
+        // CSR: interrupt on major loop complete and auto-clear ERQ
+        t.tcd_csr().write(|w| {
+            let w = if options.complete_transfer_interrupt {
+                w.intmajor().enable()
+            } else {
+                w.intmajor().disable()
+            };
+            w.inthalf()
+                .disable()
+                .dreq()
+                .erq_field_clear() // Disable request when done
+                .esg()
+                .normal_format()
+                .majorelink()
+                .disable()
+                .eeop()
+                .disable()
+                .esda()
+                .disable()
+                .bwc()
+                .no_stall()
+        });
+
+        // Ensure all TCD writes have completed before DMA engine reads them
+        cortex_m::asm::dsb();
+
+        Transfer::new(self.as_any())
+    }
+
+    /// Read data from a peripheral register to memory.
+    ///
+    /// The source address remains fixed (peripheral register) while
+    /// the destination address increments through the buffer.
+    ///
+    /// # Arguments
+    ///
+    /// * `peri_addr` - Peripheral register address
+    /// * `buf` - Destination buffer to read into
+    /// * `options` - Transfer configuration options
+    ///
+    /// # Safety
+    ///
+    /// - The buffer must remain valid for the duration of the transfer.
+    /// - The peripheral address must be valid for reads.
+    pub unsafe fn read<W: Word>(&self, peri_addr: *const W, buf: &mut [W], options: TransferOptions) -> Transfer<'_> {
+        self.read_from_peripheral(peri_addr, buf, options)
+    }
+
+    /// Configure a peripheral-to-memory DMA transfer without starting it.
+    ///
+    /// This is a convenience wrapper around [`setup_read_from_peripheral()`](Self::setup_read_from_peripheral)
+    /// that uses the default eDMA TCD register block.
+    ///
+    /// This method configures the TCD but does NOT return a `Transfer`. The caller
+    /// is responsible for the complete DMA lifecycle:
+    /// 1. Call [`enable_request()`](Self::enable_request) to start the transfer
+    /// 2. Poll [`is_done()`](Self::is_done) or use interrupts to detect completion
+    /// 3. Call [`disable_request()`](Self::disable_request), [`clear_done()`](Self::clear_done),
+    ///    [`clear_interrupt()`](Self::clear_interrupt) for cleanup
+    ///
+    /// # Example
+    ///
+    /// ```no_run
+    /// # use embassy_mcxa::dma::DmaChannel;
+    /// # let dma_ch = DmaChannel::new(p.DMA_CH0);
+    /// # let uart_rx_addr = 0x4000_0000 as *const u8;
+    /// let mut buf = [0u8; 32];
+    ///
+    /// unsafe {
+    ///     // Configure the transfer
+    ///     dma_ch.setup_read(uart_rx_addr, &mut buf, EnableInterrupt::Yes);
+    ///
+    ///     // Start when peripheral is ready
+    ///     dma_ch.enable_request();
+    ///
+    ///     // Wait for completion (or use interrupt)
+    ///     while !dma_ch.is_done() {}
+    ///
+    ///     // Clean up
+    ///     dma_ch.clear_done();
+    ///     dma_ch.clear_interrupt();
+    /// }
+    /// // buf now contains received data
+    /// ```
+    ///
+    /// # Arguments
+    ///
+    /// * `peri_addr` - Peripheral register address
+    /// * `buf` - Destination buffer to read into
+    /// * `enable_interrupt` - Whether to enable interrupt on completion
+    ///
+    /// # Safety
+    ///
+    /// - The buffer must remain valid for the duration of the transfer.
+    /// - The peripheral address must be valid for reads.
+    pub unsafe fn setup_read<W: Word>(&self, peri_addr: *const W, buf: &mut [W], enable_interrupt: EnableInterrupt) {
+        self.setup_read_from_peripheral(peri_addr, buf, enable_interrupt)
+    }
+
+    /// Read data from a peripheral register to memory.
+    ///
+    /// The source address remains fixed (peripheral register) while
+    /// the destination address increments through the buffer.
+    ///
+    /// # Arguments
+    ///
+    /// * `peri_addr` - Peripheral register address
+    /// * `buf` - Destination buffer to read into
+    /// * `options` - Transfer configuration options
+    ///
+    /// # Safety
+    ///
+    /// - The buffer must remain valid for the duration of the transfer.
+    /// - The peripheral address must be valid for reads.
+    pub unsafe fn read_from_peripheral<W: Word>(
+        &self,
+        peri_addr: *const W,
+        buf: &mut [W],
+        options: TransferOptions,
+    ) -> Transfer<'_> {
+        assert!(!buf.is_empty());
+        assert!(buf.len() <= 0x7fff);
+
+        let size = W::size();
+        let byte_size = size.bytes();
+
+        let t = self.tcd();
+
+        // Reset channel control/error/interrupt state
+        Self::reset_channel_state(t);
+
+        // Source: peripheral register, fixed
+        Self::set_source_ptr(t, peri_addr);
+        Self::set_source_fixed(t);
+
+        // Destination: memory buffer, incrementing
+        Self::set_dest_ptr(t, buf.as_mut_ptr());
+        Self::set_dest_increment(t, size);
+
+        // Transfer attributes: set size and explicitly disable modulo
+        Self::set_even_transfer_size(t, size);
+
+        // Minor loop: transfer one word per request, no offsets
+        Self::set_minor_loop_ct_no_offsets(t, byte_size as u32);
+
+        // Major loop count = number of words
+        let count = buf.len() as u16;
+        Self::set_major_loop_ct_elinkno(t, count);
+
+        // No address adjustment after major loop
+        Self::set_no_final_adjustments(t);
+
+        // Control/status: interrupt on major complete, auto-clear ERQ when done
+        t.tcd_csr().write(|w| {
+            let w = if options.complete_transfer_interrupt {
+                w.intmajor().enable()
+            } else {
+                w.intmajor().disable()
+            };
+            let w = if options.half_transfer_interrupt {
+                w.inthalf().enable()
+            } else {
+                w.inthalf().disable()
+            };
+            w.dreq()
+                .erq_field_clear() // Disable request when done (important for peripheral DMA)
+                .esg()
+                .normal_format()
+                .majorelink()
+                .disable()
+                .eeop()
+                .disable()
+                .esda()
+                .disable()
+                .bwc()
+                .no_stall()
+        });
+
+        // Ensure all TCD writes have completed before DMA engine reads them
+        cortex_m::asm::dsb();
+
+        Transfer::new(self.as_any())
+    }
+
+    /// Configure a memory-to-peripheral DMA transfer without starting it.
+    ///
+    /// This configures the TCD for a memory-to-peripheral transfer but does NOT
+    /// return a Transfer object. The caller is responsible for:
+    /// 1. Enabling the peripheral's DMA request
+    /// 2. Calling `enable_request()` to start the transfer
+    /// 3. Polling `is_done()` or using interrupts to detect completion
+    /// 4. Calling `disable_request()`, `clear_done()`, `clear_interrupt()` for cleanup
+    ///
+    /// Use this when you need manual control over the DMA lifecycle (e.g., in
+    /// peripheral drivers that have their own completion polling).
+    ///
+    /// # Arguments
+    ///
+    /// * `buf` - Source buffer to write from
+    /// * `peri_addr` - Peripheral register address
+    /// * `enable_interrupt` - Whether to enable interrupt on completion
+    ///
+    /// # Safety
+    ///
+    /// - The buffer must remain valid for the duration of the transfer.
+    /// - The peripheral address must be valid for writes.
+    pub unsafe fn setup_write_to_peripheral<W: Word>(
+        &self,
+        buf: &[W],
+        peri_addr: *mut W,
+        enable_interrupt: EnableInterrupt,
+    ) {
+        assert!(!buf.is_empty());
+        assert!(buf.len() <= 0x7fff);
+
+        let size = W::size();
+        let byte_size = size.bytes();
+
+        let t = self.tcd();
+
+        // Reset channel state
+        Self::reset_channel_state(t);
+
+        // Addresses
+        Self::set_source_ptr(t, buf.as_ptr());
+        Self::set_dest_ptr(t, peri_addr);
+
+        // Offsets: Source increments, Dest fixed
+        Self::set_source_increment(t, size);
+        Self::set_dest_fixed(t);
+
+        // Attributes: set size and explicitly disable modulo
+        Self::set_even_transfer_size(t, size);
+
+        // Minor loop: transfer one word per request
+        Self::set_minor_loop_ct_no_offsets(t, byte_size as u32);
+
+        // No final adjustments
+        Self::set_no_final_adjustments(t);
+
+        // Major loop count = number of words
+        let count = buf.len() as u16;
+        Self::set_major_loop_ct_elinkno(t, count);
+
+        // CSR: optional interrupt on major loop complete and auto-clear ERQ
+        t.tcd_csr().write(|w| {
+            let w = match enable_interrupt {
+                EnableInterrupt::Yes => w.intmajor().enable(),
+                EnableInterrupt::No => w.intmajor().disable(),
+            };
+            w.inthalf()
+                .disable()
+                .dreq()
+                .erq_field_clear()
+                .esg()
+                .normal_format()
+                .majorelink()
+                .disable()
+                .eeop()
+                .disable()
+                .esda()
+                .disable()
+                .bwc()
+                .no_stall()
+        });
+
+        // Ensure all TCD writes have completed before DMA engine reads them
+        cortex_m::asm::dsb();
+    }
+
+    /// Configure a peripheral-to-memory DMA transfer without starting it.
+    ///
+    /// This configures the TCD for a peripheral-to-memory transfer but does NOT
+    /// return a Transfer object. The caller is responsible for:
+    /// 1. Enabling the peripheral's DMA request
+    /// 2. Calling `enable_request()` to start the transfer
+    /// 3. Polling `is_done()` or using interrupts to detect completion
+    /// 4. Calling `disable_request()`, `clear_done()`, `clear_interrupt()` for cleanup
+    ///
+    /// Use this when you need manual control over the DMA lifecycle (e.g., in
+    /// peripheral drivers that have their own completion polling).
+    ///
+    /// # Arguments
+    ///
+    /// * `peri_addr` - Peripheral register address
+    /// * `buf` - Destination buffer to read into
+    /// * `enable_interrupt` - Whether to enable interrupt on completion
+    ///
+    /// # Safety
+    ///
+    /// - The buffer must remain valid for the duration of the transfer.
+    /// - The peripheral address must be valid for reads.
+    pub unsafe fn setup_read_from_peripheral<W: Word>(
+        &self,
+        peri_addr: *const W,
+        buf: &mut [W],
+        enable_interrupt: EnableInterrupt,
+    ) {
+        assert!(!buf.is_empty());
+        assert!(buf.len() <= 0x7fff);
+
+        let size = W::size();
+        let byte_size = size.bytes();
+
+        let t = self.tcd();
+
+        // Reset channel control/error/interrupt state
+        Self::reset_channel_state(t);
+
+        // Source: peripheral register, fixed
+        Self::set_source_ptr(t, peri_addr);
+        Self::set_source_fixed(t);
+
+        // Destination: memory buffer, incrementing
+        Self::set_dest_ptr(t, buf.as_mut_ptr());
+        Self::set_dest_increment(t, size);
+
+        // Attributes: set size and explicitly disable modulo
+        Self::set_even_transfer_size(t, size);
+
+        // Minor loop: transfer one word per request
+        Self::set_minor_loop_ct_no_offsets(t, byte_size as u32);
+
+        // No final adjustments
+        Self::set_no_final_adjustments(t);
+
+        // Major loop count = number of words
+        let count = buf.len() as u16;
+        Self::set_major_loop_ct_elinkno(t, count);
+
+        // CSR: optional interrupt on major loop complete and auto-clear ERQ
+        t.tcd_csr().write(|w| {
+            let w = match enable_interrupt {
+                EnableInterrupt::Yes => w.intmajor().enable(),
+                EnableInterrupt::No => w.intmajor().disable(),
+            };
+            w.inthalf()
+                .disable()
+                .dreq()
+                .erq_field_clear()
+                .esg()
+                .normal_format()
+                .majorelink()
+                .disable()
+                .eeop()
+                .disable()
+                .esda()
+                .disable()
+                .bwc()
+                .no_stall()
+        });
+
+        // Ensure all TCD writes have completed before DMA engine reads them
+        cortex_m::asm::dsb();
+    }
+
+    /// Configure the integrated channel MUX to use the given typed
+    /// DMA request source (e.g., [`Lpuart2TxRequest`] or [`Lpuart2RxRequest`]).
+    ///
+    /// This is the type-safe version that uses marker types to ensure
+    /// compile-time verification of request source validity.
+    ///
+    /// # Safety
+    ///
+    /// The channel must be properly configured before enabling requests.
+    /// The caller must ensure the DMA request source matches the peripheral
+    /// that will drive this channel.
+    ///
+    /// # Note
+    ///
+    /// The NXP SDK requires a two-step write sequence: first clear
+    /// the mux to 0, then set the actual source. This is a hardware
+    /// requirement on eDMA4 for the mux to properly latch.
+    ///
+    /// # Example
+    ///
+    /// ```ignore
+    /// use embassy_mcxa::dma::{DmaChannel, Lpuart2RxRequest};
+    ///
+    /// // Type-safe: compiler verifies this is a valid DMA request type
+    /// unsafe {
+    ///     channel.set_request_source::<Lpuart2RxRequest>();
+    /// }
+    /// ```
+    #[inline]
+    pub unsafe fn set_request_source<R: DmaRequest>(&self) {
+        // Two-step write per NXP SDK: clear to 0, then set actual source.
+        self.tcd().ch_mux().write(|w| w.src().bits(0));
+        cortex_m::asm::dsb(); // Ensure the clear completes before setting new source
+        self.tcd().ch_mux().write(|w| w.src().bits(R::REQUEST_NUMBER));
+    }
+
+    /// Enable hardware requests for this channel (ERQ=1).
+    ///
+    /// # Safety
+    ///
+    /// The channel must be properly configured before enabling requests.
+    pub unsafe fn enable_request(&self) {
+        let t = self.tcd();
+        t.ch_csr().modify(|_, w| w.erq().enable());
+    }
+
+    /// Disable hardware requests for this channel (ERQ=0).
+    ///
+    /// # Safety
+    ///
+    /// Disabling requests on an active transfer may leave the transfer incomplete.
+    pub unsafe fn disable_request(&self) {
+        let t = self.tcd();
+        t.ch_csr().modify(|_, w| w.erq().disable());
+    }
+
+    /// Return true if the channel's DONE flag is set.
+    pub fn is_done(&self) -> bool {
+        let t = self.tcd();
+        t.ch_csr().read().done().bit_is_set()
+    }
+
+    /// Clear the DONE flag for this channel.
+    ///
+    /// Uses modify to preserve other bits (especially ERQ) unlike write
+    /// which would clear ERQ and halt an active transfer.
+    ///
+    /// # Safety
+    ///
+    /// Clearing DONE while a transfer is in progress may cause undefined behavior.
+    pub unsafe fn clear_done(&self) {
+        let t = self.tcd();
+        t.ch_csr().modify(|_, w| w.done().clear_bit_by_one());
+    }
+
+    /// Clear the channel interrupt flag (CH_INT.INT).
+    ///
+    /// # Safety
+    ///
+    /// Must be called from the correct interrupt context or with interrupts disabled.
+    pub unsafe fn clear_interrupt(&self) {
+        let t = self.tcd();
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+    }
+
+    /// Trigger a software start for this channel.
+    ///
+    /// # Safety
+    ///
+    /// The channel must be properly configured with a valid TCD before triggering.
+    pub unsafe fn trigger_start(&self) {
+        let t = self.tcd();
+        t.tcd_csr().modify(|_, w| w.start().channel_started());
+    }
+
+    /// Get the waker for this channel
+    pub fn waker(&self) -> &'static AtomicWaker {
+        &STATES[C::INDEX].waker
+    }
+
+    /// Enable the interrupt for this channel in the NVIC.
+    pub fn enable_interrupt(&self) {
+        unsafe {
+            cortex_m::peripheral::NVIC::unmask(C::INTERRUPT);
+        }
+    }
+
+    /// Enable Major Loop Linking.
+    ///
+    /// When the major loop completes, the hardware will trigger a service request
+    /// on `link_ch`.
+    ///
+    /// # Arguments
+    ///
+    /// * `link_ch` - Target channel index (0-7) to link to
+    ///
+    /// # Safety
+    ///
+    /// The channel must be properly configured before setting up linking.
+    pub unsafe fn set_major_link(&self, link_ch: usize) {
+        let t = self.tcd();
+        t.tcd_csr()
+            .modify(|_, w| w.majorelink().enable().majorlinkch().bits(link_ch as u8));
+    }
+
+    /// Disable Major Loop Linking.
+    ///
+    /// Removes any major loop channel linking previously configured.
+    ///
+    /// # Safety
+    ///
+    /// The caller must ensure this doesn't disrupt an active transfer that
+    /// depends on the linking.
+    pub unsafe fn clear_major_link(&self) {
+        let t = self.tcd();
+        t.tcd_csr().modify(|_, w| w.majorelink().disable());
+    }
+
+    /// Enable Minor Loop Linking.
+    ///
+    /// After each minor loop, the hardware will trigger a service request
+    /// on `link_ch`.
+    ///
+    /// # Arguments
+    ///
+    /// * `link_ch` - Target channel index (0-7) to link to
+    ///
+    /// # Note
+    ///
+    /// This rewrites CITER and BITER registers to the ELINKYES format.
+    /// It preserves the current loop count.
+    ///
+    /// # Safety
+    ///
+    /// The channel must be properly configured before setting up linking.
+    pub unsafe fn set_minor_link(&self, link_ch: usize) {
+        let t = self.tcd();
+
+        // Read current CITER (assuming ELINKNO format initially)
+        let current_citer = t.tcd_citer_elinkno().read().citer().bits();
+        let current_biter = t.tcd_biter_elinkno().read().biter().bits();
+
+        // Write back using ELINKYES format
+        t.tcd_citer_elinkyes().write(|w| {
+            w.citer()
+                .bits(current_citer)
+                .elink()
+                .enable()
+                .linkch()
+                .bits(link_ch as u8)
+        });
+
+        t.tcd_biter_elinkyes().write(|w| {
+            w.biter()
+                .bits(current_biter)
+                .elink()
+                .enable()
+                .linkch()
+                .bits(link_ch as u8)
+        });
+    }
+
+    /// Disable Minor Loop Linking.
+    ///
+    /// Removes any minor loop channel linking previously configured.
+    /// This rewrites CITER and BITER registers to the ELINKNO format,
+    /// preserving the current loop count.
+    ///
+    /// # Safety
+    ///
+    /// The caller must ensure this doesn't disrupt an active transfer that
+    /// depends on the linking.
+    pub unsafe fn clear_minor_link(&self) {
+        let t = self.tcd();
+
+        // Read current CITER (could be in either format, but we only need the count)
+        // Note: In ELINKYES format, citer is 9 bits; in ELINKNO, it's 15 bits.
+        // We read from ELINKNO which will give us the combined value.
+        let current_citer = t.tcd_citer_elinkno().read().citer().bits();
+        let current_biter = t.tcd_biter_elinkno().read().biter().bits();
+
+        // Write back using ELINKNO format (disabling link)
+        t.tcd_citer_elinkno()
+            .write(|w| w.citer().bits(current_citer).elink().disable());
+
+        t.tcd_biter_elinkno()
+            .write(|w| w.biter().bits(current_biter).elink().disable());
+    }
+
+    /// Load a TCD from memory into the hardware channel registers.
+    ///
+    /// This is useful for scatter/gather and ping-pong transfers where
+    /// TCDs are prepared in RAM and then loaded into the hardware.
+    ///
+    /// # Safety
+    ///
+    /// - The TCD must be properly initialized.
+    /// - The caller must ensure no concurrent access to the same channel.
+    pub unsafe fn load_tcd(&self, tcd: &Tcd) {
+        let t = self.tcd();
+        t.tcd_saddr().write(|w| w.saddr().bits(tcd.saddr));
+        t.tcd_soff().write(|w| w.soff().bits(tcd.soff as u16));
+        t.tcd_attr().write(|w| w.bits(tcd.attr));
+        t.tcd_nbytes_mloffno().write(|w| w.nbytes().bits(tcd.nbytes));
+        t.tcd_slast_sda().write(|w| w.slast_sda().bits(tcd.slast as u32));
+        t.tcd_daddr().write(|w| w.daddr().bits(tcd.daddr));
+        t.tcd_doff().write(|w| w.doff().bits(tcd.doff as u16));
+        t.tcd_citer_elinkno().write(|w| w.citer().bits(tcd.citer));
+        t.tcd_dlast_sga().write(|w| w.dlast_sga().bits(tcd.dlast_sga as u32));
+        t.tcd_csr().write(|w| w.bits(tcd.csr));
+        t.tcd_biter_elinkno().write(|w| w.biter().bits(tcd.biter));
+    }
+}
+
+/// In-memory representation of a Transfer Control Descriptor (TCD).
+///
+/// This matches the hardware layout (32 bytes).
+#[repr(C, align(32))]
+#[derive(Clone, Copy, Debug, Default)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct Tcd {
+    pub saddr: u32,
+    pub soff: i16,
+    pub attr: u16,
+    pub nbytes: u32,
+    pub slast: i32,
+    pub daddr: u32,
+    pub doff: i16,
+    pub citer: u16,
+    pub dlast_sga: i32,
+    pub csr: u16,
+    pub biter: u16,
+}
+
+struct State {
+    /// Waker for transfer complete interrupt
+    waker: AtomicWaker,
+    /// Waker for half-transfer interrupt
+    half_waker: AtomicWaker,
+}
+
+impl State {
+    const fn new() -> Self {
+        Self {
+            waker: AtomicWaker::new(),
+            half_waker: AtomicWaker::new(),
+        }
+    }
+}
+
+static STATES: [State; 8] = [
+    State::new(),
+    State::new(),
+    State::new(),
+    State::new(),
+    State::new(),
+    State::new(),
+    State::new(),
+    State::new(),
+];
+
+pub(crate) fn waker(idx: usize) -> &'static AtomicWaker {
+    &STATES[idx].waker
+}
+
+pub(crate) fn half_waker(idx: usize) -> &'static AtomicWaker {
+    &STATES[idx].half_waker
+}
+
+// ============================================================================
+// Async Transfer Future
+// ============================================================================
+
+/// An in-progress DMA transfer.
+///
+/// This type implements `Future` and can be `.await`ed to wait for the
+/// transfer to complete. Dropping the transfer will abort it.
+#[must_use = "futures do nothing unless you `.await` or poll them"]
+pub struct Transfer<'a> {
+    channel: AnyChannel,
+    _phantom: core::marker::PhantomData<&'a ()>,
+}
+
+impl<'a> Transfer<'a> {
+    /// Create a new transfer for the given channel.
+    ///
+    /// The caller must have already configured and started the DMA channel.
+    pub(crate) fn new(channel: AnyChannel) -> Self {
+        Self {
+            channel,
+            _phantom: core::marker::PhantomData,
+        }
+    }
+
+    /// Check if the transfer is still running.
+    pub fn is_running(&self) -> bool {
+        !self.channel.is_done()
+    }
+
+    /// Get the remaining transfer count.
+    pub fn remaining(&self) -> u16 {
+        let t = self.channel.tcd();
+        t.tcd_citer_elinkno().read().citer().bits()
+    }
+
+    /// Block until the transfer completes.
+    pub fn blocking_wait(self) {
+        while self.is_running() {
+            core::hint::spin_loop();
+        }
+
+        // Ensure all DMA writes are visible
+        fence(Ordering::SeqCst);
+
+        // Don't run drop (which would abort)
+        core::mem::forget(self);
+    }
+
+    /// Wait for the half-transfer interrupt asynchronously.
+    ///
+    /// This is useful for double-buffering scenarios where you want to process
+    /// the first half of the buffer while the second half is being filled.
+    ///
+    /// Returns `true` if the half-transfer occurred, `false` if the transfer
+    /// completed before the half-transfer interrupt.
+    ///
+    /// # Note
+    ///
+    /// The transfer must be configured with `TransferOptions::half_transfer_interrupt = true`
+    /// for this method to work correctly.
+    pub async fn wait_half(&mut self) -> Result<bool, TransferErrorRaw> {
+        use core::future::poll_fn;
+
+        poll_fn(|cx| {
+            let state = &STATES[self.channel.index];
+
+            // Register the half-transfer waker
+            state.half_waker.register(cx.waker());
+
+            // Check if there's an error
+            let t = self.channel.tcd();
+            let es = t.ch_es().read();
+            if es.err().is_error() {
+                // Currently, all error fields are in the lowest 8 bits, as-casting truncates
+                let errs = es.bits() as u8;
+                return Poll::Ready(Err(TransferErrorRaw(errs)));
+            }
+
+            // Check if we're past the half-way point
+            let biter = t.tcd_biter_elinkno().read().biter().bits();
+            let citer = t.tcd_citer_elinkno().read().citer().bits();
+            let half_point = biter / 2;
+
+            if self.channel.is_done() {
+                // Transfer completed before half-transfer
+                Poll::Ready(Ok(false))
+            } else if citer <= half_point {
+                // We're past the half-way point
+                fence(Ordering::SeqCst);
+                Poll::Ready(Ok(true))
+            } else {
+                Poll::Pending
+            }
+        })
+        .await
+    }
+
+    /// Abort the transfer.
+    fn abort(&mut self) {
+        let t = self.channel.tcd();
+
+        // Disable channel requests
+        t.ch_csr().modify(|_, w| w.erq().disable());
+
+        // Clear any pending interrupt
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+
+        // Clear DONE flag
+        t.ch_csr().modify(|_, w| w.done().clear_bit_by_one());
+
+        fence(Ordering::SeqCst);
+    }
+}
+
+/// Raw transfer error bits. Can be queried or all errors can be iterated over
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Copy, Clone, Debug)]
+pub struct TransferErrorRaw(u8);
+
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Copy, Clone, Debug)]
+pub struct TransferErrorRawIter(u8);
+
+impl TransferErrorRaw {
+    const MAP: &[(u8, TransferError)] = &[
+        (1 << 0, TransferError::DestinationBus),
+        (1 << 1, TransferError::SourceBus),
+        (1 << 2, TransferError::ScatterGatherConfiguration),
+        (1 << 3, TransferError::NbytesCiterConfiguration),
+        (1 << 4, TransferError::DestinationOffset),
+        (1 << 5, TransferError::DestinationAddress),
+        (1 << 6, TransferError::SourceOffset),
+        (1 << 7, TransferError::SourceAddress),
+    ];
+
+    /// Convert to an iterator of contained errors
+    pub fn err_iter(self) -> TransferErrorRawIter {
+        TransferErrorRawIter(self.0)
+    }
+
+    /// Destination Bus Error
+    #[inline]
+    pub fn has_destination_bus_err(&self) -> bool {
+        (self.0 & (1 << 0)) != 0
+    }
+
+    /// Source Bus Error
+    #[inline]
+    pub fn has_source_bus_err(&self) -> bool {
+        (self.0 & (1 << 1)) != 0
+    }
+
+    /// Indicates that `TCDn_DLAST_SGA` is not on a 32-byte boundary. This field is
+    /// checked at the beginning of a scatter/gather operation after major loop completion
+    /// if `TCDn_CSR[ESG]` is enabled.
+    #[inline]
+    pub fn has_scatter_gather_configuration_err(&self) -> bool {
+        (self.0 & (1 << 2)) != 0
+    }
+
+    /// This error indicates that one of the following has occurred:
+    ///
+    /// * `TCDn_NBYTES` is not a multiple of `TCDn_ATTR[SSIZE]` and `TCDn_ATTR[DSIZE]`
+    /// * `TCDn_CITER[CITER]` is equal to zero
+    /// * `TCDn_CITER[ELINK]` is not equal to `TCDn_BITER[ELINK]`
+    #[inline]
+    pub fn has_nbytes_citer_configuration_err(&self) -> bool {
+        (self.0 & (1 << 3)) != 0
+    }
+
+    /// `TCDn_DOFF` is inconsistent with `TCDn_ATTR[DSIZE]`.
+    #[inline]
+    pub fn has_destination_offset_err(&self) -> bool {
+        (self.0 & (1 << 4)) != 0
+    }
+
+    /// `TCDn_DADDR` is inconsistent with `TCDn_ATTR[DSIZE]`.
+    #[inline]
+    pub fn has_destination_address_err(&self) -> bool {
+        (self.0 & (1 << 5)) != 0
+    }
+
+    /// `TCDn_SOFF` is inconsistent with `TCDn_ATTR[SSIZE]`.
+    #[inline]
+    pub fn has_source_offset_err(&self) -> bool {
+        (self.0 & (1 << 6)) != 0
+    }
+
+    /// `TCDn_SADDR` is inconsistent with `TCDn_ATTR[SSIZE]`
+    #[inline]
+    pub fn has_source_address_err(&self) -> bool {
+        (self.0 & (1 << 7)) != 0
+    }
+}
+
+impl Iterator for TransferErrorRawIter {
+    type Item = TransferError;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        if self.0 == 0 {
+            return None;
+        }
+
+        for (mask, var) in TransferErrorRaw::MAP {
+            // If the bit is set...
+            if self.0 | mask != 0 {
+                // clear the bit
+                self.0 &= !mask;
+                // and return the answer
+                return Some(*var);
+            }
+        }
+
+        // Shouldn't happen, but oh well.
+        None
+    }
+}
+
+#[derive(Copy, Clone, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum TransferError {
+    /// `TCDn_SADDR` is inconsistent with `TCDn_ATTR[SSIZE]`
+    SourceAddress,
+    /// `TCDn_SOFF` is inconsistent with `TCDn_ATTR[SSIZE]`.
+    SourceOffset,
+    /// `TCDn_DADDR` is inconsistent with `TCDn_ATTR[DSIZE]`.
+    DestinationAddress,
+    /// `TCDn_DOFF` is inconsistent with `TCDn_ATTR[DSIZE]`.
+    DestinationOffset,
+    /// This error indicates that one of the following has occurred:
+    ///
+    /// * `TCDn_NBYTES` is not a multiple of `TCDn_ATTR[SSIZE]` and `TCDn_ATTR[DSIZE]`
+    /// * `TCDn_CITER[CITER]` is equal to zero
+    /// * `TCDn_CITER[ELINK]` is not equal to `TCDn_BITER[ELINK]`
+    NbytesCiterConfiguration,
+    /// Indicates that `TCDn_DLAST_SGA` is not on a 32-byte boundary. This field is
+    /// checked at the beginning of a scatter/gather operation after major loop completion
+    /// if `TCDn_CSR[ESG]` is enabled.
+    ScatterGatherConfiguration,
+    /// Source Bus Error
+    SourceBus,
+    /// Destination Bus Error
+    DestinationBus,
+}
+
+impl<'a> Unpin for Transfer<'a> {}
+
+impl<'a> Future for Transfer<'a> {
+    type Output = Result<(), TransferErrorRaw>;
+
+    fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
+        let state = &STATES[self.channel.index];
+
+        // Register waker first
+        state.waker.register(cx.waker());
+
+        let done = self.channel.is_done();
+
+        if done {
+            // Ensure all DMA writes are visible before returning
+            fence(Ordering::SeqCst);
+
+            let es = self.channel.tcd().ch_es().read();
+            if es.err().is_error() {
+                // Currently, all error fields are in the lowest 8 bits, as-casting truncates
+                let errs = es.bits() as u8;
+                Poll::Ready(Err(TransferErrorRaw(errs)))
+            } else {
+                Poll::Ready(Ok(()))
+            }
+        } else {
+            Poll::Pending
+        }
+    }
+}
+
+impl<'a> Drop for Transfer<'a> {
+    fn drop(&mut self) {
+        // Only abort if the transfer is still running
+        // If already complete, no need to abort
+        if self.is_running() {
+            self.abort();
+
+            // Wait for abort to complete
+            while self.is_running() {
+                core::hint::spin_loop();
+            }
+        }
+
+        fence(Ordering::SeqCst);
+    }
+}
+
+// ============================================================================
+// Ring Buffer for Circular DMA
+// ============================================================================
+
+/// A ring buffer for continuous DMA reception.
+///
+/// This structure manages a circular DMA transfer, allowing continuous
+/// reception of data without losing bytes between reads. It uses both
+/// half-transfer and complete-transfer interrupts to track available data.
+///
+/// # Example
+///
+/// ```no_run
+/// use embassy_mcxa::dma::{DmaChannel, RingBuffer, TransferOptions};
+///
+/// static mut RX_BUF: [u8; 64] = [0; 64];
+///
+/// let dma_ch = DmaChannel::new(p.DMA_CH0);
+/// let ring_buf = unsafe {
+///     dma_ch.setup_circular_read(
+///         uart_rx_addr,
+///         &mut RX_BUF,
+///     )
+/// };
+///
+/// // Read data as it arrives
+/// let mut buf = [0u8; 16];
+/// let n = ring_buf.read(&mut buf).await?;
+/// ```
+pub struct RingBuffer<'a, W: Word> {
+    channel: AnyChannel,
+    /// Buffer pointer. We use NonNull instead of &mut because DMA acts like
+    /// a separate thread writing to this buffer, and &mut claims exclusive
+    /// access which the compiler could optimize incorrectly.
+    buf: NonNull<[W]>,
+    /// Buffer length cached for convenience
+    buf_len: usize,
+    /// Read position in the buffer (consumer side)
+    read_pos: AtomicUsize,
+    /// Phantom data to tie the lifetime to the original buffer
+    _lt: PhantomData<&'a mut [W]>,
+}
+
+impl<'a, W: Word> RingBuffer<'a, W> {
+    /// Create a new ring buffer for the given channel and buffer.
+    ///
+    /// # Safety
+    ///
+    /// The caller must ensure:
+    /// - The DMA channel has been configured for circular transfer
+    /// - The buffer remains valid for the lifetime of the ring buffer
+    /// - Only one RingBuffer exists per DMA channel at a time
+    pub(crate) unsafe fn new(channel: AnyChannel, buf: &'a mut [W]) -> Self {
+        let buf_len = buf.len();
+        Self {
+            channel,
+            buf: NonNull::from(buf),
+            buf_len,
+            read_pos: AtomicUsize::new(0),
+            _lt: PhantomData,
+        }
+    }
+
+    /// Get a slice reference to the buffer.
+    ///
+    /// # Safety
+    ///
+    /// The caller must ensure that DMA is not actively writing to the
+    /// portion of the buffer being accessed, or that the access is
+    /// appropriately synchronized.
+    #[inline]
+    unsafe fn buf_slice(&self) -> &[W] {
+        self.buf.as_ref()
+    }
+
+    /// Get the current DMA write position in the buffer.
+    ///
+    /// This reads the current destination address from the DMA controller
+    /// and calculates the buffer offset.
+    fn dma_write_pos(&self) -> usize {
+        let t = self.channel.tcd();
+        let daddr = t.tcd_daddr().read().daddr().bits() as usize;
+        let buf_start = self.buf.as_ptr() as *const W as usize;
+
+        // Calculate offset from buffer start
+        let offset = daddr.wrapping_sub(buf_start) / core::mem::size_of::<W>();
+
+        // Ensure we're within bounds (DMA wraps around)
+        offset % self.buf_len
+    }
+
+    /// Returns the number of bytes available to read.
+    pub fn available(&self) -> usize {
+        let write_pos = self.dma_write_pos();
+        let read_pos = self.read_pos.load(Ordering::Acquire);
+
+        if write_pos >= read_pos {
+            write_pos - read_pos
+        } else {
+            self.buf_len - read_pos + write_pos
+        }
+    }
+
+    /// Check if the buffer has overrun (data was lost).
+    ///
+    /// This happens when DMA writes faster than the application reads.
+    pub fn is_overrun(&self) -> bool {
+        // In a true overrun, the DMA would have wrapped around and caught up
+        // to our read position. We can detect this by checking if available()
+        // equals the full buffer size (minus 1 to distinguish from empty).
+        self.available() >= self.buf_len - 1
+    }
+
+    /// Read data from the ring buffer into the provided slice.
+    ///
+    /// Returns the number of elements read, which may be less than
+    /// `dst.len()` if not enough data is available.
+    ///
+    /// This method does not block; use `read_async()` for async waiting.
+    pub fn read_immediate(&self, dst: &mut [W]) -> usize {
+        let write_pos = self.dma_write_pos();
+        let read_pos = self.read_pos.load(Ordering::Acquire);
+
+        // Calculate available bytes
+        let available = if write_pos >= read_pos {
+            write_pos - read_pos
+        } else {
+            self.buf_len - read_pos + write_pos
+        };
+
+        let to_read = dst.len().min(available);
+        if to_read == 0 {
+            return 0;
+        }
+
+        // Safety: We only read from portions of the buffer that DMA has
+        // already written to (between read_pos and write_pos).
+        let buf = unsafe { self.buf_slice() };
+
+        // Read data, handling wrap-around
+        let first_chunk = (self.buf_len - read_pos).min(to_read);
+        dst[..first_chunk].copy_from_slice(&buf[read_pos..read_pos + first_chunk]);
+
+        if to_read > first_chunk {
+            let second_chunk = to_read - first_chunk;
+            dst[first_chunk..to_read].copy_from_slice(&buf[..second_chunk]);
+        }
+
+        // Update read position
+        let new_read_pos = (read_pos + to_read) % self.buf_len;
+        self.read_pos.store(new_read_pos, Ordering::Release);
+
+        to_read
+    }
+
+    /// Read data from the ring buffer asynchronously.
+    ///
+    /// This waits until at least one byte is available, then reads as much
+    /// as possible into the destination buffer.
+    ///
+    /// Returns the number of elements read.
+    pub async fn read(&self, dst: &mut [W]) -> Result<usize, Error> {
+        use core::future::poll_fn;
+
+        if dst.is_empty() {
+            return Ok(0);
+        }
+
+        poll_fn(|cx| {
+            // Check for overrun
+            if self.is_overrun() {
+                return Poll::Ready(Err(Error::Overrun));
+            }
+
+            // Try to read immediately
+            let n = self.read_immediate(dst);
+            if n > 0 {
+                return Poll::Ready(Ok(n));
+            }
+
+            // Register wakers for both half and complete interrupts
+            let state = &STATES[self.channel.index()];
+            state.waker.register(cx.waker());
+            state.half_waker.register(cx.waker());
+
+            // Check again after registering waker (avoid race)
+            let n = self.read_immediate(dst);
+            if n > 0 {
+                return Poll::Ready(Ok(n));
+            }
+
+            Poll::Pending
+        })
+        .await
+    }
+
+    /// Clear the ring buffer, discarding all unread data.
+    pub fn clear(&self) {
+        let write_pos = self.dma_write_pos();
+        self.read_pos.store(write_pos, Ordering::Release);
+    }
+
+    /// Stop the DMA transfer and consume the ring buffer.
+    ///
+    /// Returns any remaining unread data count.
+    pub fn stop(mut self) -> usize {
+        let res = self.teardown();
+        drop(self);
+        res
+    }
+
+    /// Stop the DMA transfer. Intended to be called by `stop()` or `Drop`.
+    fn teardown(&mut self) -> usize {
+        let available = self.available();
+
+        // Disable the channel
+        let t = self.channel.tcd();
+        t.ch_csr().modify(|_, w| w.erq().disable());
+
+        // Clear flags
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+        t.ch_csr().modify(|_, w| w.done().clear_bit_by_one());
+
+        fence(Ordering::SeqCst);
+
+        available
+    }
+}
+
+impl<'a, W: Word> Drop for RingBuffer<'a, W> {
+    fn drop(&mut self) {
+        self.teardown();
+    }
+}
+
+impl<C: Channel> DmaChannel<C> {
+    /// Set up a circular DMA transfer for continuous peripheral-to-memory reception.
+    ///
+    /// This configures the DMA channel for circular operation with both half-transfer
+    /// and complete-transfer interrupts enabled. The transfer runs continuously until
+    /// stopped via [`RingBuffer::stop()`].
+    ///
+    /// # Arguments
+    ///
+    /// * `peri_addr` - Peripheral register address to read from
+    /// * `buf` - Destination buffer (should be power-of-2 size for best efficiency)
+    ///
+    /// # Returns
+    ///
+    /// A [`RingBuffer`] that can be used to read received data.
+    ///
+    /// # Safety
+    ///
+    /// - The buffer must remain valid for the lifetime of the returned RingBuffer.
+    /// - The peripheral address must be valid for reads.
+    /// - The peripheral's DMA request must be configured to trigger this channel.
+    pub unsafe fn setup_circular_read<'a, W: Word>(&self, peri_addr: *const W, buf: &'a mut [W]) -> RingBuffer<'a, W> {
+        assert!(!buf.is_empty());
+        assert!(buf.len() <= 0x7fff);
+        // For circular mode, buffer size should ideally be power of 2
+        // but we don't enforce it
+
+        let size = W::size();
+        let byte_size = size.bytes();
+
+        let t = self.tcd();
+
+        // Reset channel state
+        Self::reset_channel_state(t);
+
+        // Source: peripheral register, fixed
+        Self::set_source_ptr(t, peri_addr);
+        Self::set_source_fixed(t);
+
+        // Destination: memory buffer, incrementing
+        Self::set_dest_ptr(t, buf.as_mut_ptr());
+        Self::set_dest_increment(t, size);
+
+        // Transfer attributes
+        Self::set_even_transfer_size(t, size);
+
+        // Minor loop: transfer one word per request
+        Self::set_minor_loop_ct_no_offsets(t, byte_size as u32);
+
+        // Major loop count = buffer size
+        let count = buf.len() as u16;
+        Self::set_major_loop_ct_elinkno(t, count);
+
+        // After major loop: reset destination to buffer start (circular)
+        let buf_bytes = (buf.len() * byte_size) as i32;
+        t.tcd_slast_sda().write(|w| w.slast_sda().bits(0)); // Source doesn't change
+        t.tcd_dlast_sga().write(|w| w.dlast_sga().bits((-buf_bytes) as u32));
+
+        // Control/status: enable both half and complete interrupts, NO DREQ (continuous)
+        t.tcd_csr().write(|w| {
+            w.intmajor()
+                .enable()
+                .inthalf()
+                .enable()
+                .dreq()
+                .channel_not_affected() // Don't clear ERQ on complete (circular)
+                .esg()
+                .normal_format()
+                .majorelink()
+                .disable()
+                .eeop()
+                .disable()
+                .esda()
+                .disable()
+                .bwc()
+                .no_stall()
+        });
+
+        cortex_m::asm::dsb();
+
+        // Enable the channel request
+        t.ch_csr().modify(|_, w| w.erq().enable());
+
+        // Enable NVIC interrupt for this channel so async wakeups work
+        self.enable_interrupt();
+
+        RingBuffer::new(self.as_any(), buf)
+    }
+}
+
+// ============================================================================
+// Scatter-Gather Builder
+// ============================================================================
+
+/// Maximum number of TCDs in a scatter-gather chain.
+pub const MAX_SCATTER_GATHER_TCDS: usize = 16;
+
+/// A builder for constructing scatter-gather DMA transfer chains.
+///
+/// This provides a type-safe way to build TCD chains for scatter-gather
+/// transfers without manual TCD manipulation.
+///
+/// # Example
+///
+/// ```no_run
+/// use embassy_mcxa::dma::{DmaChannel, ScatterGatherBuilder};
+///
+/// let mut builder = ScatterGatherBuilder::<u32>::new();
+///
+/// // Add transfer segments
+/// builder.add_transfer(&src1, &mut dst1);
+/// builder.add_transfer(&src2, &mut dst2);
+/// builder.add_transfer(&src3, &mut dst3);
+///
+/// // Build and execute
+/// let transfer = unsafe { builder.build(&dma_ch).unwrap() };
+/// transfer.await;
+/// ```
+pub struct ScatterGatherBuilder<'a, W: Word> {
+    /// TCD pool (must be 32-byte aligned)
+    tcds: [Tcd; MAX_SCATTER_GATHER_TCDS],
+    /// Number of TCDs configured
+    count: usize,
+    /// Phantom marker for word type
+    _phantom: core::marker::PhantomData<W>,
+
+    _plt: core::marker::PhantomData<&'a mut W>,
+}
+
+impl<'a, W: Word> ScatterGatherBuilder<'a, W> {
+    /// Create a new scatter-gather builder.
+    pub fn new() -> Self {
+        ScatterGatherBuilder {
+            tcds: [Tcd::default(); MAX_SCATTER_GATHER_TCDS],
+            count: 0,
+            _phantom: core::marker::PhantomData,
+            _plt: core::marker::PhantomData,
+        }
+    }
+
+    /// Add a memory-to-memory transfer segment to the chain.
+    ///
+    /// # Arguments
+    ///
+    /// * `src` - Source buffer for this segment
+    /// * `dst` - Destination buffer for this segment
+    ///
+    /// # Panics
+    ///
+    /// Panics if the maximum number of segments (16) is exceeded.
+    pub fn add_transfer<'b: 'a>(&mut self, src: &'b [W], dst: &'b mut [W]) -> &mut Self {
+        assert!(self.count < MAX_SCATTER_GATHER_TCDS, "Too many scatter-gather segments");
+        assert!(!src.is_empty());
+        assert!(dst.len() >= src.len());
+
+        let size = W::size();
+        let byte_size = size.bytes();
+        let hw_size = size.to_hw_size();
+        let nbytes = (src.len() * byte_size) as u32;
+
+        // Build the TCD for this segment
+        self.tcds[self.count] = Tcd {
+            saddr: src.as_ptr() as u32,
+            soff: byte_size as i16,
+            attr: ((hw_size as u16) << 8) | (hw_size as u16), // SSIZE | DSIZE
+            nbytes,
+            slast: 0,
+            daddr: dst.as_mut_ptr() as u32,
+            doff: byte_size as i16,
+            citer: 1,
+            dlast_sga: 0, // Will be filled in by build()
+            csr: 0x0002,  // INTMAJOR only (ESG will be set for non-last TCDs)
+            biter: 1,
+        };
+
+        self.count += 1;
+        self
+    }
+
+    /// Get the number of transfer segments added.
+    pub fn segment_count(&self) -> usize {
+        self.count
+    }
+
+    /// Build the scatter-gather chain and start the transfer.
+    ///
+    /// # Arguments
+    ///
+    /// * `channel` - The DMA channel to use for the transfer
+    ///
+    /// # Returns
+    ///
+    /// A `Transfer` future that completes when the entire chain has executed.
+    pub fn build<C: Channel>(&mut self, channel: &DmaChannel<C>) -> Result<Transfer<'a>, Error> {
+        if self.count == 0 {
+            return Err(Error::Configuration);
+        }
+
+        // Link TCDs together
+        //
+        // CSR bit definitions:
+        // - START = bit 0 = 0x0001 (triggers transfer when set)
+        // - INTMAJOR = bit 1 = 0x0002 (interrupt on major loop complete)
+        // - ESG = bit 4 = 0x0010 (enable scatter-gather, loads next TCD on complete)
+        //
+        // When hardware loads a TCD via scatter-gather (ESG), it copies the TCD's
+        // CSR directly into the hardware register. If START is not set in that CSR,
+        // the hardware will NOT auto-execute the loaded TCD.
+        //
+        // Strategy:
+        // - First TCD: ESG | INTMAJOR (no START - we add it manually after loading)
+        // - Middle TCDs: ESG | INTMAJOR | START (auto-execute when loaded via S/G)
+        // - Last TCD: INTMAJOR | START (auto-execute, no further linking)
+        for i in 0..self.count {
+            let is_first = i == 0;
+            let is_last = i == self.count - 1;
+
+            if is_first {
+                if is_last {
+                    // Only one TCD - no ESG, no START (we add START manually)
+                    self.tcds[i].dlast_sga = 0;
+                    self.tcds[i].csr = 0x0002; // INTMAJOR only
+                } else {
+                    // First of multiple - ESG to link, no START (we add START manually)
+                    self.tcds[i].dlast_sga = &self.tcds[i + 1] as *const Tcd as i32;
+                    self.tcds[i].csr = 0x0012; // ESG | INTMAJOR
+                }
+            } else if is_last {
+                // Last TCD (not first) - no ESG, but START so it auto-executes
+                self.tcds[i].dlast_sga = 0;
+                self.tcds[i].csr = 0x0003; // INTMAJOR | START
+            } else {
+                // Middle TCD - ESG to link, and START so it auto-executes
+                self.tcds[i].dlast_sga = &self.tcds[i + 1] as *const Tcd as i32;
+                self.tcds[i].csr = 0x0013; // ESG | INTMAJOR | START
+            }
+        }
+
+        let t = channel.tcd();
+
+        // Reset channel state - clear DONE, disable requests, clear errors
+        // This ensures the channel is in a clean state before loading the TCD
+        DmaChannel::<C>::reset_channel_state(t);
+
+        // Memory barrier to ensure channel state is reset before loading TCD
+        cortex_m::asm::dsb();
+
+        // Load first TCD into hardware
+        unsafe {
+            channel.load_tcd(&self.tcds[0]);
+        }
+
+        // Memory barrier before setting START
+        cortex_m::asm::dsb();
+
+        // Start the transfer
+        t.tcd_csr().modify(|_, w| w.start().channel_started());
+
+        Ok(Transfer::new(channel.as_any()))
+    }
+
+    /// Reset the builder for reuse.
+    pub fn clear(&mut self) {
+        self.count = 0;
+    }
+}
+
+impl<W: Word> Default for ScatterGatherBuilder<'_, W> {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+/// A completed scatter-gather transfer result.
+///
+/// This type is returned after a scatter-gather transfer completes,
+/// providing access to any error information.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct ScatterGatherResult {
+    /// Number of segments successfully transferred
+    pub segments_completed: usize,
+    /// Error if any occurred
+    pub error: Option<Error>,
+}
+
+// ============================================================================
+// Interrupt Handler
+// ============================================================================
+
+/// Interrupt handler helper.
+///
+/// Call this from your interrupt handler to clear the interrupt flag and wake the waker.
+/// This handles both half-transfer and complete-transfer interrupts.
+///
+/// # Safety
+/// Must be called from the correct DMA channel interrupt context.
+pub unsafe fn on_interrupt(ch_index: usize) {
+    let p = pac::Peripherals::steal();
+    let edma = &p.edma_0_tcd0;
+    let t = edma.tcd(ch_index);
+
+    // Read TCD CSR to determine interrupt source
+    let csr = t.tcd_csr().read();
+
+    // Check if this is a half-transfer interrupt
+    // INTHALF is set and we're at or past the half-way point
+    if csr.inthalf().bit_is_set() {
+        let biter = t.tcd_biter_elinkno().read().biter().bits();
+        let citer = t.tcd_citer_elinkno().read().citer().bits();
+        let half_point = biter / 2;
+
+        if citer <= half_point && citer > 0 {
+            // Half-transfer interrupt - wake half_waker
+            half_waker(ch_index).wake();
+        }
+    }
+
+    // Clear INT flag
+    t.ch_int().write(|w| w.int().clear_bit_by_one());
+
+    // If DONE is set, this is a complete-transfer interrupt
+    // Only wake the full-transfer waker when the transfer is actually complete
+    if t.ch_csr().read().done().bit_is_set() {
+        waker(ch_index).wake();
+    }
+}
+
+// ============================================================================
+// Type-level Interrupt Handlers
+// ============================================================================
+
+/// Macro to generate DMA channel interrupt handlers.
+macro_rules! impl_dma_interrupt_handler {
+    ($irq:ident, $ch:expr) => {
+        #[interrupt]
+        fn $irq() {
+            unsafe {
+                on_interrupt($ch);
+            }
+        }
+    };
+}
+
+use crate::pac::interrupt;
+
+impl_dma_interrupt_handler!(DMA_CH0, 0);
+impl_dma_interrupt_handler!(DMA_CH1, 1);
+impl_dma_interrupt_handler!(DMA_CH2, 2);
+impl_dma_interrupt_handler!(DMA_CH3, 3);
+impl_dma_interrupt_handler!(DMA_CH4, 4);
+impl_dma_interrupt_handler!(DMA_CH5, 5);
+impl_dma_interrupt_handler!(DMA_CH6, 6);
+impl_dma_interrupt_handler!(DMA_CH7, 7);
diff --git a/embassy-mcxa/src/gpio.rs b/embassy-mcxa/src/gpio.rs
new file mode 100644
index 000000000..65f8df985
--- /dev/null
+++ b/embassy-mcxa/src/gpio.rs
@@ -0,0 +1,1062 @@
+//! GPIO driver built around a type-erased `Flex` pin, similar to other Embassy HALs.
+//! The exported `Output`/`Input` drivers own a `Flex` so they no longer depend on the
+//! concrete pin type.
+
+use core::convert::Infallible;
+use core::future::Future;
+use core::marker::PhantomData;
+use core::pin::pin;
+
+use embassy_hal_internal::{Peri, PeripheralType};
+use maitake_sync::WaitMap;
+use paste::paste;
+
+use crate::pac::interrupt;
+use crate::pac::port0::pcr0::{Dse, Inv, Mux, Pe, Ps, Sre};
+
+struct BitIter(u32);
+
+impl Iterator for BitIter {
+    type Item = usize;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        match self.0.trailing_zeros() {
+            32 => None,
+            b => {
+                self.0 &= !(1 << b);
+                Some(b as usize)
+            }
+        }
+    }
+}
+
+const PORT_COUNT: usize = 5;
+
+static PORT_WAIT_MAPS: [WaitMap<usize, ()>; PORT_COUNT] = [
+    WaitMap::new(),
+    WaitMap::new(),
+    WaitMap::new(),
+    WaitMap::new(),
+    WaitMap::new(),
+];
+
+fn irq_handler(port_index: usize, gpio_base: *const crate::pac::gpio0::RegisterBlock) {
+    let gpio = unsafe { &*gpio_base };
+    let isfr = gpio.isfr0().read().bits();
+
+    for pin in BitIter(isfr) {
+        // Clear all pending interrupts
+        gpio.isfr0().write(|w| unsafe { w.bits(1 << pin) });
+        gpio.icr(pin).modify(|_, w| w.irqc().irqc0()); // Disable interrupt
+
+        // Wake the corresponding port waker
+        if let Some(w) = PORT_WAIT_MAPS.get(port_index) {
+            w.wake(&pin, ());
+        }
+    }
+}
+
+#[interrupt]
+fn GPIO0() {
+    irq_handler(0, crate::pac::Gpio0::ptr());
+}
+
+#[interrupt]
+fn GPIO1() {
+    irq_handler(1, crate::pac::Gpio1::ptr());
+}
+
+#[interrupt]
+fn GPIO2() {
+    irq_handler(2, crate::pac::Gpio2::ptr());
+}
+
+#[interrupt]
+fn GPIO3() {
+    irq_handler(3, crate::pac::Gpio3::ptr());
+}
+
+#[interrupt]
+fn GPIO4() {
+    irq_handler(4, crate::pac::Gpio4::ptr());
+}
+
+pub(crate) unsafe fn init() {
+    use embassy_hal_internal::interrupt::InterruptExt;
+
+    crate::pac::interrupt::GPIO0.enable();
+    crate::pac::interrupt::GPIO1.enable();
+    crate::pac::interrupt::GPIO2.enable();
+    crate::pac::interrupt::GPIO3.enable();
+    crate::pac::interrupt::GPIO4.enable();
+
+    cortex_m::interrupt::enable();
+}
+
+/// Logical level for GPIO pins.
+#[derive(Copy, Clone, Eq, PartialEq, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Level {
+    Low,
+    High,
+}
+
+impl From<bool> for Level {
+    fn from(val: bool) -> Self {
+        match val {
+            true => Self::High,
+            false => Self::Low,
+        }
+    }
+}
+
+#[derive(Copy, Clone, Eq, PartialEq, Debug)]
+pub enum Pull {
+    Disabled,
+    Up,
+    Down,
+}
+
+impl From<Pull> for (Pe, Ps) {
+    fn from(pull: Pull) -> Self {
+        match pull {
+            Pull::Disabled => (Pe::Pe0, Ps::Ps0),
+            Pull::Up => (Pe::Pe1, Ps::Ps1),
+            Pull::Down => (Pe::Pe1, Ps::Ps0),
+        }
+    }
+}
+
+#[derive(Copy, Clone, Eq, PartialEq, Debug)]
+pub enum SlewRate {
+    Fast,
+    Slow,
+}
+
+impl From<SlewRate> for Sre {
+    fn from(slew_rate: SlewRate) -> Self {
+        match slew_rate {
+            SlewRate::Fast => Sre::Sre0,
+            SlewRate::Slow => Sre::Sre1,
+        }
+    }
+}
+
+#[derive(Copy, Clone, Eq, PartialEq, Debug)]
+pub enum DriveStrength {
+    Normal,
+    Double,
+}
+
+impl From<DriveStrength> for Dse {
+    fn from(strength: DriveStrength) -> Self {
+        match strength {
+            DriveStrength::Normal => Dse::Dse0,
+            DriveStrength::Double => Dse::Dse1,
+        }
+    }
+}
+
+#[derive(Copy, Clone, Eq, PartialEq, Debug)]
+pub enum Inverter {
+    Disabled,
+    Enabled,
+}
+
+impl From<Inverter> for Inv {
+    fn from(strength: Inverter) -> Self {
+        match strength {
+            Inverter::Disabled => Inv::Inv0,
+            Inverter::Enabled => Inv::Inv1,
+        }
+    }
+}
+
+pub type Gpio = crate::peripherals::GPIO0;
+
+/// Type-erased representation of a GPIO pin.
+pub struct AnyPin {
+    port: usize,
+    pin: usize,
+    gpio: &'static crate::pac::gpio0::RegisterBlock,
+    port_reg: &'static crate::pac::port0::RegisterBlock,
+    pcr_reg: &'static crate::pac::port0::Pcr0,
+}
+
+impl AnyPin {
+    /// Create an `AnyPin` from raw components.
+    fn new(
+        port: usize,
+        pin: usize,
+        gpio: &'static crate::pac::gpio0::RegisterBlock,
+        port_reg: &'static crate::pac::port0::RegisterBlock,
+        pcr_reg: &'static crate::pac::port0::Pcr0,
+    ) -> Self {
+        Self {
+            port,
+            pin,
+            gpio,
+            port_reg,
+            pcr_reg,
+        }
+    }
+
+    #[inline(always)]
+    fn mask(&self) -> u32 {
+        1 << self.pin
+    }
+
+    #[inline(always)]
+    fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock {
+        self.gpio
+    }
+
+    #[inline(always)]
+    pub fn port_index(&self) -> usize {
+        self.port
+    }
+
+    #[inline(always)]
+    pub fn pin_index(&self) -> usize {
+        self.pin
+    }
+
+    #[inline(always)]
+    fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock {
+        self.port_reg
+    }
+
+    #[inline(always)]
+    fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0 {
+        self.pcr_reg
+    }
+}
+
+embassy_hal_internal::impl_peripheral!(AnyPin);
+
+pub(crate) trait SealedPin {
+    fn pin_port(&self) -> usize;
+
+    fn port(&self) -> usize {
+        self.pin_port() / 32
+    }
+
+    fn pin(&self) -> usize {
+        self.pin_port() % 32
+    }
+
+    fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock;
+
+    fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock;
+
+    fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0;
+
+    fn set_function(&self, function: Mux);
+
+    fn set_pull(&self, pull: Pull);
+
+    fn set_drive_strength(&self, strength: Dse);
+
+    fn set_slew_rate(&self, slew_rate: Sre);
+
+    fn set_enable_input_buffer(&self);
+}
+
+/// GPIO pin trait.
+#[allow(private_bounds)]
+pub trait GpioPin: SealedPin + Sized + PeripheralType + Into<AnyPin> + 'static {
+    /// Type-erase the pin.
+    fn degrade(self) -> AnyPin {
+        // SAFETY: This is only called within the GpioPin trait, which is only
+        // implemented within this module on valid pin peripherals and thus
+        // has been verified to be correct.
+        AnyPin::new(self.port(), self.pin(), self.gpio(), self.port_reg(), self.pcr_reg())
+    }
+}
+
+impl SealedPin for AnyPin {
+    fn pin_port(&self) -> usize {
+        self.port * 32 + self.pin
+    }
+
+    fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock {
+        self.gpio()
+    }
+
+    fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock {
+        self.port_reg()
+    }
+
+    fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0 {
+        self.pcr_reg()
+    }
+
+    fn set_function(&self, function: Mux) {
+        self.pcr_reg().modify(|_, w| w.mux().variant(function));
+    }
+
+    fn set_pull(&self, pull: Pull) {
+        let (pull_enable, pull_select) = pull.into();
+        self.pcr_reg().modify(|_, w| {
+            w.pe().variant(pull_enable);
+            w.ps().variant(pull_select)
+        });
+    }
+
+    fn set_drive_strength(&self, strength: Dse) {
+        self.pcr_reg().modify(|_, w| w.dse().variant(strength));
+    }
+
+    fn set_slew_rate(&self, slew_rate: Sre) {
+        self.pcr_reg().modify(|_, w| w.sre().variant(slew_rate));
+    }
+
+    fn set_enable_input_buffer(&self) {
+        self.pcr_reg().modify(|_, w| w.ibe().ibe1());
+    }
+}
+
+impl GpioPin for AnyPin {}
+
+macro_rules! impl_pin {
+    ($peri:ident, $port:expr, $pin:expr, $block:ident) => {
+        paste! {
+            impl SealedPin for crate::peripherals::$peri {
+                fn pin_port(&self) -> usize {
+                    $port * 32 + $pin
+                }
+
+                fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock {
+                    unsafe { &*crate::pac::$block::ptr() }
+                }
+
+                fn port_reg(&self) -> &'static crate::pac::port0::RegisterBlock {
+                    unsafe { &*crate::pac::[<Port $port>]::ptr() }
+                }
+
+                fn pcr_reg(&self) -> &'static crate::pac::port0::Pcr0 {
+                    self.port_reg().[<pcr $pin>]()
+                }
+
+                fn set_function(&self, function: Mux) {
+                    unsafe {
+                        let port_reg = &*crate::pac::[<Port $port>]::ptr();
+                        port_reg.[<pcr $pin>]().modify(|_, w| {
+                            w.mux().variant(function)
+                        });
+                    }
+                }
+
+                fn set_pull(&self, pull: Pull) {
+                    let port_reg = unsafe {&*crate::pac::[<Port $port>]::ptr()};
+                    let (pull_enable, pull_select) = pull.into();
+                    port_reg.[<pcr $pin>]().modify(|_, w| {
+                        w.pe().variant(pull_enable);
+                        w.ps().variant(pull_select)
+                    });
+                }
+
+                fn set_drive_strength(&self, strength: Dse) {
+                    let port_reg = unsafe {&*crate::pac::[<Port $port>]::ptr()};
+                    port_reg.[<pcr $pin>]().modify(|_, w| w.dse().variant(strength));
+                }
+
+                fn set_slew_rate(&self, slew_rate: Sre) {
+                    let port_reg = unsafe {&*crate::pac::[<Port $port>]::ptr()};
+                    port_reg.[<pcr $pin>]().modify(|_, w| w.sre().variant(slew_rate));
+                }
+
+                fn set_enable_input_buffer(&self) {
+                    let port_reg = unsafe {&*crate::pac::[<Port $port>]::ptr()};
+                    port_reg.[<pcr $pin>]().modify(|_, w| w.ibe().ibe1());
+                }
+            }
+
+            impl GpioPin for crate::peripherals::$peri {}
+
+            impl From<crate::peripherals::$peri> for AnyPin {
+                fn from(value: crate::peripherals::$peri) -> Self {
+                    value.degrade()
+                }
+            }
+
+            impl crate::peripherals::$peri {
+                /// Convenience helper to obtain a type-erased handle to this pin.
+                pub fn degrade(&self) -> AnyPin {
+                    AnyPin::new(self.port(), self.pin(), self.gpio(), self.port_reg(), self.pcr_reg())
+                }
+            }
+        }
+    };
+}
+
+impl_pin!(P0_0, 0, 0, Gpio0);
+impl_pin!(P0_1, 0, 1, Gpio0);
+impl_pin!(P0_2, 0, 2, Gpio0);
+impl_pin!(P0_3, 0, 3, Gpio0);
+impl_pin!(P0_4, 0, 4, Gpio0);
+impl_pin!(P0_5, 0, 5, Gpio0);
+impl_pin!(P0_6, 0, 6, Gpio0);
+impl_pin!(P0_7, 0, 7, Gpio0);
+impl_pin!(P0_8, 0, 8, Gpio0);
+impl_pin!(P0_9, 0, 9, Gpio0);
+impl_pin!(P0_10, 0, 10, Gpio0);
+impl_pin!(P0_11, 0, 11, Gpio0);
+impl_pin!(P0_12, 0, 12, Gpio0);
+impl_pin!(P0_13, 0, 13, Gpio0);
+impl_pin!(P0_14, 0, 14, Gpio0);
+impl_pin!(P0_15, 0, 15, Gpio0);
+impl_pin!(P0_16, 0, 16, Gpio0);
+impl_pin!(P0_17, 0, 17, Gpio0);
+impl_pin!(P0_18, 0, 18, Gpio0);
+impl_pin!(P0_19, 0, 19, Gpio0);
+impl_pin!(P0_20, 0, 20, Gpio0);
+impl_pin!(P0_21, 0, 21, Gpio0);
+impl_pin!(P0_22, 0, 22, Gpio0);
+impl_pin!(P0_23, 0, 23, Gpio0);
+impl_pin!(P0_24, 0, 24, Gpio0);
+impl_pin!(P0_25, 0, 25, Gpio0);
+impl_pin!(P0_26, 0, 26, Gpio0);
+impl_pin!(P0_27, 0, 27, Gpio0);
+impl_pin!(P0_28, 0, 28, Gpio0);
+impl_pin!(P0_29, 0, 29, Gpio0);
+impl_pin!(P0_30, 0, 30, Gpio0);
+impl_pin!(P0_31, 0, 31, Gpio0);
+
+impl_pin!(P1_0, 1, 0, Gpio1);
+impl_pin!(P1_1, 1, 1, Gpio1);
+impl_pin!(P1_2, 1, 2, Gpio1);
+impl_pin!(P1_3, 1, 3, Gpio1);
+impl_pin!(P1_4, 1, 4, Gpio1);
+impl_pin!(P1_5, 1, 5, Gpio1);
+impl_pin!(P1_6, 1, 6, Gpio1);
+impl_pin!(P1_7, 1, 7, Gpio1);
+impl_pin!(P1_8, 1, 8, Gpio1);
+impl_pin!(P1_9, 1, 9, Gpio1);
+impl_pin!(P1_10, 1, 10, Gpio1);
+impl_pin!(P1_11, 1, 11, Gpio1);
+impl_pin!(P1_12, 1, 12, Gpio1);
+impl_pin!(P1_13, 1, 13, Gpio1);
+impl_pin!(P1_14, 1, 14, Gpio1);
+impl_pin!(P1_15, 1, 15, Gpio1);
+impl_pin!(P1_16, 1, 16, Gpio1);
+impl_pin!(P1_17, 1, 17, Gpio1);
+impl_pin!(P1_18, 1, 18, Gpio1);
+impl_pin!(P1_19, 1, 19, Gpio1);
+impl_pin!(P1_20, 1, 20, Gpio1);
+impl_pin!(P1_21, 1, 21, Gpio1);
+impl_pin!(P1_22, 1, 22, Gpio1);
+impl_pin!(P1_23, 1, 23, Gpio1);
+impl_pin!(P1_24, 1, 24, Gpio1);
+impl_pin!(P1_25, 1, 25, Gpio1);
+impl_pin!(P1_26, 1, 26, Gpio1);
+impl_pin!(P1_27, 1, 27, Gpio1);
+impl_pin!(P1_28, 1, 28, Gpio1);
+impl_pin!(P1_29, 1, 29, Gpio1);
+impl_pin!(P1_30, 1, 30, Gpio1);
+impl_pin!(P1_31, 1, 31, Gpio1);
+
+impl_pin!(P2_0, 2, 0, Gpio2);
+impl_pin!(P2_1, 2, 1, Gpio2);
+impl_pin!(P2_2, 2, 2, Gpio2);
+impl_pin!(P2_3, 2, 3, Gpio2);
+impl_pin!(P2_4, 2, 4, Gpio2);
+impl_pin!(P2_5, 2, 5, Gpio2);
+impl_pin!(P2_6, 2, 6, Gpio2);
+impl_pin!(P2_7, 2, 7, Gpio2);
+impl_pin!(P2_8, 2, 8, Gpio2);
+impl_pin!(P2_9, 2, 9, Gpio2);
+impl_pin!(P2_10, 2, 10, Gpio2);
+impl_pin!(P2_11, 2, 11, Gpio2);
+impl_pin!(P2_12, 2, 12, Gpio2);
+impl_pin!(P2_13, 2, 13, Gpio2);
+impl_pin!(P2_14, 2, 14, Gpio2);
+impl_pin!(P2_15, 2, 15, Gpio2);
+impl_pin!(P2_16, 2, 16, Gpio2);
+impl_pin!(P2_17, 2, 17, Gpio2);
+impl_pin!(P2_18, 2, 18, Gpio2);
+impl_pin!(P2_19, 2, 19, Gpio2);
+impl_pin!(P2_20, 2, 20, Gpio2);
+impl_pin!(P2_21, 2, 21, Gpio2);
+impl_pin!(P2_22, 2, 22, Gpio2);
+impl_pin!(P2_23, 2, 23, Gpio2);
+impl_pin!(P2_24, 2, 24, Gpio2);
+impl_pin!(P2_25, 2, 25, Gpio2);
+impl_pin!(P2_26, 2, 26, Gpio2);
+impl_pin!(P2_27, 2, 27, Gpio2);
+impl_pin!(P2_28, 2, 28, Gpio2);
+impl_pin!(P2_29, 2, 29, Gpio2);
+impl_pin!(P2_30, 2, 30, Gpio2);
+impl_pin!(P2_31, 2, 31, Gpio2);
+
+impl_pin!(P3_0, 3, 0, Gpio3);
+impl_pin!(P3_1, 3, 1, Gpio3);
+impl_pin!(P3_2, 3, 2, Gpio3);
+impl_pin!(P3_3, 3, 3, Gpio3);
+impl_pin!(P3_4, 3, 4, Gpio3);
+impl_pin!(P3_5, 3, 5, Gpio3);
+impl_pin!(P3_6, 3, 6, Gpio3);
+impl_pin!(P3_7, 3, 7, Gpio3);
+impl_pin!(P3_8, 3, 8, Gpio3);
+impl_pin!(P3_9, 3, 9, Gpio3);
+impl_pin!(P3_10, 3, 10, Gpio3);
+impl_pin!(P3_11, 3, 11, Gpio3);
+impl_pin!(P3_12, 3, 12, Gpio3);
+impl_pin!(P3_13, 3, 13, Gpio3);
+impl_pin!(P3_14, 3, 14, Gpio3);
+impl_pin!(P3_15, 3, 15, Gpio3);
+impl_pin!(P3_16, 3, 16, Gpio3);
+impl_pin!(P3_17, 3, 17, Gpio3);
+impl_pin!(P3_18, 3, 18, Gpio3);
+impl_pin!(P3_19, 3, 19, Gpio3);
+impl_pin!(P3_20, 3, 20, Gpio3);
+impl_pin!(P3_21, 3, 21, Gpio3);
+impl_pin!(P3_22, 3, 22, Gpio3);
+impl_pin!(P3_23, 3, 23, Gpio3);
+impl_pin!(P3_24, 3, 24, Gpio3);
+impl_pin!(P3_25, 3, 25, Gpio3);
+impl_pin!(P3_26, 3, 26, Gpio3);
+impl_pin!(P3_27, 3, 27, Gpio3);
+impl_pin!(P3_28, 3, 28, Gpio3);
+impl_pin!(P3_29, 3, 29, Gpio3);
+impl_pin!(P3_30, 3, 30, Gpio3);
+impl_pin!(P3_31, 3, 31, Gpio3);
+
+impl_pin!(P4_0, 4, 0, Gpio4);
+impl_pin!(P4_1, 4, 1, Gpio4);
+impl_pin!(P4_2, 4, 2, Gpio4);
+impl_pin!(P4_3, 4, 3, Gpio4);
+impl_pin!(P4_4, 4, 4, Gpio4);
+impl_pin!(P4_5, 4, 5, Gpio4);
+impl_pin!(P4_6, 4, 6, Gpio4);
+impl_pin!(P4_7, 4, 7, Gpio4);
+impl_pin!(P4_8, 4, 8, Gpio4);
+impl_pin!(P4_9, 4, 9, Gpio4);
+impl_pin!(P4_10, 4, 10, Gpio4);
+impl_pin!(P4_11, 4, 11, Gpio4);
+impl_pin!(P4_12, 4, 12, Gpio4);
+impl_pin!(P4_13, 4, 13, Gpio4);
+impl_pin!(P4_14, 4, 14, Gpio4);
+impl_pin!(P4_15, 4, 15, Gpio4);
+impl_pin!(P4_16, 4, 16, Gpio4);
+impl_pin!(P4_17, 4, 17, Gpio4);
+impl_pin!(P4_18, 4, 18, Gpio4);
+impl_pin!(P4_19, 4, 19, Gpio4);
+impl_pin!(P4_20, 4, 20, Gpio4);
+impl_pin!(P4_21, 4, 21, Gpio4);
+impl_pin!(P4_22, 4, 22, Gpio4);
+impl_pin!(P4_23, 4, 23, Gpio4);
+impl_pin!(P4_24, 4, 24, Gpio4);
+impl_pin!(P4_25, 4, 25, Gpio4);
+impl_pin!(P4_26, 4, 26, Gpio4);
+impl_pin!(P4_27, 4, 27, Gpio4);
+impl_pin!(P4_28, 4, 28, Gpio4);
+impl_pin!(P4_29, 4, 29, Gpio4);
+impl_pin!(P4_30, 4, 30, Gpio4);
+impl_pin!(P4_31, 4, 31, Gpio4);
+
+/// A flexible pin that can be configured as input or output.
+pub struct Flex<'d> {
+    pin: Peri<'d, AnyPin>,
+    _marker: PhantomData<&'d mut ()>,
+}
+
+impl<'d> Flex<'d> {
+    /// Wrap the pin in a `Flex`.
+    ///
+    /// The pin remains unmodified. The initial output level is unspecified, but
+    /// can be changed before the pin is put into output mode.
+    pub fn new(pin: Peri<'d, impl GpioPin>) -> Self {
+        pin.set_function(Mux::Mux0);
+        Self {
+            pin: pin.into(),
+            _marker: PhantomData,
+        }
+    }
+
+    #[inline]
+    fn gpio(&self) -> &'static crate::pac::gpio0::RegisterBlock {
+        self.pin.gpio()
+    }
+
+    #[inline]
+    fn mask(&self) -> u32 {
+        self.pin.mask()
+    }
+
+    /// Put the pin into input mode.
+    pub fn set_as_input(&mut self) {
+        let mask = self.mask();
+        let gpio = self.gpio();
+
+        self.set_enable_input_buffer();
+
+        gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() & !mask) });
+    }
+
+    /// Put the pin into output mode.
+    pub fn set_as_output(&mut self) {
+        let mask = self.mask();
+        let gpio = self.gpio();
+
+        self.set_pull(Pull::Disabled);
+
+        gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
+    }
+
+    /// Set output level to High.
+    #[inline]
+    pub fn set_high(&mut self) {
+        self.gpio().psor().write(|w| unsafe { w.bits(self.mask()) });
+    }
+
+    /// Set output level to Low.
+    #[inline]
+    pub fn set_low(&mut self) {
+        self.gpio().pcor().write(|w| unsafe { w.bits(self.mask()) });
+    }
+
+    /// Set output level to the given `Level`.
+    #[inline]
+    pub fn set_level(&mut self, level: Level) {
+        match level {
+            Level::High => self.set_high(),
+            Level::Low => self.set_low(),
+        }
+    }
+
+    /// Toggle output level.
+    #[inline]
+    pub fn toggle(&mut self) {
+        self.gpio().ptor().write(|w| unsafe { w.bits(self.mask()) });
+    }
+
+    /// Get whether the pin input level is high.
+    #[inline]
+    pub fn is_high(&self) -> bool {
+        (self.gpio().pdir().read().bits() & self.mask()) != 0
+    }
+
+    /// Get whether the pin input level is low.
+    #[inline]
+    pub fn is_low(&self) -> bool {
+        !self.is_high()
+    }
+
+    /// Is the output pin set as high?
+    #[inline]
+    pub fn is_set_high(&self) -> bool {
+        self.is_high()
+    }
+
+    /// Is the output pin set as low?
+    #[inline]
+    pub fn is_set_low(&self) -> bool {
+        !self.is_set_high()
+    }
+
+    /// Configure the pin pull up/down level.
+    pub fn set_pull(&mut self, pull_select: Pull) {
+        self.pin.set_pull(pull_select);
+    }
+
+    /// Configure the pin drive strength.
+    pub fn set_drive_strength(&mut self, strength: DriveStrength) {
+        self.pin.set_drive_strength(strength.into());
+    }
+
+    /// Configure the pin slew rate.
+    pub fn set_slew_rate(&mut self, slew_rate: SlewRate) {
+        self.pin.set_slew_rate(slew_rate.into());
+    }
+
+    /// Enable input buffer for the pin.
+    pub fn set_enable_input_buffer(&mut self) {
+        self.pin.set_enable_input_buffer();
+    }
+
+    /// Get pin level.
+    pub fn get_level(&self) -> Level {
+        self.is_high().into()
+    }
+}
+
+/// Async methods
+impl<'d> Flex<'d> {
+    /// Helper function that waits for a given interrupt trigger
+    async fn wait_for_inner(&mut self, level: crate::pac::gpio0::icr::Irqc) {
+        // First, ensure that we have a waker that is ready for this port+pin
+        let w = PORT_WAIT_MAPS[self.pin.port].wait(self.pin.pin);
+        let mut w = pin!(w);
+        // Wait for the subscription to occur, which requires polling at least once
+        //
+        // This function returns a result, but can only be an Err if:
+        //
+        // * We call `.close()` on a WaitMap, which we never do
+        // * We have a duplicate key, which can't happen because `wait_for_*` methods
+        //   take an &mut ref of their unique port+pin combo
+        //
+        // So we wait for it to complete, but ignore the result.
+        _ = w.as_mut().subscribe().await;
+
+        // Now that our waker is in the map, we can enable the appropriate interrupt
+        //
+        // Clear any existing pending interrupt on this pin
+        self.pin
+            .gpio()
+            .isfr0()
+            .write(|w| unsafe { w.bits(1 << self.pin.pin()) });
+        self.pin.gpio().icr(self.pin.pin()).write(|w| w.isf().isf1());
+
+        // Pin interrupt configuration
+        self.pin
+            .gpio()
+            .icr(self.pin.pin())
+            .modify(|_, w| w.irqc().variant(level));
+
+        // Finally, we can await the matching call to `.wake()` from the interrupt.
+        //
+        // Again, technically, this could return a result, but for the same reasons
+        // as above, this can't be an error in our case, so just wait for it to complete
+        _ = w.await;
+    }
+
+    /// Wait until the pin is high. If it is already high, return immediately.
+    #[inline]
+    pub fn wait_for_high(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc12)
+    }
+
+    /// Wait until the pin is low. If it is already low, return immediately.
+    #[inline]
+    pub fn wait_for_low(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc8)
+    }
+
+    /// Wait for the pin to undergo a transition from low to high.
+    #[inline]
+    pub fn wait_for_rising_edge(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc9)
+    }
+
+    /// Wait for the pin to undergo a transition from high to low.
+    #[inline]
+    pub fn wait_for_falling_edge(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc10)
+    }
+
+    /// Wait for the pin to undergo any transition, i.e low to high OR high to low.
+    #[inline]
+    pub fn wait_for_any_edge(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.wait_for_inner(crate::pac::gpio0::icr::Irqc::Irqc11)
+    }
+}
+
+/// GPIO output driver that owns a `Flex` pin.
+pub struct Output<'d> {
+    flex: Flex<'d>,
+}
+
+impl<'d> Output<'d> {
+    /// Create a GPIO output driver for a [GpioPin] with the provided [Level].
+    pub fn new(pin: Peri<'d, impl GpioPin>, initial: Level, strength: DriveStrength, slew_rate: SlewRate) -> Self {
+        let mut flex = Flex::new(pin);
+        flex.set_level(initial);
+        flex.set_as_output();
+        flex.set_drive_strength(strength);
+        flex.set_slew_rate(slew_rate);
+        Self { flex }
+    }
+
+    /// Set the output as high.
+    #[inline]
+    pub fn set_high(&mut self) {
+        self.flex.set_high();
+    }
+
+    /// Set the output as low.
+    #[inline]
+    pub fn set_low(&mut self) {
+        self.flex.set_low();
+    }
+
+    /// Set the output level.
+    #[inline]
+    pub fn set_level(&mut self, level: Level) {
+        self.flex.set_level(level);
+    }
+
+    /// Toggle the output level.
+    #[inline]
+    pub fn toggle(&mut self) {
+        self.flex.toggle();
+    }
+
+    /// Is the output pin set as high?
+    #[inline]
+    pub fn is_set_high(&self) -> bool {
+        self.flex.is_high()
+    }
+
+    /// Is the output pin set as low?
+    #[inline]
+    pub fn is_set_low(&self) -> bool {
+        !self.is_set_high()
+    }
+
+    /// Expose the inner `Flex` if callers need to reconfigure the pin.
+    #[inline]
+    pub fn into_flex(self) -> Flex<'d> {
+        self.flex
+    }
+}
+
+/// GPIO input driver that owns a `Flex` pin.
+pub struct Input<'d> {
+    flex: Flex<'d>,
+}
+
+impl<'d> Input<'d> {
+    /// Create a GPIO input driver for a [GpioPin].
+    ///
+    pub fn new(pin: Peri<'d, impl GpioPin>, pull_select: Pull) -> Self {
+        let mut flex = Flex::new(pin);
+        flex.set_as_input();
+        flex.set_pull(pull_select);
+        Self { flex }
+    }
+
+    /// Get whether the pin input level is high.
+    #[inline]
+    pub fn is_high(&self) -> bool {
+        self.flex.is_high()
+    }
+
+    /// Get whether the pin input level is low.
+    #[inline]
+    pub fn is_low(&self) -> bool {
+        self.flex.is_low()
+    }
+
+    /// Expose the inner `Flex` if callers need to reconfigure the pin.
+    ///
+    /// Since Drive Strength and Slew Rate are not set when creating the Input
+    /// pin, they need to be set when converting
+    #[inline]
+    pub fn into_flex(mut self, strength: DriveStrength, slew_rate: SlewRate) -> Flex<'d> {
+        self.flex.set_drive_strength(strength);
+        self.flex.set_slew_rate(slew_rate);
+        self.flex
+    }
+
+    /// Get the pin level.
+    pub fn get_level(&self) -> Level {
+        self.flex.get_level()
+    }
+}
+
+/// Async methods
+impl<'d> Input<'d> {
+    /// Wait until the pin is high. If it is already high, return immediately.
+    #[inline]
+    pub fn wait_for_high(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.flex.wait_for_high()
+    }
+
+    /// Wait until the pin is low. If it is already low, return immediately.
+    #[inline]
+    pub fn wait_for_low(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.flex.wait_for_low()
+    }
+
+    /// Wait for the pin to undergo a transition from low to high.
+    #[inline]
+    pub fn wait_for_rising_edge(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.flex.wait_for_rising_edge()
+    }
+
+    /// Wait for the pin to undergo a transition from high to low.
+    #[inline]
+    pub fn wait_for_falling_edge(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.flex.wait_for_falling_edge()
+    }
+
+    /// Wait for the pin to undergo any transition, i.e low to high OR high to low.
+    #[inline]
+    pub fn wait_for_any_edge(&mut self) -> impl Future<Output = ()> + use<'_, 'd> {
+        self.flex.wait_for_any_edge()
+    }
+}
+
+impl embedded_hal_async::digital::Wait for Input<'_> {
+    async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_high().await;
+        Ok(())
+    }
+
+    async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_low().await;
+        Ok(())
+    }
+
+    async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_rising_edge().await;
+        Ok(())
+    }
+
+    async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_falling_edge().await;
+        Ok(())
+    }
+
+    async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_any_edge().await;
+        Ok(())
+    }
+}
+
+impl embedded_hal_async::digital::Wait for Flex<'_> {
+    async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_high().await;
+        Ok(())
+    }
+
+    async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_low().await;
+        Ok(())
+    }
+
+    async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_rising_edge().await;
+        Ok(())
+    }
+
+    async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_falling_edge().await;
+        Ok(())
+    }
+
+    async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_any_edge().await;
+        Ok(())
+    }
+}
+
+// Both embedded_hal 0.2 and 1.0 must be supported by embassy HALs.
+impl embedded_hal_02::digital::v2::InputPin for Flex<'_> {
+    // GPIO operations on this block cannot fail, therefor we set the error type
+    // to Infallible to guarantee that we can only produce Ok variants.
+    type Error = Infallible;
+
+    #[inline]
+    fn is_high(&self) -> Result<bool, Self::Error> {
+        Ok(self.is_high())
+    }
+
+    #[inline]
+    fn is_low(&self) -> Result<bool, Self::Error> {
+        Ok(self.is_low())
+    }
+}
+
+impl embedded_hal_02::digital::v2::InputPin for Input<'_> {
+    type Error = Infallible;
+
+    #[inline]
+    fn is_high(&self) -> Result<bool, Self::Error> {
+        Ok(self.is_high())
+    }
+
+    #[inline]
+    fn is_low(&self) -> Result<bool, Self::Error> {
+        Ok(self.is_low())
+    }
+}
+
+impl embedded_hal_02::digital::v2::OutputPin for Flex<'_> {
+    type Error = Infallible;
+
+    #[inline]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self.set_high();
+        Ok(())
+    }
+
+    #[inline]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self.set_low();
+        Ok(())
+    }
+}
+
+impl embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'_> {
+    #[inline]
+    fn is_set_high(&self) -> Result<bool, Self::Error> {
+        Ok(self.is_set_high())
+    }
+
+    #[inline]
+    fn is_set_low(&self) -> Result<bool, Self::Error> {
+        Ok(self.is_set_low())
+    }
+}
+
+impl embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'_> {
+    type Error = Infallible;
+
+    #[inline]
+    fn toggle(&mut self) -> Result<(), Self::Error> {
+        self.toggle();
+        Ok(())
+    }
+}
+
+impl embedded_hal_1::digital::ErrorType for Flex<'_> {
+    type Error = Infallible;
+}
+
+impl embedded_hal_1::digital::ErrorType for Input<'_> {
+    type Error = Infallible;
+}
+
+impl embedded_hal_1::digital::ErrorType for Output<'_> {
+    type Error = Infallible;
+}
+
+impl embedded_hal_1::digital::InputPin for Input<'_> {
+    #[inline]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        Ok((*self).is_high())
+    }
+
+    #[inline]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        Ok((*self).is_low())
+    }
+}
+
+impl embedded_hal_1::digital::OutputPin for Flex<'_> {
+    #[inline]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self.set_high();
+        Ok(())
+    }
+
+    #[inline]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self.set_low();
+        Ok(())
+    }
+}
+
+impl embedded_hal_1::digital::StatefulOutputPin for Flex<'_> {
+    #[inline]
+    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+        Ok((*self).is_set_high())
+    }
+
+    #[inline]
+    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+        Ok((*self).is_set_low())
+    }
+}
diff --git a/embassy-mcxa/src/i2c/controller.rs b/embassy-mcxa/src/i2c/controller.rs
new file mode 100644
index 000000000..c27d508b0
--- /dev/null
+++ b/embassy-mcxa/src/i2c/controller.rs
@@ -0,0 +1,742 @@
+//! LPI2C controller driver
+
+use core::future::Future;
+use core::marker::PhantomData;
+
+use embassy_hal_internal::Peri;
+use embassy_hal_internal::drop::OnDrop;
+use mcxa_pac::lpi2c0::mtdr::Cmd;
+
+use super::{Async, Blocking, Error, Instance, InterruptHandler, Mode, Result, SclPin, SdaPin};
+use crate::AnyPin;
+use crate::clocks::periph_helpers::{Div4, Lpi2cClockSel, Lpi2cConfig};
+use crate::clocks::{PoweredClock, enable_and_reset};
+use crate::interrupt::typelevel::Interrupt;
+
+/// Bus speed (nominal SCL, no clock stretching)
+#[derive(Clone, Copy, Default, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Speed {
+    #[default]
+    /// 100 kbit/sec
+    Standard,
+    /// 400 kbit/sec
+    Fast,
+    /// 1 Mbit/sec
+    FastPlus,
+    /// 3.4 Mbit/sec
+    UltraFast,
+}
+
+impl From<Speed> for (u8, u8, u8, u8) {
+    fn from(value: Speed) -> (u8, u8, u8, u8) {
+        match value {
+            Speed::Standard => (0x3d, 0x37, 0x3b, 0x1d),
+            Speed::Fast => (0x0e, 0x0c, 0x0d, 0x06),
+            Speed::FastPlus => (0x04, 0x03, 0x03, 0x02),
+
+            // UltraFast is "special". Leaving it unimplemented until
+            // the driver and the clock API is further stabilized.
+            Speed::UltraFast => todo!(),
+        }
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+enum SendStop {
+    No,
+    Yes,
+}
+
+/// I2C controller configuration
+#[derive(Clone, Copy, Default)]
+#[non_exhaustive]
+pub struct Config {
+    /// Bus speed
+    pub speed: Speed,
+}
+
+/// I2C Controller Driver.
+pub struct I2c<'d, T: Instance, M: Mode> {
+    _peri: Peri<'d, T>,
+    _scl: Peri<'d, AnyPin>,
+    _sda: Peri<'d, AnyPin>,
+    _phantom: PhantomData<M>,
+    is_hs: bool,
+}
+
+impl<'d, T: Instance> I2c<'d, T, Blocking> {
+    /// Create a new blocking instance of the I2C Controller bus driver.
+    pub fn new_blocking(
+        peri: Peri<'d, T>,
+        scl: Peri<'d, impl SclPin<T>>,
+        sda: Peri<'d, impl SdaPin<T>>,
+        config: Config,
+    ) -> Result<Self> {
+        Self::new_inner(peri, scl, sda, config)
+    }
+}
+
+impl<'d, T: Instance, M: Mode> I2c<'d, T, M> {
+    fn new_inner(
+        _peri: Peri<'d, T>,
+        scl: Peri<'d, impl SclPin<T>>,
+        sda: Peri<'d, impl SdaPin<T>>,
+        config: Config,
+    ) -> Result<Self> {
+        let (power, source, div) = Self::clock_config(config.speed);
+
+        // Enable clocks
+        let conf = Lpi2cConfig {
+            power,
+            source,
+            div,
+            instance: T::CLOCK_INSTANCE,
+        };
+
+        _ = unsafe { enable_and_reset::<T>(&conf).map_err(Error::ClockSetup)? };
+
+        scl.mux();
+        sda.mux();
+
+        let _scl = scl.into();
+        let _sda = sda.into();
+
+        Self::set_config(&config)?;
+
+        Ok(Self {
+            _peri,
+            _scl,
+            _sda,
+            _phantom: PhantomData,
+            is_hs: config.speed == Speed::UltraFast,
+        })
+    }
+
+    fn set_config(config: &Config) -> Result<()> {
+        // Disable the controller.
+        critical_section::with(|_| T::regs().mcr().modify(|_, w| w.men().disabled()));
+
+        // Soft-reset the controller, read and write FIFOs.
+        Self::reset_fifos();
+        critical_section::with(|_| {
+            T::regs().mcr().modify(|_, w| w.rst().reset());
+            // According to Reference Manual section 40.7.1.4, "There
+            // is no minimum delay required before clearing the
+            // software reset", therefore we clear it immediately.
+            T::regs().mcr().modify(|_, w| w.rst().not_reset());
+
+            T::regs().mcr().modify(|_, w| w.dozen().clear_bit().dbgen().clear_bit());
+        });
+
+        let (clklo, clkhi, sethold, datavd) = config.speed.into();
+
+        critical_section::with(|_| {
+            T::regs().mccr0().modify(|_, w| unsafe {
+                w.clklo()
+                    .bits(clklo)
+                    .clkhi()
+                    .bits(clkhi)
+                    .sethold()
+                    .bits(sethold)
+                    .datavd()
+                    .bits(datavd)
+            })
+        });
+
+        // Enable the controller.
+        critical_section::with(|_| T::regs().mcr().modify(|_, w| w.men().enabled()));
+
+        // Clear all flags
+        T::regs().msr().write(|w| {
+            w.epf()
+                .clear_bit_by_one()
+                .sdf()
+                .clear_bit_by_one()
+                .ndf()
+                .clear_bit_by_one()
+                .alf()
+                .clear_bit_by_one()
+                .fef()
+                .clear_bit_by_one()
+                .pltf()
+                .clear_bit_by_one()
+                .dmf()
+                .clear_bit_by_one()
+                .stf()
+                .clear_bit_by_one()
+        });
+
+        Ok(())
+    }
+
+    // REVISIT: turn this into a function of the speed parameter
+    fn clock_config(speed: Speed) -> (PoweredClock, Lpi2cClockSel, Div4) {
+        match speed {
+            Speed::Standard | Speed::Fast | Speed::FastPlus => (
+                PoweredClock::NormalEnabledDeepSleepDisabled,
+                Lpi2cClockSel::FroLfDiv,
+                const { Div4::no_div() },
+            ),
+            Speed::UltraFast => (
+                PoweredClock::NormalEnabledDeepSleepDisabled,
+                Lpi2cClockSel::FroHfDiv,
+                const { Div4::no_div() },
+            ),
+        }
+    }
+
+    /// Resets both TX and RX FIFOs dropping their contents.
+    fn reset_fifos() {
+        critical_section::with(|_| {
+            T::regs().mcr().modify(|_, w| w.rtf().reset().rrf().reset());
+        });
+    }
+
+    /// Checks whether the TX FIFO is full
+    fn is_tx_fifo_full() -> bool {
+        let txfifo_size = 1 << T::regs().param().read().mtxfifo().bits();
+        T::regs().mfsr().read().txcount().bits() == txfifo_size
+    }
+
+    /// Checks whether the TX FIFO is empty
+    fn is_tx_fifo_empty() -> bool {
+        T::regs().mfsr().read().txcount() == 0
+    }
+
+    /// Checks whether the RX FIFO is empty.
+    fn is_rx_fifo_empty() -> bool {
+        T::regs().mfsr().read().rxcount() == 0
+    }
+
+    /// Reads and parses the controller status producing an
+    /// appropriate `Result<(), Error>` variant.
+    fn status() -> Result<()> {
+        let msr = T::regs().msr().read();
+        T::regs().msr().write(|w| {
+            w.epf()
+                .clear_bit_by_one()
+                .sdf()
+                .clear_bit_by_one()
+                .ndf()
+                .clear_bit_by_one()
+                .alf()
+                .clear_bit_by_one()
+                .fef()
+                .clear_bit_by_one()
+                .fef()
+                .clear_bit_by_one()
+                .pltf()
+                .clear_bit_by_one()
+                .dmf()
+                .clear_bit_by_one()
+                .stf()
+                .clear_bit_by_one()
+        });
+
+        if msr.ndf().bit_is_set() {
+            Err(Error::AddressNack)
+        } else if msr.alf().bit_is_set() {
+            Err(Error::ArbitrationLoss)
+        } else if msr.fef().bit_is_set() {
+            Err(Error::FifoError)
+        } else {
+            Ok(())
+        }
+    }
+
+    /// Inserts the given command into the outgoing FIFO.
+    ///
+    /// Caller must ensure there is space in the FIFO for the new
+    /// command.
+    fn send_cmd(cmd: Cmd, data: u8) {
+        #[cfg(feature = "defmt")]
+        defmt::trace!(
+            "Sending cmd '{}' ({}) with data '{:08x}' MSR: {:08x}",
+            cmd,
+            cmd as u8,
+            data,
+            T::regs().msr().read().bits()
+        );
+
+        T::regs()
+            .mtdr()
+            .write(|w| unsafe { w.data().bits(data) }.cmd().variant(cmd));
+    }
+
+    /// Prepares an appropriate Start condition on bus by issuing a
+    /// `Start` command together with the device address and R/w bit.
+    ///
+    /// Blocks waiting for space in the FIFO to become available, then
+    /// sends the command and blocks waiting for the FIFO to become
+    /// empty ensuring the command was sent.
+    fn start(&mut self, address: u8, read: bool) -> Result<()> {
+        if address >= 0x80 {
+            return Err(Error::AddressOutOfRange(address));
+        }
+
+        // Wait until we have space in the TxFIFO
+        while Self::is_tx_fifo_full() {}
+
+        let addr_rw = address << 1 | if read { 1 } else { 0 };
+        Self::send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw);
+
+        // Wait for TxFIFO to be drained
+        while !Self::is_tx_fifo_empty() {}
+
+        // Check controller status
+        Self::status()
+    }
+
+    /// Prepares a Stop condition on the bus.
+    ///
+    /// Analogous to `start`, this blocks waiting for space in the
+    /// FIFO to become available, then sends the command and blocks
+    /// waiting for the FIFO to become empty ensuring the command was
+    /// sent.
+    fn stop() -> Result<()> {
+        // Wait until we have space in the TxFIFO
+        while Self::is_tx_fifo_full() {}
+
+        Self::send_cmd(Cmd::Stop, 0);
+
+        // Wait for TxFIFO to be drained
+        while !Self::is_tx_fifo_empty() {}
+
+        Self::status()
+    }
+
+    fn blocking_read_internal(&mut self, address: u8, read: &mut [u8], send_stop: SendStop) -> Result<()> {
+        if read.is_empty() {
+            return Err(Error::InvalidReadBufferLength);
+        }
+
+        for chunk in read.chunks_mut(256) {
+            self.start(address, true)?;
+
+            // Wait until we have space in the TxFIFO
+            while Self::is_tx_fifo_full() {}
+
+            Self::send_cmd(Cmd::Receive, (chunk.len() - 1) as u8);
+
+            for byte in chunk.iter_mut() {
+                // Wait until there's data in the RxFIFO
+                while Self::is_rx_fifo_empty() {}
+
+                *byte = T::regs().mrdr().read().data().bits();
+            }
+        }
+
+        if send_stop == SendStop::Yes {
+            Self::stop()?;
+        }
+
+        Ok(())
+    }
+
+    fn blocking_write_internal(&mut self, address: u8, write: &[u8], send_stop: SendStop) -> Result<()> {
+        self.start(address, false)?;
+
+        // Usually, embassy HALs error out with an empty write,
+        // however empty writes are useful for writing I2C scanning
+        // logic through write probing. That is, we send a start with
+        // R/w bit cleared, but instead of writing any data, just send
+        // the stop onto the bus. This has the effect of checking if
+        // the resulting address got an ACK but causing no
+        // side-effects to the device on the other end.
+        //
+        // Because of this, we are not going to error out in case of
+        // empty writes.
+        #[cfg(feature = "defmt")]
+        if write.is_empty() {
+            defmt::trace!("Empty write, write probing?");
+        }
+
+        for byte in write {
+            // Wait until we have space in the TxFIFO
+            while Self::is_tx_fifo_full() {}
+
+            Self::send_cmd(Cmd::Transmit, *byte);
+        }
+
+        if send_stop == SendStop::Yes {
+            Self::stop()?;
+        }
+
+        Ok(())
+    }
+
+    // Public API: Blocking
+
+    /// Read from address into buffer blocking caller until done.
+    pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<()> {
+        self.blocking_read_internal(address, read, SendStop::Yes)
+    }
+
+    /// Write to address from buffer blocking caller until done.
+    pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<()> {
+        self.blocking_write_internal(address, write, SendStop::Yes)
+    }
+
+    /// Write to address from bytes and read from address into buffer blocking caller until done.
+    pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<()> {
+        self.blocking_write_internal(address, write, SendStop::No)?;
+        self.blocking_read_internal(address, read, SendStop::Yes)
+    }
+}
+
+impl<'d, T: Instance> I2c<'d, T, Async> {
+    /// Create a new async instance of the I2C Controller bus driver.
+    pub fn new_async(
+        peri: Peri<'d, T>,
+        scl: Peri<'d, impl SclPin<T>>,
+        sda: Peri<'d, impl SdaPin<T>>,
+        _irq: impl crate::interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+        config: Config,
+    ) -> Result<Self> {
+        T::Interrupt::unpend();
+
+        // Safety: `_irq` ensures an Interrupt Handler exists.
+        unsafe { T::Interrupt::enable() };
+
+        Self::new_inner(peri, scl, sda, config)
+    }
+
+    fn remediation() {
+        #[cfg(feature = "defmt")]
+        defmt::trace!("Future dropped, issuing stop",);
+
+        // if the FIFO is not empty, drop its contents.
+        if !Self::is_tx_fifo_empty() {
+            Self::reset_fifos();
+        }
+
+        // send a stop command
+        let _ = Self::stop();
+    }
+
+    fn enable_rx_ints(&mut self) {
+        T::regs().mier().write(|w| {
+            w.rdie()
+                .enabled()
+                .ndie()
+                .enabled()
+                .alie()
+                .enabled()
+                .feie()
+                .enabled()
+                .pltie()
+                .enabled()
+        });
+    }
+
+    fn enable_tx_ints(&mut self) {
+        T::regs().mier().write(|w| {
+            w.tdie()
+                .enabled()
+                .ndie()
+                .enabled()
+                .alie()
+                .enabled()
+                .feie()
+                .enabled()
+                .pltie()
+                .enabled()
+        });
+    }
+
+    async fn async_start(&mut self, address: u8, read: bool) -> Result<()> {
+        if address >= 0x80 {
+            return Err(Error::AddressOutOfRange(address));
+        }
+
+        // send the start command
+        let addr_rw = address << 1 | if read { 1 } else { 0 };
+        Self::send_cmd(if self.is_hs { Cmd::StartHs } else { Cmd::Start }, addr_rw);
+
+        T::wait_cell()
+            .wait_for(|| {
+                // enable interrupts
+                self.enable_tx_ints();
+                // if the command FIFO is empty, we're done sending start
+                Self::is_tx_fifo_empty()
+            })
+            .await
+            .map_err(|_| Error::Other)?;
+
+        Self::status()
+    }
+
+    async fn async_stop(&mut self) -> Result<()> {
+        // send the stop command
+        Self::send_cmd(Cmd::Stop, 0);
+
+        T::wait_cell()
+            .wait_for(|| {
+                // enable interrupts
+                self.enable_tx_ints();
+                // if the command FIFO is empty, we're done sending stop
+                Self::is_tx_fifo_empty()
+            })
+            .await
+            .map_err(|_| Error::Other)?;
+
+        Self::status()
+    }
+
+    async fn async_read_internal(&mut self, address: u8, read: &mut [u8], send_stop: SendStop) -> Result<()> {
+        if read.is_empty() {
+            return Err(Error::InvalidReadBufferLength);
+        }
+
+        // perform corrective action if the future is dropped
+        let on_drop = OnDrop::new(|| Self::remediation());
+
+        for chunk in read.chunks_mut(256) {
+            self.async_start(address, true).await?;
+
+            // send receive command
+            Self::send_cmd(Cmd::Receive, (chunk.len() - 1) as u8);
+
+            T::wait_cell()
+                .wait_for(|| {
+                    // enable interrupts
+                    self.enable_tx_ints();
+                    // if the command FIFO is empty, we're done sending start
+                    Self::is_tx_fifo_empty()
+                })
+                .await
+                .map_err(|_| Error::Other)?;
+
+            for byte in chunk.iter_mut() {
+                T::wait_cell()
+                    .wait_for(|| {
+                        // enable interrupts
+                        self.enable_rx_ints();
+                        // if the rx FIFO is not empty, we need to read a byte
+                        !Self::is_rx_fifo_empty()
+                    })
+                    .await
+                    .map_err(|_| Error::ReadFail)?;
+
+                *byte = T::regs().mrdr().read().data().bits();
+            }
+        }
+
+        if send_stop == SendStop::Yes {
+            self.async_stop().await?;
+        }
+
+        // defuse it if the future is not dropped
+        on_drop.defuse();
+
+        Ok(())
+    }
+
+    async fn async_write_internal(&mut self, address: u8, write: &[u8], send_stop: SendStop) -> Result<()> {
+        self.async_start(address, false).await?;
+
+        // perform corrective action if the future is dropped
+        let on_drop = OnDrop::new(|| Self::remediation());
+
+        // Usually, embassy HALs error out with an empty write,
+        // however empty writes are useful for writing I2C scanning
+        // logic through write probing. That is, we send a start with
+        // R/w bit cleared, but instead of writing any data, just send
+        // the stop onto the bus. This has the effect of checking if
+        // the resulting address got an ACK but causing no
+        // side-effects to the device on the other end.
+        //
+        // Because of this, we are not going to error out in case of
+        // empty writes.
+        #[cfg(feature = "defmt")]
+        if write.is_empty() {
+            defmt::trace!("Empty write, write probing?");
+        }
+
+        for byte in write {
+            T::wait_cell()
+                .wait_for(|| {
+                    // enable interrupts
+                    self.enable_tx_ints();
+                    // initiate transmit
+                    Self::send_cmd(Cmd::Transmit, *byte);
+                    // if the tx FIFO is empty, we're done transmiting
+                    Self::is_tx_fifo_empty()
+                })
+                .await
+                .map_err(|_| Error::WriteFail)?;
+        }
+
+        if send_stop == SendStop::Yes {
+            self.async_stop().await?;
+        }
+
+        // defuse it if the future is not dropped
+        on_drop.defuse();
+
+        Ok(())
+    }
+
+    // Public API: Async
+
+    /// Read from address into buffer asynchronously.
+    pub fn async_read<'a>(
+        &mut self,
+        address: u8,
+        read: &'a mut [u8],
+    ) -> impl Future<Output = Result<()>> + use<'_, 'a, 'd, T> {
+        self.async_read_internal(address, read, SendStop::Yes)
+    }
+
+    /// Write to address from buffer asynchronously.
+    pub fn async_write<'a>(
+        &mut self,
+        address: u8,
+        write: &'a [u8],
+    ) -> impl Future<Output = Result<()>> + use<'_, 'a, 'd, T> {
+        self.async_write_internal(address, write, SendStop::Yes)
+    }
+
+    /// Write to address from bytes and read from address into buffer asynchronously.
+    pub async fn async_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<()> {
+        self.async_write_internal(address, write, SendStop::No).await?;
+        self.async_read_internal(address, read, SendStop::Yes).await
+    }
+}
+
+impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, T, M> {
+    type Error = Error;
+
+    fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<()> {
+        self.blocking_read(address, buffer)
+    }
+}
+
+impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, T, M> {
+    type Error = Error;
+
+    fn write(&mut self, address: u8, bytes: &[u8]) -> Result<()> {
+        self.blocking_write(address, bytes)
+    }
+}
+
+impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T, M> {
+    type Error = Error;
+
+    fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<()> {
+        self.blocking_write_read(address, bytes, buffer)
+    }
+}
+
+impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Transactional for I2c<'d, T, M> {
+    type Error = Error;
+
+    fn exec(&mut self, address: u8, operations: &mut [embedded_hal_02::blocking::i2c::Operation<'_>]) -> Result<()> {
+        if let Some((last, rest)) = operations.split_last_mut() {
+            for op in rest {
+                match op {
+                    embedded_hal_02::blocking::i2c::Operation::Read(buf) => {
+                        self.blocking_read_internal(address, buf, SendStop::No)?
+                    }
+                    embedded_hal_02::blocking::i2c::Operation::Write(buf) => {
+                        self.blocking_write_internal(address, buf, SendStop::No)?
+                    }
+                }
+            }
+
+            match last {
+                embedded_hal_02::blocking::i2c::Operation::Read(buf) => {
+                    self.blocking_read_internal(address, buf, SendStop::Yes)
+                }
+                embedded_hal_02::blocking::i2c::Operation::Write(buf) => {
+                    self.blocking_write_internal(address, buf, SendStop::Yes)
+                }
+            }
+        } else {
+            Ok(())
+        }
+    }
+}
+
+impl embedded_hal_1::i2c::Error for Error {
+    fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
+        match *self {
+            Self::ArbitrationLoss => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
+            Self::AddressNack => {
+                embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Address)
+            }
+            _ => embedded_hal_1::i2c::ErrorKind::Other,
+        }
+    }
+}
+
+impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::ErrorType for I2c<'d, T, M> {
+    type Error = Error;
+}
+
+impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::I2c for I2c<'d, T, M> {
+    fn transaction(&mut self, address: u8, operations: &mut [embedded_hal_1::i2c::Operation<'_>]) -> Result<()> {
+        if let Some((last, rest)) = operations.split_last_mut() {
+            for op in rest {
+                match op {
+                    embedded_hal_1::i2c::Operation::Read(buf) => {
+                        self.blocking_read_internal(address, buf, SendStop::No)?
+                    }
+                    embedded_hal_1::i2c::Operation::Write(buf) => {
+                        self.blocking_write_internal(address, buf, SendStop::No)?
+                    }
+                }
+            }
+
+            match last {
+                embedded_hal_1::i2c::Operation::Read(buf) => self.blocking_read_internal(address, buf, SendStop::Yes),
+                embedded_hal_1::i2c::Operation::Write(buf) => self.blocking_write_internal(address, buf, SendStop::Yes),
+            }
+        } else {
+            Ok(())
+        }
+    }
+}
+
+impl<'d, T: Instance> embedded_hal_async::i2c::I2c for I2c<'d, T, Async> {
+    async fn transaction(
+        &mut self,
+        address: u8,
+        operations: &mut [embedded_hal_async::i2c::Operation<'_>],
+    ) -> Result<()> {
+        if let Some((last, rest)) = operations.split_last_mut() {
+            for op in rest {
+                match op {
+                    embedded_hal_async::i2c::Operation::Read(buf) => {
+                        self.async_read_internal(address, buf, SendStop::No).await?
+                    }
+                    embedded_hal_async::i2c::Operation::Write(buf) => {
+                        self.async_write_internal(address, buf, SendStop::No).await?
+                    }
+                }
+            }
+
+            match last {
+                embedded_hal_async::i2c::Operation::Read(buf) => {
+                    self.async_read_internal(address, buf, SendStop::Yes).await
+                }
+                embedded_hal_async::i2c::Operation::Write(buf) => {
+                    self.async_write_internal(address, buf, SendStop::Yes).await
+                }
+            }
+        } else {
+            Ok(())
+        }
+    }
+}
+
+impl<'d, T: Instance, M: Mode> embassy_embedded_hal::SetConfig for I2c<'d, T, M> {
+    type Config = Config;
+    type ConfigError = Error;
+
+    fn set_config(&mut self, config: &Self::Config) -> Result<()> {
+        Self::set_config(config)
+    }
+}
diff --git a/embassy-mcxa/src/i2c/mod.rs b/embassy-mcxa/src/i2c/mod.rs
new file mode 100644
index 000000000..9a014224a
--- /dev/null
+++ b/embassy-mcxa/src/i2c/mod.rs
@@ -0,0 +1,194 @@
+//! I2C Support
+
+use core::marker::PhantomData;
+
+use embassy_hal_internal::PeripheralType;
+use maitake_sync::WaitCell;
+use paste::paste;
+
+use crate::clocks::periph_helpers::Lpi2cConfig;
+use crate::clocks::{ClockError, Gate};
+use crate::gpio::{GpioPin, SealedPin};
+use crate::{interrupt, pac};
+
+/// Shorthand for `Result<T>`.
+pub type Result<T> = core::result::Result<T, Error>;
+
+pub mod controller;
+
+/// Error information type
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    /// Clock configuration error.
+    ClockSetup(ClockError),
+    /// FIFO Error
+    FifoError,
+    /// Reading for I2C failed.
+    ReadFail,
+    /// Writing to I2C failed.
+    WriteFail,
+    /// I2C address NAK condition.
+    AddressNack,
+    /// Bus level arbitration loss.
+    ArbitrationLoss,
+    /// Address out of range.
+    AddressOutOfRange(u8),
+    /// Invalid write buffer length.
+    InvalidWriteBufferLength,
+    /// Invalid read buffer length.
+    InvalidReadBufferLength,
+    /// Other internal errors or unexpected state.
+    Other,
+}
+
+/// I2C interrupt handler.
+pub struct InterruptHandler<T: Instance> {
+    _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        if T::regs().mier().read().bits() != 0 {
+            T::regs().mier().write(|w| {
+                w.tdie()
+                    .disabled()
+                    .rdie()
+                    .disabled()
+                    .epie()
+                    .disabled()
+                    .sdie()
+                    .disabled()
+                    .ndie()
+                    .disabled()
+                    .alie()
+                    .disabled()
+                    .feie()
+                    .disabled()
+                    .pltie()
+                    .disabled()
+                    .dmie()
+                    .disabled()
+                    .stie()
+                    .disabled()
+            });
+
+            T::wait_cell().wake();
+        }
+    }
+}
+
+mod sealed {
+    /// Seal a trait
+    pub trait Sealed {}
+}
+
+impl<T: GpioPin> sealed::Sealed for T {}
+
+trait SealedInstance {
+    fn regs() -> &'static pac::lpi2c0::RegisterBlock;
+    fn wait_cell() -> &'static WaitCell;
+}
+
+/// I2C Instance
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType + 'static + Send + Gate<MrccPeriphConfig = Lpi2cConfig> {
+    /// Interrupt for this I2C instance.
+    type Interrupt: interrupt::typelevel::Interrupt;
+    /// Clock instance
+    const CLOCK_INSTANCE: crate::clocks::periph_helpers::Lpi2cInstance;
+}
+
+macro_rules! impl_instance {
+    ($($n:expr),*) => {
+        $(
+            paste!{
+                impl SealedInstance for crate::peripherals::[<LPI2C $n>] {
+                    fn regs() -> &'static pac::lpi2c0::RegisterBlock {
+                        unsafe { &*pac::[<Lpi2c $n>]::ptr() }
+                    }
+
+                    fn wait_cell() -> &'static WaitCell {
+                        static WAIT_CELL: WaitCell = WaitCell::new();
+                        &WAIT_CELL
+                    }
+                }
+
+                impl Instance for crate::peripherals::[<LPI2C $n>] {
+                    type Interrupt = crate::interrupt::typelevel::[<LPI2C $n>];
+                    const CLOCK_INSTANCE: crate::clocks::periph_helpers::Lpi2cInstance
+                        = crate::clocks::periph_helpers::Lpi2cInstance::[<Lpi2c $n>];
+                }
+            }
+        )*
+    };
+}
+
+impl_instance!(0, 1, 2, 3);
+
+/// SCL pin trait.
+pub trait SclPin<Instance>: GpioPin + sealed::Sealed + PeripheralType {
+    fn mux(&self);
+}
+
+/// SDA pin trait.
+pub trait SdaPin<Instance>: GpioPin + sealed::Sealed + PeripheralType {
+    fn mux(&self);
+}
+
+/// Driver mode.
+#[allow(private_bounds)]
+pub trait Mode: sealed::Sealed {}
+
+/// Blocking mode.
+pub struct Blocking;
+impl sealed::Sealed for Blocking {}
+impl Mode for Blocking {}
+
+/// Async mode.
+pub struct Async;
+impl sealed::Sealed for Async {}
+impl Mode for Async {}
+
+macro_rules! impl_pin {
+    ($pin:ident, $peri:ident, $fn:ident, $trait:ident) => {
+        impl $trait<crate::peripherals::$peri> for crate::peripherals::$pin {
+            fn mux(&self) {
+                self.set_pull(crate::gpio::Pull::Disabled);
+                self.set_slew_rate(crate::gpio::SlewRate::Fast.into());
+                self.set_drive_strength(crate::gpio::DriveStrength::Double.into());
+                self.set_function(crate::pac::port0::pcr0::Mux::$fn);
+                self.set_enable_input_buffer();
+            }
+        }
+    };
+}
+
+impl_pin!(P0_16, LPI2C0, Mux2, SdaPin);
+impl_pin!(P0_17, LPI2C0, Mux2, SclPin);
+impl_pin!(P0_18, LPI2C0, Mux2, SclPin);
+impl_pin!(P0_19, LPI2C0, Mux2, SdaPin);
+impl_pin!(P1_0, LPI2C1, Mux3, SdaPin);
+impl_pin!(P1_1, LPI2C1, Mux3, SclPin);
+impl_pin!(P1_2, LPI2C1, Mux3, SdaPin);
+impl_pin!(P1_3, LPI2C1, Mux3, SclPin);
+impl_pin!(P1_8, LPI2C2, Mux3, SdaPin);
+impl_pin!(P1_9, LPI2C2, Mux3, SclPin);
+impl_pin!(P1_10, LPI2C2, Mux3, SdaPin);
+impl_pin!(P1_11, LPI2C2, Mux3, SclPin);
+impl_pin!(P1_12, LPI2C1, Mux2, SdaPin);
+impl_pin!(P1_13, LPI2C1, Mux2, SclPin);
+impl_pin!(P1_14, LPI2C1, Mux2, SclPin);
+impl_pin!(P1_15, LPI2C1, Mux2, SdaPin);
+impl_pin!(P1_30, LPI2C0, Mux3, SdaPin);
+impl_pin!(P1_31, LPI2C0, Mux3, SclPin);
+impl_pin!(P3_27, LPI2C3, Mux2, SclPin);
+impl_pin!(P3_28, LPI2C3, Mux2, SdaPin);
+// impl_pin!(P3_29, LPI2C3, Mux2, HreqPin); What is this HREQ pin?
+impl_pin!(P3_30, LPI2C3, Mux2, SclPin);
+impl_pin!(P3_31, LPI2C3, Mux2, SdaPin);
+impl_pin!(P4_2, LPI2C2, Mux2, SdaPin);
+impl_pin!(P4_3, LPI2C0, Mux2, SclPin);
+impl_pin!(P4_4, LPI2C2, Mux2, SdaPin);
+impl_pin!(P4_5, LPI2C0, Mux2, SclPin);
+// impl_pin!(P4_6, LPI2C0, Mux2, HreqPin); What is this HREQ pin?
diff --git a/embassy-mcxa/src/interrupt.rs b/embassy-mcxa/src/interrupt.rs
new file mode 100644
index 000000000..725f8d499
--- /dev/null
+++ b/embassy-mcxa/src/interrupt.rs
@@ -0,0 +1,536 @@
+//! Minimal interrupt helpers mirroring embassy-imxrt style for OS_EVENT and LPUART2.
+//! Type-level interrupt traits and bindings are provided by the
+//! `embassy_hal_internal::interrupt_mod!` macro via the generated module below.
+
+// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs
+// are complete prior to release.
+#![allow(clippy::missing_safety_doc)]
+
+mod generated {
+    #[rustfmt::skip]
+    embassy_hal_internal::interrupt_mod!(
+        ADC0,
+        ADC1,
+        ADC2,
+        ADC3,
+        DMA_CH0,
+        DMA_CH1,
+        DMA_CH2,
+        DMA_CH3,
+        DMA_CH4,
+        DMA_CH5,
+        DMA_CH6,
+        DMA_CH7,
+        GPIO0,
+        GPIO1,
+        GPIO2,
+        GPIO3,
+        GPIO4,
+        LPI2C0,
+        LPI2C1,
+        LPI2C2,
+        LPI2C3,
+        LPUART0,
+        LPUART1,
+        LPUART2,
+        LPUART3,
+        LPUART4,
+        LPUART5,
+        OS_EVENT,
+        RTC,
+    );
+}
+
+use core::sync::atomic::{AtomicU16, AtomicU32, Ordering};
+
+pub use generated::interrupt::{Priority, typelevel};
+
+use crate::pac::Interrupt;
+
+/// Trait for configuring and controlling interrupts.
+///
+/// This trait provides a consistent interface for interrupt management across
+/// different interrupt sources, similar to embassy-imxrt's InterruptExt.
+pub trait InterruptExt {
+    /// Clear any pending interrupt in NVIC.
+    fn unpend(&self);
+
+    /// Set NVIC priority for this interrupt.
+    fn set_priority(&self, priority: Priority);
+
+    /// Enable this interrupt in NVIC.
+    ///
+    /// # Safety
+    /// This function is unsafe because it can enable interrupts that may not be
+    /// properly configured, potentially leading to undefined behavior.
+    unsafe fn enable(&self);
+
+    /// Disable this interrupt in NVIC.
+    ///
+    /// # Safety
+    /// This function is unsafe because disabling interrupts may leave the system
+    /// in an inconsistent state if the interrupt was expected to fire.
+    unsafe fn disable(&self);
+
+    /// Check if the interrupt is pending in NVIC.
+    fn is_pending(&self) -> bool;
+}
+
+#[derive(Clone, Copy, Debug, Default)]
+pub struct DefaultHandlerSnapshot {
+    pub vector: u16,
+    pub count: u32,
+    pub cfsr: u32,
+    pub hfsr: u32,
+    pub stacked_pc: u32,
+    pub stacked_lr: u32,
+    pub stacked_sp: u32,
+}
+
+static LAST_DEFAULT_VECTOR: AtomicU16 = AtomicU16::new(0);
+static LAST_DEFAULT_COUNT: AtomicU32 = AtomicU32::new(0);
+static LAST_DEFAULT_CFSR: AtomicU32 = AtomicU32::new(0);
+static LAST_DEFAULT_HFSR: AtomicU32 = AtomicU32::new(0);
+static LAST_DEFAULT_PC: AtomicU32 = AtomicU32::new(0);
+static LAST_DEFAULT_LR: AtomicU32 = AtomicU32::new(0);
+static LAST_DEFAULT_SP: AtomicU32 = AtomicU32::new(0);
+
+#[inline]
+pub fn default_handler_snapshot() -> DefaultHandlerSnapshot {
+    DefaultHandlerSnapshot {
+        vector: LAST_DEFAULT_VECTOR.load(Ordering::Relaxed),
+        count: LAST_DEFAULT_COUNT.load(Ordering::Relaxed),
+        cfsr: LAST_DEFAULT_CFSR.load(Ordering::Relaxed),
+        hfsr: LAST_DEFAULT_HFSR.load(Ordering::Relaxed),
+        stacked_pc: LAST_DEFAULT_PC.load(Ordering::Relaxed),
+        stacked_lr: LAST_DEFAULT_LR.load(Ordering::Relaxed),
+        stacked_sp: LAST_DEFAULT_SP.load(Ordering::Relaxed),
+    }
+}
+
+#[inline]
+pub fn clear_default_handler_snapshot() {
+    LAST_DEFAULT_VECTOR.store(0, Ordering::Relaxed);
+    LAST_DEFAULT_COUNT.store(0, Ordering::Relaxed);
+    LAST_DEFAULT_CFSR.store(0, Ordering::Relaxed);
+    LAST_DEFAULT_HFSR.store(0, Ordering::Relaxed);
+    LAST_DEFAULT_PC.store(0, Ordering::Relaxed);
+    LAST_DEFAULT_LR.store(0, Ordering::Relaxed);
+    LAST_DEFAULT_SP.store(0, Ordering::Relaxed);
+}
+
+/// OS_EVENT interrupt helper with methods similar to embassy-imxrt's InterruptExt.
+pub struct OsEvent;
+pub const OS_EVENT: OsEvent = OsEvent;
+
+impl InterruptExt for OsEvent {
+    /// Clear any pending OS_EVENT in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::OS_EVENT);
+    }
+
+    /// Set NVIC priority for OS_EVENT.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::OS_EVENT, u8::from(priority));
+        }
+    }
+
+    /// Enable OS_EVENT in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::OS_EVENT);
+    }
+
+    /// Disable OS_EVENT in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::OS_EVENT);
+    }
+
+    /// Check if OS_EVENT is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::OS_EVENT)
+    }
+}
+
+impl OsEvent {
+    /// Configure OS_EVENT interrupt for timer operation.
+    /// This sets up the NVIC priority, enables the interrupt, and ensures global interrupts are enabled.
+    /// Also performs a software event to wake any pending WFE.
+    pub fn configure_for_timer(&self, priority: Priority) {
+        // Configure NVIC
+        self.unpend();
+        self.set_priority(priority);
+        unsafe {
+            self.enable();
+        }
+
+        // Ensure global interrupts are enabled in no-reset scenarios (e.g., cargo run)
+        // Debuggers typically perform a reset which leaves PRIMASK=0; cargo run may not.
+        unsafe {
+            cortex_m::interrupt::enable();
+        }
+
+        // Wake any executor WFE that might be sleeping when we armed the first deadline
+        cortex_m::asm::sev();
+    }
+}
+
+/// LPUART2 interrupt helper with methods similar to embassy-imxrt's InterruptExt.
+pub struct Lpuart2;
+pub const LPUART2: Lpuart2 = Lpuart2;
+
+impl InterruptExt for Lpuart2 {
+    /// Clear any pending LPUART2 in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::LPUART2);
+    }
+
+    /// Set NVIC priority for LPUART2.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::LPUART2, u8::from(priority));
+        }
+    }
+
+    /// Enable LPUART2 in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::LPUART2);
+    }
+
+    /// Disable LPUART2 in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::LPUART2);
+    }
+
+    /// Check if LPUART2 is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::LPUART2)
+    }
+}
+
+impl Lpuart2 {
+    /// Configure LPUART2 interrupt for UART operation.
+    /// This sets up the NVIC priority, enables the interrupt, and ensures global interrupts are enabled.
+    pub fn configure_for_uart(&self, priority: Priority) {
+        // Configure NVIC
+        self.unpend();
+        self.set_priority(priority);
+        unsafe {
+            self.enable();
+        }
+
+        // Ensure global interrupts are enabled in no-reset scenarios (e.g., cargo run)
+        // Debuggers typically perform a reset which leaves PRIMASK=0; cargo run may not.
+        unsafe {
+            cortex_m::interrupt::enable();
+        }
+    }
+
+    /// Install LPUART2 handler into the RAM vector table.
+    /// Safety: See `install_irq_handler`.
+    pub unsafe fn install_handler(&self, handler: unsafe extern "C" fn()) {
+        install_irq_handler(Interrupt::LPUART2, handler);
+    }
+}
+
+pub struct Rtc;
+pub const RTC: Rtc = Rtc;
+
+impl InterruptExt for Rtc {
+    /// Clear any pending RTC in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::RTC);
+    }
+
+    /// Set NVIC priority for RTC.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::RTC, u8::from(priority));
+        }
+    }
+
+    /// Enable RTC in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::RTC);
+    }
+
+    /// Disable RTC in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::RTC);
+    }
+
+    /// Check if RTC is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::RTC)
+    }
+}
+
+pub struct Gpio0;
+pub const GPIO0: Gpio0 = Gpio0;
+
+impl InterruptExt for Gpio0 {
+    /// Clear any pending GPIO0 in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO0);
+    }
+
+    /// Set NVIC priority for GPIO0.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::GPIO0, u8::from(priority));
+        }
+    }
+
+    /// Enable GPIO0 in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO0);
+    }
+
+    /// Disable GPIO0 in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::GPIO0);
+    }
+
+    /// Check if GPIO0 is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO0)
+    }
+}
+
+pub struct Gpio1;
+pub const GPIO1: Gpio1 = Gpio1;
+
+impl InterruptExt for Gpio1 {
+    /// Clear any pending GPIO1 in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO1);
+    }
+
+    /// Set NVIC priority for GPIO1.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::GPIO1, u8::from(priority));
+        }
+    }
+
+    /// Enable GPIO1 in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO1);
+    }
+
+    /// Disable GPIO1 in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::GPIO1);
+    }
+
+    /// Check if GPIO1 is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO1)
+    }
+}
+
+pub struct Gpio2;
+pub const GPIO2: Gpio2 = Gpio2;
+
+impl InterruptExt for Gpio2 {
+    /// Clear any pending GPIO2 in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO2);
+    }
+
+    /// Set NVIC priority for GPIO2.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::GPIO2, u8::from(priority));
+        }
+    }
+
+    /// Enable GPIO2 in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO2);
+    }
+
+    /// Disable GPIO2 in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::GPIO2);
+    }
+
+    /// Check if GPIO2 is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO2)
+    }
+}
+
+pub struct Gpio3;
+pub const GPIO3: Gpio3 = Gpio3;
+
+impl InterruptExt for Gpio3 {
+    /// Clear any pending GPIO3 in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO3);
+    }
+
+    /// Set NVIC priority for GPIO3.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::GPIO3, u8::from(priority));
+        }
+    }
+
+    /// Enable GPIO3 in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO3);
+    }
+
+    /// Disable GPIO3 in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::GPIO3);
+    }
+
+    /// Check if GPIO3 is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO3)
+    }
+}
+
+pub struct Gpio4;
+pub const GPIO4: Gpio4 = Gpio4;
+
+impl InterruptExt for Gpio4 {
+    /// Clear any pending GPIO4 in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::GPIO4);
+    }
+
+    /// Set NVIC priority for GPIO4.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::GPIO4, u8::from(priority));
+        }
+    }
+
+    /// Enable GPIO4 in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::GPIO4);
+    }
+
+    /// Disable GPIO4 in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::GPIO4);
+    }
+
+    /// Check if GPIO4 is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::GPIO4)
+    }
+}
+
+/// Set VTOR (Vector Table Offset) to a RAM-based vector table.
+/// Pass a pointer to the first word in the RAM table (stack pointer slot 0).
+/// Safety: Caller must ensure the RAM table is valid and aligned as required by the core.
+pub unsafe fn vtor_set_ram_vector_base(base: *const u32) {
+    core::ptr::write_volatile(0xE000_ED08 as *mut u32, base as u32);
+}
+
+/// Install an interrupt handler into the current VTOR-based vector table.
+/// This writes the function pointer at index 16 + irq number.
+/// Safety: Caller must ensure VTOR points at a writable RAM table and that `handler`
+/// has the correct ABI and lifetime.
+pub unsafe fn install_irq_handler(irq: Interrupt, handler: unsafe extern "C" fn()) {
+    let vtor_base = core::ptr::read_volatile(0xE000_ED08 as *const u32) as *mut u32;
+    let idx = 16 + (irq as isize as usize);
+    core::ptr::write_volatile(vtor_base.add(idx), handler as usize as u32);
+}
+
+impl OsEvent {
+    /// Convenience to install the OS_EVENT handler into the RAM vector table.
+    /// Safety: See `install_irq_handler`.
+    pub unsafe fn install_handler(&self, handler: extern "C" fn()) {
+        install_irq_handler(Interrupt::OS_EVENT, handler);
+    }
+}
+
+/// Install OS_EVENT handler by raw address. Useful to avoid fn pointer type mismatches.
+/// Safety: Caller must ensure the address is a valid `extern "C" fn()` handler.
+pub unsafe fn os_event_install_handler_raw(handler_addr: usize) {
+    let vtor_base = core::ptr::read_volatile(0xE000_ED08 as *const u32) as *mut u32;
+    let idx = 16 + (Interrupt::OS_EVENT as isize as usize);
+    core::ptr::write_volatile(vtor_base.add(idx), handler_addr as u32);
+}
+
+/// Provide a conservative default IRQ handler that avoids wedging the system.
+/// It clears all NVIC pending bits and returns, so spurious or reserved IRQs
+/// don’t trap the core in an infinite WFI loop during bring-up.
+#[no_mangle]
+pub unsafe extern "C" fn DefaultHandler() {
+    let active = core::ptr::read_volatile(0xE000_ED04 as *const u32) & 0x1FF;
+    let cfsr = core::ptr::read_volatile(0xE000_ED28 as *const u32);
+    let hfsr = core::ptr::read_volatile(0xE000_ED2C as *const u32);
+
+    let sp = cortex_m::register::msp::read();
+    let stacked = sp as *const u32;
+    // Stacked registers follow ARMv8-M procedure call standard order
+    let stacked_pc = unsafe { stacked.add(6).read() };
+    let stacked_lr = unsafe { stacked.add(5).read() };
+
+    LAST_DEFAULT_VECTOR.store(active as u16, Ordering::Relaxed);
+    LAST_DEFAULT_CFSR.store(cfsr, Ordering::Relaxed);
+    LAST_DEFAULT_HFSR.store(hfsr, Ordering::Relaxed);
+    LAST_DEFAULT_COUNT.fetch_add(1, Ordering::Relaxed);
+    LAST_DEFAULT_PC.store(stacked_pc, Ordering::Relaxed);
+    LAST_DEFAULT_LR.store(stacked_lr, Ordering::Relaxed);
+    LAST_DEFAULT_SP.store(sp, Ordering::Relaxed);
+
+    // Do nothing here: on some MCUs/TrustZone setups, writing NVIC from a spurious
+    // handler can fault if targeting the Secure bank. Just return.
+    cortex_m::asm::dsb();
+    cortex_m::asm::isb();
+}
diff --git a/embassy-mcxa/src/lib.rs b/embassy-mcxa/src/lib.rs
new file mode 100644
index 000000000..be279e509
--- /dev/null
+++ b/embassy-mcxa/src/lib.rs
@@ -0,0 +1,447 @@
+#![no_std]
+#![allow(async_fn_in_trait)]
+#![doc = include_str!("../README.md")]
+
+// //! ## Feature flags
+// #![doc = document_features::document_features!(feature_label = r#"<span class="stab portability"><code>{feature}</code></span>"#)]
+
+pub mod clocks; // still provide clock helpers
+pub mod dma;
+pub mod gpio;
+
+pub mod adc;
+pub mod clkout;
+pub mod config;
+pub mod crc;
+pub mod i2c;
+pub mod interrupt;
+pub mod lpuart;
+pub mod ostimer;
+pub mod rtc;
+
+pub use crate::pac::NVIC_PRIO_BITS;
+
+#[rustfmt::skip]
+embassy_hal_internal::peripherals!(
+    ADC0,
+    ADC1,
+    ADC2,
+    ADC3,
+
+    AOI0,
+    AOI1,
+
+    CAN0,
+    CAN1,
+
+    CDOG0,
+    CDOG1,
+
+    // CLKOUT is not specifically a peripheral (it's part of SYSCON),
+    // but we still want it to be a singleton.
+    CLKOUT,
+
+    CMC,
+    CMP0,
+    CMP1,
+    CRC0,
+
+    CTIMER0,
+    CTIMER1,
+    CTIMER2,
+    CTIMER3,
+    CTIMER4,
+
+    DBGMAILBOX,
+    DMA0,
+    DMA_CH0,
+    DMA_CH1,
+    DMA_CH2,
+    DMA_CH3,
+    DMA_CH4,
+    DMA_CH5,
+    DMA_CH6,
+    DMA_CH7,
+    EDMA0_TCD0,
+    EIM0,
+    EQDC0,
+    EQDC1,
+    ERM0,
+    FLEXIO0,
+    FLEXPWM0,
+    FLEXPWM1,
+    FMC0,
+    FMU0,
+    FREQME0,
+    GLIKEY0,
+
+    GPIO0,
+    GPIO1,
+    GPIO2,
+    GPIO3,
+    GPIO4,
+
+    I3C0,
+    INPUTMUX0,
+
+    LPI2C0,
+    LPI2C1,
+    LPI2C2,
+    LPI2C3,
+
+    LPSPI0,
+    LPSPI1,
+
+    LPTMR0,
+
+    LPUART0,
+    LPUART1,
+    LPUART2,
+    LPUART3,
+    LPUART4,
+    LPUART5,
+
+    MAU0,
+    MBC0,
+    MRCC0,
+    OPAMP0,
+
+    #[cfg(not(feature = "time"))]
+    OSTIMER0,
+
+    P0_0,
+    P0_1,
+    P0_2,
+    P0_3,
+    P0_4,
+    P0_5,
+    P0_6,
+    P0_7,
+    P0_8,
+    P0_9,
+    P0_10,
+    P0_11,
+    P0_12,
+    P0_13,
+    P0_14,
+    P0_15,
+    P0_16,
+    P0_17,
+    P0_18,
+    P0_19,
+    P0_20,
+    P0_21,
+    P0_22,
+    P0_23,
+    P0_24,
+    P0_25,
+    P0_26,
+    P0_27,
+    P0_28,
+    P0_29,
+    P0_30,
+    P0_31,
+
+    P1_0,
+    P1_1,
+    P1_2,
+    P1_3,
+    P1_4,
+    P1_5,
+    P1_6,
+    P1_7,
+    P1_8,
+    P1_9,
+    P1_10,
+    P1_11,
+    P1_12,
+    P1_13,
+    P1_14,
+    P1_15,
+    P1_16,
+    P1_17,
+    P1_18,
+    P1_19,
+    P1_20,
+    P1_21,
+    P1_22,
+    P1_23,
+    P1_24,
+    P1_25,
+    P1_26,
+    P1_27,
+    P1_28,
+    P1_29,
+    P1_30,
+    P1_31,
+
+    P2_0,
+    P2_1,
+    P2_2,
+    P2_3,
+    P2_4,
+    P2_5,
+    P2_6,
+    P2_7,
+    P2_8,
+    P2_9,
+    P2_10,
+    P2_11,
+    P2_12,
+    P2_13,
+    P2_14,
+    P2_15,
+    P2_16,
+    P2_17,
+    P2_18,
+    P2_19,
+    P2_20,
+    P2_21,
+    P2_22,
+    P2_23,
+    P2_24,
+    P2_25,
+    P2_26,
+    P2_27,
+    P2_28,
+    P2_29,
+    P2_30,
+    P2_31,
+
+    P3_0,
+    P3_1,
+    P3_2,
+    P3_3,
+    P3_4,
+    P3_5,
+    P3_6,
+    P3_7,
+    P3_8,
+    P3_9,
+    P3_10,
+    P3_11,
+    P3_12,
+    P3_13,
+    P3_14,
+    P3_15,
+    P3_16,
+    P3_17,
+    P3_18,
+    P3_19,
+    P3_20,
+    P3_21,
+    P3_22,
+    P3_23,
+    P3_24,
+    P3_25,
+    P3_26,
+    P3_27,
+    P3_28,
+    P3_29,
+    P3_30,
+    P3_31,
+
+    P4_0,
+    P4_1,
+    P4_2,
+    P4_3,
+    P4_4,
+    P4_5,
+    P4_6,
+    P4_7,
+    P4_8,
+    P4_9,
+    P4_10,
+    P4_11,
+    P4_12,
+    P4_13,
+    P4_14,
+    P4_15,
+    P4_16,
+    P4_17,
+    P4_18,
+    P4_19,
+    P4_20,
+    P4_21,
+    P4_22,
+    P4_23,
+    P4_24,
+    P4_25,
+    P4_26,
+    P4_27,
+    P4_28,
+    P4_29,
+    P4_30,
+    P4_31,
+
+    P5_0,
+    P5_1,
+    P5_2,
+    P5_3,
+    P5_4,
+    P5_5,
+    P5_6,
+    P5_7,
+    P5_8,
+    P5_9,
+    P5_10,
+    P5_11,
+    P5_12,
+    P5_13,
+    P5_14,
+    P5_15,
+    P5_16,
+    P5_17,
+    P5_18,
+    P5_19,
+    P5_20,
+    P5_21,
+    P5_22,
+    P5_23,
+    P5_24,
+    P5_25,
+    P5_26,
+    P5_27,
+    P5_28,
+    P5_29,
+    P5_30,
+    P5_31,
+
+    PKC0,
+
+    PORT0,
+    PORT1,
+    PORT2,
+    PORT3,
+    PORT4,
+
+    RTC0,
+    SAU,
+    SCG0,
+    SCN_SCB,
+    SGI0,
+    SMARTDMA0,
+    SPC0,
+    SYSCON,
+    TDET0,
+    TRNG0,
+    UDF0,
+    USB0,
+    UTICK0,
+    VBAT0,
+    WAKETIMER0,
+    WUU0,
+    WWDT0,
+);
+
+// Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it.
+
+// Re-export interrupt traits and types
+pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output};
+pub use interrupt::InterruptExt;
+#[cfg(feature = "unstable-pac")]
+pub use mcxa_pac as pac;
+#[cfg(not(feature = "unstable-pac"))]
+pub(crate) use mcxa_pac as pac;
+
+/// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals.
+/// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling).
+pub fn init(cfg: crate::config::Config) -> Peripherals {
+    let peripherals = Peripherals::take();
+    // Apply user-configured priority early; enabling is left to examples/apps
+    #[cfg(feature = "time")]
+    crate::interrupt::OS_EVENT.set_priority(cfg.time_interrupt_priority);
+    // Apply user-configured priority early; enabling is left to examples/apps
+    crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority);
+    // Apply user-configured priority early; enabling is left to examples/apps
+    crate::interrupt::GPIO0.set_priority(cfg.gpio_interrupt_priority);
+    // Apply user-configured priority early; enabling is left to examples/apps
+    crate::interrupt::GPIO1.set_priority(cfg.gpio_interrupt_priority);
+    // Apply user-configured priority early; enabling is left to examples/apps
+    crate::interrupt::GPIO2.set_priority(cfg.gpio_interrupt_priority);
+    // Apply user-configured priority early; enabling is left to examples/apps
+    crate::interrupt::GPIO3.set_priority(cfg.gpio_interrupt_priority);
+    // Apply user-configured priority early; enabling is left to examples/apps
+    crate::interrupt::GPIO4.set_priority(cfg.gpio_interrupt_priority);
+
+    // Configure clocks
+    crate::clocks::init(cfg.clock_cfg).unwrap();
+
+    unsafe {
+        crate::gpio::init();
+    }
+
+    // Initialize DMA controller (clock, reset, configuration)
+    crate::dma::init();
+
+    // Initialize embassy-time global driver backed by OSTIMER0
+    #[cfg(feature = "time")]
+    crate::ostimer::time_driver::init(crate::config::Config::default().time_interrupt_priority, 1_000_000);
+
+    // Enable GPIO clocks
+    unsafe {
+        _ = crate::clocks::enable_and_reset::<crate::peripherals::PORT0>(&crate::clocks::periph_helpers::NoConfig);
+        _ = crate::clocks::enable_and_reset::<crate::peripherals::GPIO0>(&crate::clocks::periph_helpers::NoConfig);
+
+        _ = crate::clocks::enable_and_reset::<crate::peripherals::PORT1>(&crate::clocks::periph_helpers::NoConfig);
+        _ = crate::clocks::enable_and_reset::<crate::peripherals::GPIO1>(&crate::clocks::periph_helpers::NoConfig);
+
+        _ = crate::clocks::enable_and_reset::<crate::peripherals::PORT2>(&crate::clocks::periph_helpers::NoConfig);
+        _ = crate::clocks::enable_and_reset::<crate::peripherals::GPIO2>(&crate::clocks::periph_helpers::NoConfig);
+
+        _ = crate::clocks::enable_and_reset::<crate::peripherals::PORT3>(&crate::clocks::periph_helpers::NoConfig);
+        _ = crate::clocks::enable_and_reset::<crate::peripherals::GPIO3>(&crate::clocks::periph_helpers::NoConfig);
+
+        _ = crate::clocks::enable_and_reset::<crate::peripherals::PORT4>(&crate::clocks::periph_helpers::NoConfig);
+        _ = crate::clocks::enable_and_reset::<crate::peripherals::GPIO4>(&crate::clocks::periph_helpers::NoConfig);
+    }
+
+    peripherals
+}
+
+/// Macro to bind interrupts to handlers, similar to embassy-imxrt.
+///
+/// Example:
+/// - Bind OS_EVENT to the OSTIMER time-driver handler
+///   bind_interrupts!(struct Irqs { OS_EVENT => crate::ostimer::time_driver::OsEventHandler; });
+#[macro_export]
+macro_rules! bind_interrupts {
+    ($(#[$attr:meta])* $vis:vis struct $name:ident {
+        $(
+            $(#[cfg($cond_irq:meta)])?
+            $irq:ident => $(
+                $(#[cfg($cond_handler:meta)])?
+                $handler:ty
+            ),*;
+        )*
+    }) => {
+        #[derive(Copy, Clone)]
+        $(#[$attr])*
+        $vis struct $name;
+
+        $(
+            #[allow(non_snake_case)]
+            #[no_mangle]
+            $(#[cfg($cond_irq)])?
+            unsafe extern "C" fn $irq() {
+                unsafe {
+                    $(
+                        $(#[cfg($cond_handler)])?
+                        <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
+                    )*
+                }
+            }
+
+            $(#[cfg($cond_irq)])?
+            $crate::bind_interrupts!(@inner
+                $(
+                    $(#[cfg($cond_handler)])?
+                    unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {}
+                )*
+            );
+        )*
+    };
+    (@inner $($t:tt)*) => {
+        $($t)*
+    }
+}
diff --git a/embassy-mcxa/src/lpuart/buffered.rs b/embassy-mcxa/src/lpuart/buffered.rs
new file mode 100644
index 000000000..34fdbb76c
--- /dev/null
+++ b/embassy-mcxa/src/lpuart/buffered.rs
@@ -0,0 +1,780 @@
+use core::future::poll_fn;
+use core::marker::PhantomData;
+use core::sync::atomic::{AtomicBool, Ordering};
+use core::task::Poll;
+
+use embassy_hal_internal::Peri;
+use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
+use embassy_sync::waitqueue::AtomicWaker;
+
+use super::*;
+use crate::interrupt;
+
+// ============================================================================
+// STATIC STATE MANAGEMENT
+// ============================================================================
+
+/// State for buffered LPUART operations
+pub struct State {
+    tx_waker: AtomicWaker,
+    tx_buf: RingBuffer,
+    tx_done: AtomicBool,
+    rx_waker: AtomicWaker,
+    rx_buf: RingBuffer,
+    initialized: AtomicBool,
+}
+
+impl Default for State {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl State {
+    /// Create a new state instance
+    pub const fn new() -> Self {
+        Self {
+            tx_waker: AtomicWaker::new(),
+            tx_buf: RingBuffer::new(),
+            tx_done: AtomicBool::new(true),
+            rx_waker: AtomicWaker::new(),
+            rx_buf: RingBuffer::new(),
+            initialized: AtomicBool::new(false),
+        }
+    }
+}
+// ============================================================================
+// BUFFERED DRIVER STRUCTURES
+// ============================================================================
+
+/// Buffered LPUART driver
+pub struct BufferedLpuart<'a> {
+    tx: BufferedLpuartTx<'a>,
+    rx: BufferedLpuartRx<'a>,
+}
+
+/// Buffered LPUART TX driver
+pub struct BufferedLpuartTx<'a> {
+    info: Info,
+    state: &'static State,
+    _tx_pin: Peri<'a, AnyPin>,
+    _cts_pin: Option<Peri<'a, AnyPin>>,
+}
+
+/// Buffered LPUART RX driver
+pub struct BufferedLpuartRx<'a> {
+    info: Info,
+    state: &'static State,
+    _rx_pin: Peri<'a, AnyPin>,
+    _rts_pin: Option<Peri<'a, AnyPin>>,
+}
+
+// ============================================================================
+// BUFFERED LPUART IMPLEMENTATION
+// ============================================================================
+
+impl<'a> BufferedLpuart<'a> {
+    /// Common initialization logic
+    fn init_common<T: Instance>(
+        _inner: &Peri<'a, T>,
+        tx_buffer: Option<&'a mut [u8]>,
+        rx_buffer: Option<&'a mut [u8]>,
+        config: &Config,
+        enable_tx: bool,
+        enable_rx: bool,
+        enable_rts: bool,
+        enable_cts: bool,
+    ) -> Result<&'static State> {
+        let state = T::buffered_state();
+
+        if state.initialized.load(Ordering::Relaxed) {
+            return Err(Error::InvalidArgument);
+        }
+
+        // Initialize buffers
+        if let Some(tx_buffer) = tx_buffer {
+            if tx_buffer.is_empty() {
+                return Err(Error::InvalidArgument);
+            }
+            unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), tx_buffer.len()) };
+        }
+
+        if let Some(rx_buffer) = rx_buffer {
+            if rx_buffer.is_empty() {
+                return Err(Error::InvalidArgument);
+            }
+            unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), rx_buffer.len()) };
+        }
+
+        state.initialized.store(true, Ordering::Relaxed);
+
+        // Enable clocks and initialize hardware
+        let conf = LpuartConfig {
+            power: config.power,
+            source: config.source,
+            div: config.div,
+            instance: T::CLOCK_INSTANCE,
+        };
+        let clock_freq = unsafe { enable_and_reset::<T>(&conf).map_err(Error::ClockSetup)? };
+
+        Self::init_hardware(
+            T::info().regs,
+            *config,
+            clock_freq,
+            enable_tx,
+            enable_rx,
+            enable_rts,
+            enable_cts,
+        )?;
+
+        Ok(state)
+    }
+
+    /// Helper for full-duplex initialization
+    fn new_inner<T: Instance>(
+        inner: Peri<'a, T>,
+        tx_pin: Peri<'a, AnyPin>,
+        rx_pin: Peri<'a, AnyPin>,
+        rts_pin: Option<Peri<'a, AnyPin>>,
+        cts_pin: Option<Peri<'a, AnyPin>>,
+        tx_buffer: &'a mut [u8],
+        rx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<(BufferedLpuartTx<'a>, BufferedLpuartRx<'a>)> {
+        let state = Self::init_common::<T>(
+            &inner,
+            Some(tx_buffer),
+            Some(rx_buffer),
+            &config,
+            true,
+            true,
+            rts_pin.is_some(),
+            cts_pin.is_some(),
+        )?;
+
+        let tx = BufferedLpuartTx {
+            info: T::info(),
+            state,
+            _tx_pin: tx_pin,
+            _cts_pin: cts_pin,
+        };
+
+        let rx = BufferedLpuartRx {
+            info: T::info(),
+            state,
+            _rx_pin: rx_pin,
+            _rts_pin: rts_pin,
+        };
+
+        Ok((tx, rx))
+    }
+
+    /// Common hardware initialization logic
+    fn init_hardware(
+        regs: &'static mcxa_pac::lpuart0::RegisterBlock,
+        config: Config,
+        clock_freq: u32,
+        enable_tx: bool,
+        enable_rx: bool,
+        enable_rts: bool,
+        enable_cts: bool,
+    ) -> Result<()> {
+        // Perform standard initialization
+        perform_software_reset(regs);
+        disable_transceiver(regs);
+        configure_baudrate(regs, config.baudrate_bps, clock_freq)?;
+        configure_frame_format(regs, &config);
+        configure_control_settings(regs, &config);
+        configure_fifo(regs, &config);
+        clear_all_status_flags(regs);
+        configure_flow_control(regs, enable_rts, enable_cts, &config);
+        configure_bit_order(regs, config.msb_first);
+
+        // Enable interrupts for buffered operation
+        cortex_m::interrupt::free(|_| {
+            regs.ctrl().modify(|_, w| {
+                w.rie()
+                    .enabled() // RX interrupt
+                    .orie()
+                    .enabled() // Overrun interrupt
+                    .peie()
+                    .enabled() // Parity error interrupt
+                    .feie()
+                    .enabled() // Framing error interrupt
+                    .neie()
+                    .enabled() // Noise error interrupt
+            });
+        });
+
+        // Enable the transceiver
+        enable_transceiver(regs, enable_rx, enable_tx);
+
+        Ok(())
+    }
+
+    /// Create a new full duplex buffered LPUART
+    pub fn new<T: Instance>(
+        inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
+        tx_buffer: &'a mut [u8],
+        rx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<Self> {
+        tx_pin.as_tx();
+        rx_pin.as_rx();
+
+        let (tx, rx) = Self::new_inner::<T>(
+            inner,
+            tx_pin.into(),
+            rx_pin.into(),
+            None,
+            None,
+            tx_buffer,
+            rx_buffer,
+            config,
+        )?;
+
+        Ok(Self { tx, rx })
+    }
+
+    /// Create a new buffered LPUART instance with RTS/CTS flow control
+    pub fn new_with_rtscts<T: Instance>(
+        inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        rts_pin: Peri<'a, impl RtsPin<T>>,
+        cts_pin: Peri<'a, impl CtsPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
+        tx_buffer: &'a mut [u8],
+        rx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<Self> {
+        tx_pin.as_tx();
+        rx_pin.as_rx();
+        rts_pin.as_rts();
+        cts_pin.as_cts();
+
+        let (tx, rx) = Self::new_inner::<T>(
+            inner,
+            tx_pin.into(),
+            rx_pin.into(),
+            Some(rts_pin.into()),
+            Some(cts_pin.into()),
+            tx_buffer,
+            rx_buffer,
+            config,
+        )?;
+
+        Ok(Self { tx, rx })
+    }
+
+    /// Create a new buffered LPUART with only RTS flow control (RX flow control)
+    pub fn new_with_rts<T: Instance>(
+        inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        rts_pin: Peri<'a, impl RtsPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
+        tx_buffer: &'a mut [u8],
+        rx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<Self> {
+        tx_pin.as_tx();
+        rx_pin.as_rx();
+        rts_pin.as_rts();
+
+        let (tx, rx) = Self::new_inner::<T>(
+            inner,
+            tx_pin.into(),
+            rx_pin.into(),
+            Some(rts_pin.into()),
+            None,
+            tx_buffer,
+            rx_buffer,
+            config,
+        )?;
+
+        Ok(Self { tx, rx })
+    }
+
+    /// Create a new buffered LPUART with only CTS flow control (TX flow control)
+    pub fn new_with_cts<T: Instance>(
+        inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        cts_pin: Peri<'a, impl CtsPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
+        tx_buffer: &'a mut [u8],
+        rx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<Self> {
+        tx_pin.as_tx();
+        rx_pin.as_rx();
+        cts_pin.as_cts();
+
+        let (tx, rx) = Self::new_inner::<T>(
+            inner,
+            tx_pin.into(),
+            rx_pin.into(),
+            None,
+            Some(cts_pin.into()),
+            tx_buffer,
+            rx_buffer,
+            config,
+        )?;
+
+        Ok(Self { tx, rx })
+    }
+
+    /// Split the buffered LPUART into separate TX and RX parts
+    pub fn split(self) -> (BufferedLpuartTx<'a>, BufferedLpuartRx<'a>) {
+        (self.tx, self.rx)
+    }
+
+    /// Get mutable references to TX and RX parts
+    pub fn split_ref(&mut self) -> (&mut BufferedLpuartTx<'a>, &mut BufferedLpuartRx<'a>) {
+        (&mut self.tx, &mut self.rx)
+    }
+}
+
+// ============================================================================
+// BUFFERED TX IMPLEMENTATION
+// ============================================================================
+
+impl<'a> BufferedLpuartTx<'a> {
+    /// Helper for TX-only initialization
+    fn new_inner<T: Instance>(
+        inner: Peri<'a, T>,
+        tx_pin: Peri<'a, AnyPin>,
+        cts_pin: Option<Peri<'a, AnyPin>>,
+        tx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<BufferedLpuartTx<'a>> {
+        let state = BufferedLpuart::init_common::<T>(
+            &inner,
+            Some(tx_buffer),
+            None,
+            &config,
+            true,
+            false,
+            false,
+            cts_pin.is_some(),
+        )?;
+
+        Ok(BufferedLpuartTx {
+            info: T::info(),
+            state,
+            _tx_pin: tx_pin,
+            _cts_pin: cts_pin,
+        })
+    }
+
+    pub fn new<T: Instance>(
+        inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
+        tx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<Self> {
+        tx_pin.as_tx();
+
+        Self::new_inner::<T>(inner, tx_pin.into(), None, tx_buffer, config)
+    }
+
+    /// Create a new TX-only buffered LPUART with CTS flow control
+    pub fn new_with_cts<T: Instance>(
+        inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        cts_pin: Peri<'a, impl CtsPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
+        tx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<Self> {
+        tx_pin.as_tx();
+        cts_pin.as_cts();
+
+        Self::new_inner::<T>(inner, tx_pin.into(), Some(cts_pin.into()), tx_buffer, config)
+    }
+}
+
+impl<'a> BufferedLpuartTx<'a> {
+    /// Write data asynchronously
+    pub async fn write(&mut self, buf: &[u8]) -> Result<usize> {
+        let mut written = 0;
+
+        for &byte in buf {
+            // Wait for space in the buffer
+            poll_fn(|cx| {
+                self.state.tx_waker.register(cx.waker());
+
+                let mut writer = unsafe { self.state.tx_buf.writer() };
+                if writer.push_one(byte) {
+                    // Enable TX interrupt to start transmission
+                    cortex_m::interrupt::free(|_| {
+                        self.info.regs.ctrl().modify(|_, w| w.tie().enabled());
+                    });
+                    Poll::Ready(Ok(()))
+                } else {
+                    Poll::Pending
+                }
+            })
+            .await?;
+
+            written += 1;
+        }
+
+        Ok(written)
+    }
+
+    /// Flush the TX buffer and wait for transmission to complete
+    pub async fn flush(&mut self) -> Result<()> {
+        // Wait for TX buffer to empty and transmission to complete
+        poll_fn(|cx| {
+            self.state.tx_waker.register(cx.waker());
+
+            let tx_empty = self.state.tx_buf.is_empty();
+            let fifo_empty = self.info.regs.water().read().txcount().bits() == 0;
+            let tc_complete = self.info.regs.stat().read().tc().is_complete();
+
+            if tx_empty && fifo_empty && tc_complete {
+                Poll::Ready(Ok(()))
+            } else {
+                // Enable appropriate interrupt
+                cortex_m::interrupt::free(|_| {
+                    if !tx_empty {
+                        self.info.regs.ctrl().modify(|_, w| w.tie().enabled());
+                    } else {
+                        self.info.regs.ctrl().modify(|_, w| w.tcie().enabled());
+                    }
+                });
+                Poll::Pending
+            }
+        })
+        .await
+    }
+
+    /// Try to write without blocking
+    pub fn try_write(&mut self, buf: &[u8]) -> Result<usize> {
+        let mut writer = unsafe { self.state.tx_buf.writer() };
+        let mut written = 0;
+
+        for &byte in buf {
+            if writer.push_one(byte) {
+                written += 1;
+            } else {
+                break;
+            }
+        }
+
+        if written > 0 {
+            // Enable TX interrupt to start transmission
+            cortex_m::interrupt::free(|_| {
+                self.info.regs.ctrl().modify(|_, w| w.tie().enabled());
+            });
+        }
+
+        Ok(written)
+    }
+}
+
+// ============================================================================
+// BUFFERED RX IMPLEMENTATION
+// ============================================================================
+
+impl<'a> BufferedLpuartRx<'a> {
+    /// Helper for RX-only initialization
+    fn new_inner<T: Instance>(
+        inner: Peri<'a, T>,
+        rx_pin: Peri<'a, AnyPin>,
+        rts_pin: Option<Peri<'a, AnyPin>>,
+        rx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<BufferedLpuartRx<'a>> {
+        let state = BufferedLpuart::init_common::<T>(
+            &inner,
+            None,
+            Some(rx_buffer),
+            &config,
+            false,
+            true,
+            rts_pin.is_some(),
+            false,
+        )?;
+
+        Ok(BufferedLpuartRx {
+            info: T::info(),
+            state,
+            _rx_pin: rx_pin,
+            _rts_pin: rts_pin,
+        })
+    }
+
+    /// Create a new RX-only buffered LPUART
+    pub fn new<T: Instance>(
+        inner: Peri<'a, T>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
+        rx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<Self> {
+        rx_pin.as_rx();
+
+        Self::new_inner::<T>(inner, rx_pin.into(), None, rx_buffer, config)
+    }
+
+    /// Create a new RX-only buffered LPUART with RTS flow control
+    pub fn new_with_rts<T: Instance>(
+        inner: Peri<'a, T>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        rts_pin: Peri<'a, impl RtsPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
+        rx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<Self> {
+        rx_pin.as_rx();
+        rts_pin.as_rts();
+
+        Self::new_inner::<T>(inner, rx_pin.into(), Some(rts_pin.into()), rx_buffer, config)
+    }
+}
+
+impl<'a> BufferedLpuartRx<'a> {
+    /// Read data asynchronously
+    pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize> {
+        if buf.is_empty() {
+            return Ok(0);
+        }
+
+        let mut read = 0;
+
+        // Try to read available data
+        poll_fn(|cx| {
+            self.state.rx_waker.register(cx.waker());
+
+            // Disable RX interrupt while reading from buffer
+            cortex_m::interrupt::free(|_| {
+                self.info.regs.ctrl().modify(|_, w| w.rie().disabled());
+            });
+
+            let mut reader = unsafe { self.state.rx_buf.reader() };
+            let available = reader.pop(|data| {
+                let to_copy = core::cmp::min(data.len(), buf.len() - read);
+                if to_copy > 0 {
+                    buf[read..read + to_copy].copy_from_slice(&data[..to_copy]);
+                    read += to_copy;
+                }
+                to_copy
+            });
+
+            // Re-enable RX interrupt
+            cortex_m::interrupt::free(|_| {
+                self.info.regs.ctrl().modify(|_, w| w.rie().enabled());
+            });
+
+            if read > 0 {
+                Poll::Ready(Ok(read))
+            } else if available == 0 {
+                Poll::Pending
+            } else {
+                Poll::Ready(Ok(0))
+            }
+        })
+        .await
+    }
+
+    /// Try to read without blocking
+    pub fn try_read(&mut self, buf: &mut [u8]) -> Result<usize> {
+        if buf.is_empty() {
+            return Ok(0);
+        }
+
+        // Disable RX interrupt while reading from buffer
+        cortex_m::interrupt::free(|_| {
+            self.info.regs.ctrl().modify(|_, w| w.rie().disabled());
+        });
+
+        let mut reader = unsafe { self.state.rx_buf.reader() };
+        let read = reader.pop(|data| {
+            let to_copy = core::cmp::min(data.len(), buf.len());
+            if to_copy > 0 {
+                buf[..to_copy].copy_from_slice(&data[..to_copy]);
+            }
+            to_copy
+        });
+
+        // Re-enable RX interrupt
+        cortex_m::interrupt::free(|_| {
+            self.info.regs.ctrl().modify(|_, w| w.rie().enabled());
+        });
+
+        Ok(read)
+    }
+}
+
+// ============================================================================
+// INTERRUPT HANDLER
+// ============================================================================
+
+/// Buffered UART interrupt handler
+pub struct BufferedInterruptHandler<T: Instance> {
+    _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> crate::interrupt::typelevel::Handler<T::Interrupt> for BufferedInterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        let regs = T::info().regs;
+        let state = T::buffered_state();
+
+        // Check if this instance is initialized
+        if !state.initialized.load(Ordering::Relaxed) {
+            return;
+        }
+
+        let ctrl = regs.ctrl().read();
+        let stat = regs.stat().read();
+        let has_fifo = regs.param().read().rxfifo().bits() > 0;
+
+        // Handle overrun error
+        if stat.or().is_overrun() {
+            regs.stat().write(|w| w.or().clear_bit_by_one());
+            state.rx_waker.wake();
+            return;
+        }
+
+        // Clear other error flags
+        if stat.pf().is_parity() {
+            regs.stat().write(|w| w.pf().clear_bit_by_one());
+        }
+        if stat.fe().is_error() {
+            regs.stat().write(|w| w.fe().clear_bit_by_one());
+        }
+        if stat.nf().is_noise() {
+            regs.stat().write(|w| w.nf().clear_bit_by_one());
+        }
+
+        // Handle RX data
+        if ctrl.rie().is_enabled() && (has_data(regs) || stat.idle().is_idle()) {
+            let mut pushed_any = false;
+            let mut writer = state.rx_buf.writer();
+
+            if has_fifo {
+                // Read from FIFO
+                while regs.water().read().rxcount().bits() > 0 {
+                    let byte = (regs.data().read().bits() & 0xFF) as u8;
+                    if writer.push_one(byte) {
+                        pushed_any = true;
+                    } else {
+                        // Buffer full, stop reading
+                        break;
+                    }
+                }
+            } else {
+                // Read single byte
+                if regs.stat().read().rdrf().is_rxdata() {
+                    let byte = (regs.data().read().bits() & 0xFF) as u8;
+                    if writer.push_one(byte) {
+                        pushed_any = true;
+                    }
+                }
+            }
+
+            if pushed_any {
+                state.rx_waker.wake();
+            }
+
+            // Clear idle flag if set
+            if stat.idle().is_idle() {
+                regs.stat().write(|w| w.idle().clear_bit_by_one());
+            }
+        }
+
+        // Handle TX data
+        if ctrl.tie().is_enabled() {
+            let mut sent_any = false;
+            let mut reader = state.tx_buf.reader();
+
+            // Send data while TX buffer is ready and we have data
+            while regs.stat().read().tdre().is_no_txdata() {
+                if let Some(byte) = reader.pop_one() {
+                    regs.data().write(|w| w.bits(u32::from(byte)));
+                    sent_any = true;
+                } else {
+                    // No more data to send
+                    break;
+                }
+            }
+
+            if sent_any {
+                state.tx_waker.wake();
+            }
+
+            // If buffer is empty, switch to TC interrupt or disable
+            if state.tx_buf.is_empty() {
+                cortex_m::interrupt::free(|_| {
+                    regs.ctrl().modify(|_, w| w.tie().disabled().tcie().enabled());
+                });
+            }
+        }
+
+        // Handle transmission complete
+        if ctrl.tcie().is_enabled() && regs.stat().read().tc().is_complete() {
+            state.tx_done.store(true, Ordering::Release);
+            state.tx_waker.wake();
+
+            // Disable TC interrupt
+            cortex_m::interrupt::free(|_| {
+                regs.ctrl().modify(|_, w| w.tcie().disabled());
+            });
+        }
+    }
+}
+
+// ============================================================================
+// EMBEDDED-IO ASYNC TRAIT IMPLEMENTATIONS
+// ============================================================================
+
+impl embedded_io_async::ErrorType for BufferedLpuartTx<'_> {
+    type Error = Error;
+}
+
+impl embedded_io_async::ErrorType for BufferedLpuartRx<'_> {
+    type Error = Error;
+}
+
+impl embedded_io_async::ErrorType for BufferedLpuart<'_> {
+    type Error = Error;
+}
+
+impl embedded_io_async::Write for BufferedLpuartTx<'_> {
+    async fn write(&mut self, buf: &[u8]) -> core::result::Result<usize, Self::Error> {
+        self.write(buf).await
+    }
+
+    async fn flush(&mut self) -> core::result::Result<(), Self::Error> {
+        self.flush().await
+    }
+}
+
+impl embedded_io_async::Read for BufferedLpuartRx<'_> {
+    async fn read(&mut self, buf: &mut [u8]) -> core::result::Result<usize, Self::Error> {
+        self.read(buf).await
+    }
+}
+
+impl embedded_io_async::Write for BufferedLpuart<'_> {
+    async fn write(&mut self, buf: &[u8]) -> core::result::Result<usize, Self::Error> {
+        self.tx.write(buf).await
+    }
+
+    async fn flush(&mut self) -> core::result::Result<(), Self::Error> {
+        self.tx.flush().await
+    }
+}
+
+impl embedded_io_async::Read for BufferedLpuart<'_> {
+    async fn read(&mut self, buf: &mut [u8]) -> core::result::Result<usize, Self::Error> {
+        self.rx.read(buf).await
+    }
+}
diff --git a/embassy-mcxa/src/lpuart/mod.rs b/embassy-mcxa/src/lpuart/mod.rs
new file mode 100644
index 000000000..e59ce8140
--- /dev/null
+++ b/embassy-mcxa/src/lpuart/mod.rs
@@ -0,0 +1,1783 @@
+use core::future::Future;
+use core::marker::PhantomData;
+
+use embassy_hal_internal::{Peri, PeripheralType};
+use paste::paste;
+
+use crate::clocks::periph_helpers::{Div4, LpuartClockSel, LpuartConfig};
+use crate::clocks::{ClockError, Gate, PoweredClock, enable_and_reset};
+use crate::gpio::SealedPin;
+use crate::pac::lpuart0::baud::Sbns as StopBits;
+use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, M as DataBits, Pt as Parity};
+use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource};
+use crate::pac::lpuart0::stat::Msbf as MsbFirst;
+use crate::{AnyPin, interrupt, pac};
+
+pub mod buffered;
+
+// ============================================================================
+// DMA INTEGRATION
+// ============================================================================
+
+use crate::dma::{
+    Channel as DmaChannelTrait, DMA_MAX_TRANSFER_SIZE, DmaChannel, DmaRequest, EnableInterrupt, RingBuffer,
+};
+
+// ============================================================================
+// MISC
+// ============================================================================
+
+mod sealed {
+    /// Simply seal a trait to prevent external implementations
+    pub trait Sealed {}
+}
+
+// ============================================================================
+// INSTANCE TRAIT
+// ============================================================================
+
+pub type Regs = &'static crate::pac::lpuart0::RegisterBlock;
+
+pub trait SealedInstance {
+    fn info() -> Info;
+    fn index() -> usize;
+    fn buffered_state() -> &'static buffered::State;
+}
+
+pub struct Info {
+    pub regs: Regs,
+}
+
+/// Trait for LPUART peripheral instances
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType + 'static + Send + Gate<MrccPeriphConfig = LpuartConfig> {
+    const CLOCK_INSTANCE: crate::clocks::periph_helpers::LpuartInstance;
+    type Interrupt: interrupt::typelevel::Interrupt;
+    /// Type-safe DMA request source for TX
+    type TxDmaRequest: DmaRequest;
+    /// Type-safe DMA request source for RX
+    type RxDmaRequest: DmaRequest;
+}
+
+macro_rules! impl_instance {
+    ($($n:expr);* $(;)?) => {
+        $(
+            paste!{
+                impl SealedInstance for crate::peripherals::[<LPUART $n>] {
+                    fn info() -> Info {
+                        Info {
+                            regs: unsafe { &*pac::[<Lpuart $n>]::ptr() },
+                        }
+                    }
+
+                    #[inline]
+                    fn index() -> usize {
+                        $n
+                    }
+
+                    fn buffered_state() -> &'static buffered::State {
+                        static BUFFERED_STATE: buffered::State = buffered::State::new();
+                        &BUFFERED_STATE
+                    }
+                }
+
+                impl Instance for crate::peripherals::[<LPUART $n>] {
+                    const CLOCK_INSTANCE: crate::clocks::periph_helpers::LpuartInstance
+                        = crate::clocks::periph_helpers::LpuartInstance::[<Lpuart $n>];
+                    type Interrupt = crate::interrupt::typelevel::[<LPUART $n>];
+                    type TxDmaRequest = crate::dma::[<Lpuart $n TxRequest>];
+                    type RxDmaRequest = crate::dma::[<Lpuart $n RxRequest>];
+                }
+            }
+        )*
+    };
+}
+
+// DMA request sources are now type-safe via associated types.
+// The request source numbers are defined in src/dma.rs:
+// LPUART0: RX=21, TX=22 -> Lpuart0RxRequest, Lpuart0TxRequest
+// LPUART1: RX=23, TX=24 -> Lpuart1RxRequest, Lpuart1TxRequest
+// LPUART2: RX=25, TX=26 -> Lpuart2RxRequest, Lpuart2TxRequest
+// LPUART3: RX=27, TX=28 -> Lpuart3RxRequest, Lpuart3TxRequest
+// LPUART4: RX=29, TX=30 -> Lpuart4RxRequest, Lpuart4TxRequest
+// LPUART5: RX=31, TX=32 -> Lpuart5RxRequest, Lpuart5TxRequest
+impl_instance!(0; 1; 2; 3; 4; 5);
+
+// ============================================================================
+// INSTANCE HELPER FUNCTIONS
+// ============================================================================
+
+/// Perform software reset on the LPUART peripheral
+pub fn perform_software_reset(regs: Regs) {
+    // Software reset - set and clear RST bit (Global register)
+    regs.global().write(|w| w.rst().reset());
+    regs.global().write(|w| w.rst().no_effect());
+}
+
+/// Disable both transmitter and receiver
+pub fn disable_transceiver(regs: Regs) {
+    regs.ctrl().modify(|_, w| w.te().disabled().re().disabled());
+}
+
+/// Calculate and configure baudrate settings
+pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock_freq: u32) -> Result<()> {
+    let (osr, sbr) = calculate_baudrate(baudrate_bps, clock_freq)?;
+
+    // Configure BAUD register
+    regs.baud().modify(|_, w| unsafe {
+        // Clear and set OSR
+        w.osr().bits(osr - 1);
+        // Clear and set SBR
+        w.sbr().bits(sbr);
+        // Set BOTHEDGE if OSR is between 4 and 7
+        if osr > 3 && osr < 8 {
+            w.bothedge().enabled()
+        } else {
+            w.bothedge().disabled()
+        }
+    });
+
+    Ok(())
+}
+
+/// Configure frame format (stop bits, data bits)
+pub fn configure_frame_format(regs: Regs, config: &Config) {
+    // Configure stop bits
+    regs.baud().modify(|_, w| w.sbns().variant(config.stop_bits_count));
+
+    // Clear M10 for now (10-bit mode)
+    regs.baud().modify(|_, w| w.m10().disabled());
+}
+
+/// Configure control settings (parity, data bits, idle config, pin swap)
+pub fn configure_control_settings(regs: Regs, config: &Config) {
+    regs.ctrl().modify(|_, w| {
+        // Parity configuration
+        let mut w = if let Some(parity) = config.parity_mode {
+            w.pe().enabled().pt().variant(parity)
+        } else {
+            w.pe().disabled()
+        };
+
+        // Data bits configuration
+        w = match config.data_bits_count {
+            DataBits::Data8 => {
+                if config.parity_mode.is_some() {
+                    w.m().data9() // 8 data + 1 parity = 9 bits
+                } else {
+                    w.m().data8() // 8 data bits only
+                }
+            }
+            DataBits::Data9 => w.m().data9(),
+        };
+
+        // Idle configuration
+        w = w.idlecfg().variant(config.rx_idle_config);
+        w = w.ilt().variant(config.rx_idle_type);
+
+        // Swap TXD/RXD if configured
+        if config.swap_txd_rxd {
+            w.swap().swap()
+        } else {
+            w.swap().standard()
+        }
+    });
+}
+
+/// Configure FIFO settings and watermarks
+pub fn configure_fifo(regs: Regs, config: &Config) {
+    // Configure WATER register for FIFO watermarks
+    regs.water().write(|w| unsafe {
+        w.rxwater()
+            .bits(config.rx_fifo_watermark)
+            .txwater()
+            .bits(config.tx_fifo_watermark)
+    });
+
+    // Enable TX/RX FIFOs
+    regs.fifo().modify(|_, w| w.txfe().enabled().rxfe().enabled());
+
+    // Flush FIFOs
+    regs.fifo()
+        .modify(|_, w| w.txflush().txfifo_rst().rxflush().rxfifo_rst());
+}
+
+/// Clear all status flags
+pub fn clear_all_status_flags(regs: Regs) {
+    regs.stat().reset();
+}
+
+/// Configure hardware flow control if enabled
+pub fn configure_flow_control(regs: Regs, enable_tx_cts: bool, enable_rx_rts: bool, config: &Config) {
+    if enable_rx_rts || enable_tx_cts {
+        regs.modir().modify(|_, w| {
+            let mut w = w;
+
+            // Configure TX CTS
+            w = w.txctsc().variant(config.tx_cts_config);
+            w = w.txctssrc().variant(config.tx_cts_source);
+
+            if enable_rx_rts {
+                w = w.rxrtse().enabled();
+            } else {
+                w = w.rxrtse().disabled();
+            }
+
+            if enable_tx_cts {
+                w = w.txctse().enabled();
+            } else {
+                w = w.txctse().disabled();
+            }
+
+            w
+        });
+    }
+}
+
+/// Configure bit order (MSB first or LSB first)
+pub fn configure_bit_order(regs: Regs, msb_first: MsbFirst) {
+    regs.stat().modify(|_, w| w.msbf().variant(msb_first));
+}
+
+/// Enable transmitter and/or receiver based on configuration
+pub fn enable_transceiver(regs: Regs, enable_tx: bool, enable_rx: bool) {
+    regs.ctrl().modify(|_, w| {
+        let mut w = w;
+        if enable_tx {
+            w = w.te().enabled();
+        }
+        if enable_rx {
+            w = w.re().enabled();
+        }
+        w
+    });
+}
+
+pub fn calculate_baudrate(baudrate: u32, src_clock_hz: u32) -> Result<(u8, u16)> {
+    let mut baud_diff = baudrate;
+    let mut osr = 0u8;
+    let mut sbr = 0u16;
+
+    // Try OSR values from 4 to 32
+    for osr_temp in 4u8..=32u8 {
+        // Calculate SBR: (srcClock_Hz * 2 / (baudRate * osr) + 1) / 2
+        let sbr_calc = ((src_clock_hz * 2) / (baudrate * osr_temp as u32)).div_ceil(2);
+
+        let sbr_temp = if sbr_calc == 0 {
+            1
+        } else if sbr_calc > 0x1FFF {
+            0x1FFF
+        } else {
+            sbr_calc as u16
+        };
+
+        // Calculate actual baud rate
+        let calculated_baud = src_clock_hz / (osr_temp as u32 * sbr_temp as u32);
+
+        let temp_diff = calculated_baud.abs_diff(baudrate);
+
+        if temp_diff <= baud_diff {
+            baud_diff = temp_diff;
+            osr = osr_temp;
+            sbr = sbr_temp;
+        }
+    }
+
+    // Check if baud rate difference is within 3%
+    if baud_diff > (baudrate / 100) * 3 {
+        return Err(Error::UnsupportedBaudrate);
+    }
+
+    Ok((osr, sbr))
+}
+
+/// Wait for all transmit operations to complete
+pub fn wait_for_tx_complete(regs: Regs) {
+    // Wait for TX FIFO to empty
+    while regs.water().read().txcount().bits() != 0 {
+        // Wait for TX FIFO to drain
+    }
+
+    // Wait for last character to shift out (TC = Transmission Complete)
+    while regs.stat().read().tc().is_active() {
+        // Wait for transmission to complete
+    }
+}
+
+pub fn check_and_clear_rx_errors(regs: Regs) -> Result<()> {
+    let stat = regs.stat().read();
+    let mut status = Ok(());
+
+    // Check for overrun first - other error flags are prevented when OR is set
+    if stat.or().is_overrun() {
+        regs.stat().write(|w| w.or().clear_bit_by_one());
+
+        return Err(Error::Overrun);
+    }
+
+    if stat.pf().is_parity() {
+        regs.stat().write(|w| w.pf().clear_bit_by_one());
+        status = Err(Error::Parity);
+    }
+
+    if stat.fe().is_error() {
+        regs.stat().write(|w| w.fe().clear_bit_by_one());
+        status = Err(Error::Framing);
+    }
+
+    if stat.nf().is_noise() {
+        regs.stat().write(|w| w.nf().clear_bit_by_one());
+        status = Err(Error::Noise);
+    }
+
+    status
+}
+
+pub fn has_data(regs: Regs) -> bool {
+    if regs.param().read().rxfifo().bits() > 0 {
+        // FIFO is available - check RXCOUNT in WATER register
+        regs.water().read().rxcount().bits() > 0
+    } else {
+        // No FIFO - check RDRF flag in STAT register
+        regs.stat().read().rdrf().is_rxdata()
+    }
+}
+
+// ============================================================================
+// PIN TRAITS FOR LPUART FUNCTIONALITY
+// ============================================================================
+
+impl<T: SealedPin> sealed::Sealed for T {}
+
+/// io configuration trait for Lpuart Tx configuration
+pub trait TxPin<T: Instance>: Into<AnyPin> + sealed::Sealed + PeripheralType {
+    /// convert the pin to appropriate function for Lpuart Tx  usage
+    fn as_tx(&self);
+}
+
+/// io configuration trait for Lpuart Rx configuration
+pub trait RxPin<T: Instance>: Into<AnyPin> + sealed::Sealed + PeripheralType {
+    /// convert the pin to appropriate function for Lpuart Rx  usage
+    fn as_rx(&self);
+}
+
+/// io configuration trait for Lpuart Cts
+pub trait CtsPin<T: Instance>: Into<AnyPin> + sealed::Sealed + PeripheralType {
+    /// convert the pin to appropriate function for Lpuart Cts usage
+    fn as_cts(&self);
+}
+
+/// io configuration trait for Lpuart Rts
+pub trait RtsPin<T: Instance>: Into<AnyPin> + sealed::Sealed + PeripheralType {
+    /// convert the pin to appropriate function for Lpuart Rts usage
+    fn as_rts(&self);
+}
+
+macro_rules! impl_tx_pin {
+    ($inst:ident, $pin:ident, $alt:ident) => {
+        impl TxPin<crate::peripherals::$inst> for crate::peripherals::$pin {
+            fn as_tx(&self) {
+                // TODO: Check these are right
+                self.set_pull(crate::gpio::Pull::Up);
+                self.set_slew_rate(crate::gpio::SlewRate::Fast.into());
+                self.set_drive_strength(crate::gpio::DriveStrength::Double.into());
+                self.set_function(crate::pac::port0::pcr0::Mux::$alt);
+                self.set_enable_input_buffer();
+            }
+        }
+    };
+}
+
+macro_rules! impl_rx_pin {
+    ($inst:ident, $pin:ident, $alt:ident) => {
+        impl RxPin<crate::peripherals::$inst> for crate::peripherals::$pin {
+            fn as_rx(&self) {
+                // TODO: Check these are right
+                self.set_pull(crate::gpio::Pull::Up);
+                self.set_slew_rate(crate::gpio::SlewRate::Fast.into());
+                self.set_drive_strength(crate::gpio::DriveStrength::Double.into());
+                self.set_function(crate::pac::port0::pcr0::Mux::$alt);
+                self.set_enable_input_buffer();
+            }
+        }
+    };
+}
+
+// TODO: Macro and impls for CTS/RTS pins
+macro_rules! impl_cts_pin {
+    ($inst:ident, $pin:ident, $alt:ident) => {
+        impl CtsPin<crate::peripherals::$inst> for crate::peripherals::$pin {
+            fn as_cts(&self) {
+                todo!()
+            }
+        }
+    };
+}
+
+macro_rules! impl_rts_pin {
+    ($inst:ident, $pin:ident, $alt:ident) => {
+        impl RtsPin<crate::peripherals::$inst> for crate::peripherals::$pin {
+            fn as_rts(&self) {
+                todo!()
+            }
+        }
+    };
+}
+
+// LPUART 0
+impl_tx_pin!(LPUART0, P0_3, Mux2);
+impl_tx_pin!(LPUART0, P0_21, Mux3);
+impl_tx_pin!(LPUART0, P2_1, Mux2);
+
+impl_rx_pin!(LPUART0, P0_2, Mux2);
+impl_rx_pin!(LPUART0, P0_20, Mux3);
+impl_rx_pin!(LPUART0, P2_0, Mux2);
+
+impl_cts_pin!(LPUART0, P0_1, Mux2);
+impl_cts_pin!(LPUART0, P0_23, Mux3);
+impl_cts_pin!(LPUART0, P2_3, Mux2);
+
+impl_rts_pin!(LPUART0, P0_0, Mux2);
+impl_rts_pin!(LPUART0, P0_22, Mux3);
+impl_rts_pin!(LPUART0, P2_2, Mux2);
+
+// LPUART 1
+impl_tx_pin!(LPUART1, P1_9, Mux2);
+impl_tx_pin!(LPUART1, P2_13, Mux3);
+impl_tx_pin!(LPUART1, P3_9, Mux3);
+impl_tx_pin!(LPUART1, P3_21, Mux3);
+
+impl_rx_pin!(LPUART1, P1_8, Mux2);
+impl_rx_pin!(LPUART1, P2_12, Mux3);
+impl_rx_pin!(LPUART1, P3_8, Mux3);
+impl_rx_pin!(LPUART1, P3_20, Mux3);
+
+impl_cts_pin!(LPUART1, P1_11, Mux2);
+impl_cts_pin!(LPUART1, P2_17, Mux3);
+impl_cts_pin!(LPUART1, P3_11, Mux3);
+impl_cts_pin!(LPUART1, P3_23, Mux3);
+
+impl_rts_pin!(LPUART1, P1_10, Mux2);
+impl_rts_pin!(LPUART1, P2_15, Mux3);
+impl_rts_pin!(LPUART1, P2_16, Mux3);
+impl_rts_pin!(LPUART1, P3_10, Mux3);
+
+// LPUART 2
+impl_tx_pin!(LPUART2, P1_5, Mux3);
+impl_tx_pin!(LPUART2, P1_13, Mux3);
+impl_tx_pin!(LPUART2, P2_2, Mux3);
+impl_tx_pin!(LPUART2, P2_10, Mux3);
+impl_tx_pin!(LPUART2, P3_15, Mux2);
+
+impl_rx_pin!(LPUART2, P1_4, Mux3);
+impl_rx_pin!(LPUART2, P1_12, Mux3);
+impl_rx_pin!(LPUART2, P2_3, Mux3);
+impl_rx_pin!(LPUART2, P2_11, Mux3);
+impl_rx_pin!(LPUART2, P3_14, Mux2);
+
+impl_cts_pin!(LPUART2, P1_7, Mux3);
+impl_cts_pin!(LPUART2, P1_15, Mux3);
+impl_cts_pin!(LPUART2, P2_4, Mux3);
+impl_cts_pin!(LPUART2, P3_13, Mux2);
+
+impl_rts_pin!(LPUART2, P1_6, Mux3);
+impl_rts_pin!(LPUART2, P1_14, Mux3);
+impl_rts_pin!(LPUART2, P2_5, Mux3);
+impl_rts_pin!(LPUART2, P3_12, Mux2);
+
+// LPUART 3
+impl_tx_pin!(LPUART3, P3_1, Mux3);
+impl_tx_pin!(LPUART3, P3_12, Mux3);
+impl_tx_pin!(LPUART3, P4_5, Mux3);
+
+impl_rx_pin!(LPUART3, P3_0, Mux3);
+impl_rx_pin!(LPUART3, P3_13, Mux3);
+impl_rx_pin!(LPUART3, P4_2, Mux3);
+
+impl_cts_pin!(LPUART3, P3_7, Mux3);
+impl_cts_pin!(LPUART3, P3_14, Mux3);
+impl_cts_pin!(LPUART3, P4_6, Mux3);
+
+impl_rts_pin!(LPUART3, P3_6, Mux3);
+impl_rts_pin!(LPUART3, P3_15, Mux3);
+impl_rts_pin!(LPUART3, P4_7, Mux3);
+
+// LPUART 4
+impl_tx_pin!(LPUART4, P2_7, Mux3);
+impl_tx_pin!(LPUART4, P3_19, Mux2);
+impl_tx_pin!(LPUART4, P3_27, Mux3);
+impl_tx_pin!(LPUART4, P4_3, Mux3);
+
+impl_rx_pin!(LPUART4, P2_6, Mux3);
+impl_rx_pin!(LPUART4, P3_18, Mux2);
+impl_rx_pin!(LPUART4, P3_28, Mux3);
+impl_rx_pin!(LPUART4, P4_4, Mux3);
+
+impl_cts_pin!(LPUART4, P2_0, Mux3);
+impl_cts_pin!(LPUART4, P3_17, Mux2);
+impl_cts_pin!(LPUART4, P3_31, Mux3);
+
+impl_rts_pin!(LPUART4, P2_1, Mux3);
+impl_rts_pin!(LPUART4, P3_16, Mux2);
+impl_rts_pin!(LPUART4, P3_30, Mux3);
+
+// LPUART 5
+impl_tx_pin!(LPUART5, P1_10, Mux8);
+impl_tx_pin!(LPUART5, P1_17, Mux8);
+
+impl_rx_pin!(LPUART5, P1_11, Mux8);
+impl_rx_pin!(LPUART5, P1_16, Mux8);
+
+impl_cts_pin!(LPUART5, P1_12, Mux8);
+impl_cts_pin!(LPUART5, P1_19, Mux8);
+
+impl_rts_pin!(LPUART5, P1_13, Mux8);
+impl_rts_pin!(LPUART5, P1_18, Mux8);
+
+// ============================================================================
+// ERROR TYPES AND RESULTS
+// ============================================================================
+
+/// LPUART error types
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    /// Read error
+    Read,
+    /// Buffer overflow
+    Overrun,
+    /// Noise error
+    Noise,
+    /// Framing error
+    Framing,
+    /// Parity error
+    Parity,
+    /// Failure
+    Fail,
+    /// Invalid argument
+    InvalidArgument,
+    /// Lpuart baud rate cannot be supported with the given clock
+    UnsupportedBaudrate,
+    /// RX FIFO Empty
+    RxFifoEmpty,
+    /// TX FIFO Full
+    TxFifoFull,
+    /// TX Busy
+    TxBusy,
+    /// Clock Error
+    ClockSetup(ClockError),
+}
+
+/// A specialized Result type for LPUART operations
+pub type Result<T> = core::result::Result<T, Error>;
+
+// ============================================================================
+// CONFIGURATION STRUCTURES
+// ============================================================================
+
+/// Lpuart config
+#[derive(Debug, Clone, Copy)]
+pub struct Config {
+    /// Power state required for this peripheral
+    pub power: PoweredClock,
+    /// Clock source
+    pub source: LpuartClockSel,
+    /// Clock divisor
+    pub div: Div4,
+    /// Baud rate in bits per second
+    pub baudrate_bps: u32,
+    /// Parity configuration
+    pub parity_mode: Option<Parity>,
+    /// Number of data bits
+    pub data_bits_count: DataBits,
+    /// MSB First or LSB First configuration
+    pub msb_first: MsbFirst,
+    /// Number of stop bits
+    pub stop_bits_count: StopBits,
+    /// TX FIFO watermark
+    pub tx_fifo_watermark: u8,
+    /// RX FIFO watermark
+    pub rx_fifo_watermark: u8,
+    /// TX CTS source
+    pub tx_cts_source: TxCtsSource,
+    /// TX CTS configure
+    pub tx_cts_config: TxCtsConfig,
+    /// RX IDLE type
+    pub rx_idle_type: IdleType,
+    /// RX IDLE configuration
+    pub rx_idle_config: IdleConfig,
+    /// Swap TXD and RXD pins
+    pub swap_txd_rxd: bool,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            baudrate_bps: 115_200u32,
+            parity_mode: None,
+            data_bits_count: DataBits::Data8,
+            msb_first: MsbFirst::LsbFirst,
+            stop_bits_count: StopBits::One,
+            tx_fifo_watermark: 0,
+            rx_fifo_watermark: 1,
+            tx_cts_source: TxCtsSource::Cts,
+            tx_cts_config: TxCtsConfig::Start,
+            rx_idle_type: IdleType::FromStart,
+            rx_idle_config: IdleConfig::Idle1,
+            swap_txd_rxd: false,
+            power: PoweredClock::NormalEnabledDeepSleepDisabled,
+            source: LpuartClockSel::FroLfDiv,
+            div: Div4::no_div(),
+        }
+    }
+}
+
+/// LPUART status flags
+#[derive(Debug, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct Status {
+    /// Transmit data register empty
+    pub tx_empty: bool,
+    /// Transmission complete
+    pub tx_complete: bool,
+    /// Receive data register full
+    pub rx_full: bool,
+    /// Idle line detected
+    pub idle: bool,
+    /// Receiver overrun
+    pub overrun: bool,
+    /// Noise error
+    pub noise: bool,
+    /// Framing error
+    pub framing: bool,
+    /// Parity error
+    pub parity: bool,
+}
+
+// ============================================================================
+// MODE TRAITS (BLOCKING/ASYNC)
+// ============================================================================
+
+/// Driver move trait.
+#[allow(private_bounds)]
+pub trait Mode: sealed::Sealed {}
+
+/// Blocking mode.
+pub struct Blocking;
+impl sealed::Sealed for Blocking {}
+impl Mode for Blocking {}
+
+/// Async mode.
+pub struct Async;
+impl sealed::Sealed for Async {}
+impl Mode for Async {}
+
+// ============================================================================
+// CORE DRIVER STRUCTURES
+// ============================================================================
+
+/// Lpuart driver.
+pub struct Lpuart<'a, M: Mode> {
+    info: Info,
+    tx: LpuartTx<'a, M>,
+    rx: LpuartRx<'a, M>,
+}
+
+/// Lpuart TX driver.
+pub struct LpuartTx<'a, M: Mode> {
+    info: Info,
+    _tx_pin: Peri<'a, AnyPin>,
+    _cts_pin: Option<Peri<'a, AnyPin>>,
+    mode: PhantomData<(&'a (), M)>,
+}
+
+/// Lpuart Rx driver.
+pub struct LpuartRx<'a, M: Mode> {
+    info: Info,
+    _rx_pin: Peri<'a, AnyPin>,
+    _rts_pin: Option<Peri<'a, AnyPin>>,
+    mode: PhantomData<(&'a (), M)>,
+}
+
+/// Lpuart TX driver with DMA support.
+pub struct LpuartTxDma<'a, T: Instance, C: DmaChannelTrait> {
+    info: Info,
+    _tx_pin: Peri<'a, AnyPin>,
+    tx_dma: DmaChannel<C>,
+    _instance: core::marker::PhantomData<T>,
+}
+
+/// Lpuart RX driver with DMA support.
+pub struct LpuartRxDma<'a, T: Instance, C: DmaChannelTrait> {
+    info: Info,
+    _rx_pin: Peri<'a, AnyPin>,
+    rx_dma: DmaChannel<C>,
+    _instance: core::marker::PhantomData<T>,
+}
+
+/// Lpuart driver with DMA support for both TX and RX.
+pub struct LpuartDma<'a, T: Instance, TxC: DmaChannelTrait, RxC: DmaChannelTrait> {
+    tx: LpuartTxDma<'a, T, TxC>,
+    rx: LpuartRxDma<'a, T, RxC>,
+}
+
+/// Lpuart RX driver with ring-buffered DMA support.
+pub struct LpuartRxRingDma<'peri, 'ring, T: Instance, C: DmaChannelTrait> {
+    _inner: LpuartRxDma<'peri, T, C>,
+    ring: RingBuffer<'ring, u8>,
+}
+
+// ============================================================================
+// LPUART CORE IMPLEMENTATION
+// ============================================================================
+
+impl<'a, M: Mode> Lpuart<'a, M> {
+    fn init<T: Instance>(
+        enable_tx: bool,
+        enable_rx: bool,
+        enable_tx_cts: bool,
+        enable_rx_rts: bool,
+        config: Config,
+    ) -> Result<()> {
+        let regs = T::info().regs;
+
+        // Enable clocks
+        let conf = LpuartConfig {
+            power: config.power,
+            source: config.source,
+            div: config.div,
+            instance: T::CLOCK_INSTANCE,
+        };
+        let clock_freq = unsafe { enable_and_reset::<T>(&conf).map_err(Error::ClockSetup)? };
+
+        // Perform initialization sequence
+        perform_software_reset(regs);
+        disable_transceiver(regs);
+        configure_baudrate(regs, config.baudrate_bps, clock_freq)?;
+        configure_frame_format(regs, &config);
+        configure_control_settings(regs, &config);
+        configure_fifo(regs, &config);
+        clear_all_status_flags(regs);
+        configure_flow_control(regs, enable_tx_cts, enable_rx_rts, &config);
+        configure_bit_order(regs, config.msb_first);
+        enable_transceiver(regs, enable_rx, enable_tx);
+
+        Ok(())
+    }
+
+    /// Deinitialize the LPUART peripheral
+    pub fn deinit(&self) -> Result<()> {
+        let regs = self.info.regs;
+
+        // Wait for TX operations to complete
+        wait_for_tx_complete(regs);
+
+        // Clear all status flags
+        clear_all_status_flags(regs);
+
+        // Disable the module - clear all CTRL register bits
+        regs.ctrl().reset();
+
+        Ok(())
+    }
+
+    /// Split the Lpuart into a transmitter and receiver
+    pub fn split(self) -> (LpuartTx<'a, M>, LpuartRx<'a, M>) {
+        (self.tx, self.rx)
+    }
+
+    /// Split the Lpuart into a transmitter and receiver by mutable reference
+    pub fn split_ref(&mut self) -> (&mut LpuartTx<'a, M>, &mut LpuartRx<'a, M>) {
+        (&mut self.tx, &mut self.rx)
+    }
+}
+
+// ============================================================================
+// BLOCKING MODE IMPLEMENTATIONS
+// ============================================================================
+
+impl<'a> Lpuart<'a, Blocking> {
+    /// Create a new blocking LPUART instance with RX/TX pins.
+    pub fn new_blocking<T: Instance>(
+        _inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        config: Config,
+    ) -> Result<Self> {
+        // Configure the pins for LPUART usage
+        tx_pin.as_tx();
+        rx_pin.as_rx();
+
+        // Initialize the peripheral
+        Self::init::<T>(true, true, false, false, config)?;
+
+        Ok(Self {
+            info: T::info(),
+            tx: LpuartTx::new_inner(T::info(), tx_pin.into(), None),
+            rx: LpuartRx::new_inner(T::info(), rx_pin.into(), None),
+        })
+    }
+
+    /// Create a new blocking LPUART instance with RX, TX and RTS/CTS flow control pins
+    pub fn new_blocking_with_rtscts<T: Instance>(
+        _inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        cts_pin: Peri<'a, impl CtsPin<T>>,
+        rts_pin: Peri<'a, impl RtsPin<T>>,
+        config: Config,
+    ) -> Result<Self> {
+        // Configure the pins for LPUART usage
+        rx_pin.as_rx();
+        tx_pin.as_tx();
+        rts_pin.as_rts();
+        cts_pin.as_cts();
+
+        // Initialize the peripheral with flow control
+        Self::init::<T>(true, true, true, true, config)?;
+
+        Ok(Self {
+            info: T::info(),
+            rx: LpuartRx::new_inner(T::info(), rx_pin.into(), Some(rts_pin.into())),
+            tx: LpuartTx::new_inner(T::info(), tx_pin.into(), Some(cts_pin.into())),
+        })
+    }
+}
+
+// ----------------------------------------------------------------------------
+// Blocking TX Implementation
+// ----------------------------------------------------------------------------
+
+impl<'a, M: Mode> LpuartTx<'a, M> {
+    fn new_inner(info: Info, tx_pin: Peri<'a, AnyPin>, cts_pin: Option<Peri<'a, AnyPin>>) -> Self {
+        Self {
+            info,
+            _tx_pin: tx_pin,
+            _cts_pin: cts_pin,
+            mode: PhantomData,
+        }
+    }
+}
+
+impl<'a> LpuartTx<'a, Blocking> {
+    /// Create a new blocking LPUART transmitter instance
+    pub fn new_blocking<T: Instance>(
+        _inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        config: Config,
+    ) -> Result<Self> {
+        // Configure the pins for LPUART usage
+        tx_pin.as_tx();
+
+        // Initialize the peripheral
+        Lpuart::<Blocking>::init::<T>(true, false, false, false, config)?;
+
+        Ok(Self::new_inner(T::info(), tx_pin.into(), None))
+    }
+
+    /// Create a new blocking LPUART transmitter instance with CTS flow control
+    pub fn new_blocking_with_cts<T: Instance>(
+        _inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        cts_pin: Peri<'a, impl CtsPin<T>>,
+        config: Config,
+    ) -> Result<Self> {
+        tx_pin.as_tx();
+        cts_pin.as_cts();
+
+        Lpuart::<Blocking>::init::<T>(true, false, true, false, config)?;
+
+        Ok(Self::new_inner(T::info(), tx_pin.into(), Some(cts_pin.into())))
+    }
+
+    fn write_byte_internal(&mut self, byte: u8) -> Result<()> {
+        self.info.regs.data().modify(|_, w| unsafe { w.bits(u32::from(byte)) });
+
+        Ok(())
+    }
+
+    fn blocking_write_byte(&mut self, byte: u8) -> Result<()> {
+        while self.info.regs.stat().read().tdre().is_txdata() {}
+        self.write_byte_internal(byte)
+    }
+
+    fn write_byte(&mut self, byte: u8) -> Result<()> {
+        if self.info.regs.stat().read().tdre().is_txdata() {
+            Err(Error::TxFifoFull)
+        } else {
+            self.write_byte_internal(byte)
+        }
+    }
+
+    /// Write data to LPUART TX blocking execution until all data is sent.
+    pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> {
+        for x in buf {
+            self.blocking_write_byte(*x)?;
+        }
+
+        Ok(())
+    }
+
+    pub fn write_str_blocking(&mut self, buf: &str) {
+        let _ = self.blocking_write(buf.as_bytes());
+    }
+
+    /// Write data to LPUART TX without blocking.
+    pub fn write(&mut self, buf: &[u8]) -> Result<()> {
+        for x in buf {
+            self.write_byte(*x)?;
+        }
+
+        Ok(())
+    }
+
+    /// Flush LPUART TX blocking execution until all data has been transmitted.
+    pub fn blocking_flush(&mut self) -> Result<()> {
+        while self.info.regs.water().read().txcount().bits() != 0 {
+            // Wait for TX FIFO to drain
+        }
+
+        // Wait for last character to shift out
+        while self.info.regs.stat().read().tc().is_active() {
+            // Wait for transmission to complete
+        }
+
+        Ok(())
+    }
+
+    /// Flush LPUART TX.
+    pub fn flush(&mut self) -> Result<()> {
+        // Check if TX FIFO is empty
+        if self.info.regs.water().read().txcount().bits() != 0 {
+            return Err(Error::TxBusy);
+        }
+
+        // Check if transmission is complete
+        if self.info.regs.stat().read().tc().is_active() {
+            return Err(Error::TxBusy);
+        }
+
+        Ok(())
+    }
+}
+
+// ----------------------------------------------------------------------------
+// Blocking RX Implementation
+// ----------------------------------------------------------------------------
+
+impl<'a, M: Mode> LpuartRx<'a, M> {
+    fn new_inner(info: Info, rx_pin: Peri<'a, AnyPin>, rts_pin: Option<Peri<'a, AnyPin>>) -> Self {
+        Self {
+            info,
+            _rx_pin: rx_pin,
+            _rts_pin: rts_pin,
+            mode: PhantomData,
+        }
+    }
+}
+
+impl<'a> LpuartRx<'a, Blocking> {
+    /// Create a new blocking LPUART Receiver instance
+    pub fn new_blocking<T: Instance>(
+        _inner: Peri<'a, T>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        config: Config,
+    ) -> Result<Self> {
+        rx_pin.as_rx();
+
+        Lpuart::<Blocking>::init::<T>(false, true, false, false, config)?;
+
+        Ok(Self::new_inner(T::info(), rx_pin.into(), None))
+    }
+
+    /// Create a new blocking LPUART Receiver instance with RTS flow control
+    pub fn new_blocking_with_rts<T: Instance>(
+        _inner: Peri<'a, T>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        rts_pin: Peri<'a, impl RtsPin<T>>,
+        config: Config,
+    ) -> Result<Self> {
+        rx_pin.as_rx();
+        rts_pin.as_rts();
+
+        Lpuart::<Blocking>::init::<T>(false, true, false, true, config)?;
+
+        Ok(Self::new_inner(T::info(), rx_pin.into(), Some(rts_pin.into())))
+    }
+
+    fn read_byte_internal(&mut self) -> Result<u8> {
+        let data = self.info.regs.data().read();
+
+        Ok((data.bits() & 0xFF) as u8)
+    }
+
+    fn read_byte(&mut self) -> Result<u8> {
+        check_and_clear_rx_errors(self.info.regs)?;
+
+        if !has_data(self.info.regs) {
+            return Err(Error::RxFifoEmpty);
+        }
+
+        self.read_byte_internal()
+    }
+
+    fn blocking_read_byte(&mut self) -> Result<u8> {
+        loop {
+            if has_data(self.info.regs) {
+                return self.read_byte_internal();
+            }
+
+            check_and_clear_rx_errors(self.info.regs)?;
+        }
+    }
+
+    /// Read data from LPUART RX without blocking.
+    pub fn read(&mut self, buf: &mut [u8]) -> Result<()> {
+        for byte in buf.iter_mut() {
+            *byte = self.read_byte()?;
+        }
+        Ok(())
+    }
+
+    /// Read data from LPUART RX blocking execution until the buffer is filled.
+    pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> {
+        for byte in buf.iter_mut() {
+            *byte = self.blocking_read_byte()?;
+        }
+        Ok(())
+    }
+}
+
+impl<'a> Lpuart<'a, Blocking> {
+    /// Read data from LPUART RX blocking execution until the buffer is filled
+    pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> {
+        self.rx.blocking_read(buf)
+    }
+
+    /// Read data from LPUART RX without blocking
+    pub fn read(&mut self, buf: &mut [u8]) -> Result<()> {
+        self.rx.read(buf)
+    }
+
+    /// Write data to LPUART TX blocking execution until all data is sent
+    pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> {
+        self.tx.blocking_write(buf)
+    }
+
+    pub fn write_byte(&mut self, byte: u8) -> Result<()> {
+        self.tx.write_byte(byte)
+    }
+
+    pub fn read_byte_blocking(&mut self) -> u8 {
+        loop {
+            if let Ok(b) = self.rx.read_byte() {
+                return b;
+            }
+        }
+    }
+
+    pub fn write_str_blocking(&mut self, buf: &str) {
+        self.tx.write_str_blocking(buf);
+    }
+
+    /// Write data to LPUART TX without blocking
+    pub fn write(&mut self, buf: &[u8]) -> Result<()> {
+        self.tx.write(buf)
+    }
+
+    /// Flush LPUART TX blocking execution until all data has been transmitted
+    pub fn blocking_flush(&mut self) -> Result<()> {
+        self.tx.blocking_flush()
+    }
+
+    /// Flush LPUART TX without blocking
+    pub fn flush(&mut self) -> Result<()> {
+        self.tx.flush()
+    }
+}
+
+// ============================================================================
+// ASYNC MODE IMPLEMENTATIONS (DMA-based)
+// ============================================================================
+
+/// Guard struct that ensures DMA is stopped if the async future is cancelled.
+///
+/// This implements the RAII pattern: if the future is dropped before completion
+/// (e.g., due to a timeout), the DMA transfer is automatically aborted to prevent
+/// use-after-free when the buffer goes out of scope.
+struct TxDmaGuard<'a, C: DmaChannelTrait> {
+    dma: &'a DmaChannel<C>,
+    regs: Regs,
+}
+
+impl<'a, C: DmaChannelTrait> TxDmaGuard<'a, C> {
+    fn new(dma: &'a DmaChannel<C>, regs: Regs) -> Self {
+        Self { dma, regs }
+    }
+
+    /// Complete the transfer normally (don't abort on drop).
+    fn complete(self) {
+        // Cleanup
+        self.regs.baud().modify(|_, w| w.tdmae().disabled());
+        unsafe {
+            self.dma.disable_request();
+            self.dma.clear_done();
+        }
+        // Don't run drop since we've cleaned up
+        core::mem::forget(self);
+    }
+}
+
+impl<C: DmaChannelTrait> Drop for TxDmaGuard<'_, C> {
+    fn drop(&mut self) {
+        // Abort the DMA transfer if still running
+        unsafe {
+            self.dma.disable_request();
+            self.dma.clear_done();
+            self.dma.clear_interrupt();
+        }
+        // Disable UART TX DMA request
+        self.regs.baud().modify(|_, w| w.tdmae().disabled());
+    }
+}
+
+/// Guard struct for RX DMA transfers.
+struct RxDmaGuard<'a, C: DmaChannelTrait> {
+    dma: &'a DmaChannel<C>,
+    regs: Regs,
+}
+
+impl<'a, C: DmaChannelTrait> RxDmaGuard<'a, C> {
+    fn new(dma: &'a DmaChannel<C>, regs: Regs) -> Self {
+        Self { dma, regs }
+    }
+
+    /// Complete the transfer normally (don't abort on drop).
+    fn complete(self) {
+        // Ensure DMA writes are visible to CPU
+        cortex_m::asm::dsb();
+        // Cleanup
+        self.regs.baud().modify(|_, w| w.rdmae().disabled());
+        unsafe {
+            self.dma.disable_request();
+            self.dma.clear_done();
+        }
+        // Don't run drop since we've cleaned up
+        core::mem::forget(self);
+    }
+}
+
+impl<C: DmaChannelTrait> Drop for RxDmaGuard<'_, C> {
+    fn drop(&mut self) {
+        // Abort the DMA transfer if still running
+        unsafe {
+            self.dma.disable_request();
+            self.dma.clear_done();
+            self.dma.clear_interrupt();
+        }
+        // Disable UART RX DMA request
+        self.regs.baud().modify(|_, w| w.rdmae().disabled());
+    }
+}
+
+impl<'a, T: Instance, C: DmaChannelTrait> LpuartTxDma<'a, T, C> {
+    /// Create a new LPUART TX driver with DMA support.
+    pub fn new(
+        _inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        tx_dma_ch: Peri<'a, C>,
+        config: Config,
+    ) -> Result<Self> {
+        tx_pin.as_tx();
+        let tx_pin: Peri<'a, AnyPin> = tx_pin.into();
+
+        // Initialize LPUART with TX enabled, RX disabled, no flow control
+        Lpuart::<Async>::init::<T>(true, false, false, false, config)?;
+
+        // Enable interrupt
+        let tx_dma = DmaChannel::new(tx_dma_ch);
+        tx_dma.enable_interrupt();
+
+        Ok(Self {
+            info: T::info(),
+            _tx_pin: tx_pin,
+            tx_dma,
+            _instance: core::marker::PhantomData,
+        })
+    }
+
+    /// Write data using DMA.
+    ///
+    /// This configures the DMA channel for a memory-to-peripheral transfer
+    /// and waits for completion asynchronously. Large buffers are automatically
+    /// split into chunks that fit within the DMA transfer limit.
+    ///
+    /// The DMA request source is automatically derived from the LPUART instance type.
+    ///
+    /// # Safety
+    ///
+    /// If the returned future is dropped before completion (e.g., due to a timeout),
+    /// the DMA transfer is automatically aborted to prevent use-after-free.
+    ///
+    /// # Arguments
+    /// * `buf` - Data buffer to transmit
+    pub async fn write_dma(&mut self, buf: &[u8]) -> Result<usize> {
+        if buf.is_empty() {
+            return Ok(0);
+        }
+
+        let mut total = 0;
+        for chunk in buf.chunks(DMA_MAX_TRANSFER_SIZE) {
+            total += self.write_dma_inner(chunk).await?;
+        }
+
+        Ok(total)
+    }
+
+    /// Internal helper to write a single chunk (max 0x7FFF bytes) using DMA.
+    async fn write_dma_inner(&mut self, buf: &[u8]) -> Result<usize> {
+        let len = buf.len();
+        let peri_addr = self.info.regs.data().as_ptr() as *mut u8;
+
+        unsafe {
+            // Clean up channel state
+            self.tx_dma.disable_request();
+            self.tx_dma.clear_done();
+            self.tx_dma.clear_interrupt();
+
+            // Set DMA request source from instance type (type-safe)
+            self.tx_dma.set_request_source::<T::TxDmaRequest>();
+
+            // Configure TCD for memory-to-peripheral transfer
+            self.tx_dma
+                .setup_write_to_peripheral(buf, peri_addr, EnableInterrupt::Yes);
+
+            // Enable UART TX DMA request
+            self.info.regs.baud().modify(|_, w| w.tdmae().enabled());
+
+            // Enable DMA channel request
+            self.tx_dma.enable_request();
+        }
+
+        // Create guard that will abort DMA if this future is dropped
+        let guard = TxDmaGuard::new(&self.tx_dma, self.info.regs);
+
+        // Wait for completion asynchronously
+        core::future::poll_fn(|cx| {
+            self.tx_dma.waker().register(cx.waker());
+            if self.tx_dma.is_done() {
+                core::task::Poll::Ready(())
+            } else {
+                core::task::Poll::Pending
+            }
+        })
+        .await;
+
+        // Transfer completed successfully - clean up without aborting
+        guard.complete();
+
+        Ok(len)
+    }
+
+    /// Blocking write (fallback when DMA is not needed)
+    pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> {
+        for &byte in buf {
+            while self.info.regs.stat().read().tdre().is_txdata() {}
+            self.info.regs.data().modify(|_, w| unsafe { w.bits(u32::from(byte)) });
+        }
+        Ok(())
+    }
+
+    /// Flush TX blocking
+    pub fn blocking_flush(&mut self) -> Result<()> {
+        while self.info.regs.water().read().txcount().bits() != 0 {}
+        while self.info.regs.stat().read().tc().is_active() {}
+        Ok(())
+    }
+}
+
+impl<'a, T: Instance, C: DmaChannelTrait> LpuartRxDma<'a, T, C> {
+    /// Create a new LPUART RX driver with DMA support.
+    pub fn new(
+        _inner: Peri<'a, T>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        rx_dma_ch: Peri<'a, C>,
+        config: Config,
+    ) -> Result<Self> {
+        rx_pin.as_rx();
+        let rx_pin: Peri<'a, AnyPin> = rx_pin.into();
+
+        // Initialize LPUART with TX disabled, RX enabled, no flow control
+        Lpuart::<Async>::init::<T>(false, true, false, false, config)?;
+
+        // Enable dma interrupt
+        let rx_dma = DmaChannel::new(rx_dma_ch);
+        rx_dma.enable_interrupt();
+
+        Ok(Self {
+            info: T::info(),
+            _rx_pin: rx_pin,
+            rx_dma,
+            _instance: core::marker::PhantomData,
+        })
+    }
+
+    /// Read data using DMA.
+    ///
+    /// This configures the DMA channel for a peripheral-to-memory transfer
+    /// and waits for completion asynchronously. Large buffers are automatically
+    /// split into chunks that fit within the DMA transfer limit.
+    ///
+    /// The DMA request source is automatically derived from the LPUART instance type.
+    ///
+    /// # Safety
+    ///
+    /// If the returned future is dropped before completion (e.g., due to a timeout),
+    /// the DMA transfer is automatically aborted to prevent use-after-free.
+    ///
+    /// # Arguments
+    /// * `buf` - Buffer to receive data into
+    pub async fn read_dma(&mut self, buf: &mut [u8]) -> Result<usize> {
+        if buf.is_empty() {
+            return Ok(0);
+        }
+
+        let mut total = 0;
+        for chunk in buf.chunks_mut(DMA_MAX_TRANSFER_SIZE) {
+            total += self.read_dma_inner(chunk).await?;
+        }
+
+        Ok(total)
+    }
+
+    /// Internal helper to read a single chunk (max 0x7FFF bytes) using DMA.
+    async fn read_dma_inner(&mut self, buf: &mut [u8]) -> Result<usize> {
+        let len = buf.len();
+        let peri_addr = self.info.regs.data().as_ptr() as *const u8;
+
+        unsafe {
+            // Clean up channel state
+            self.rx_dma.disable_request();
+            self.rx_dma.clear_done();
+            self.rx_dma.clear_interrupt();
+
+            // Set DMA request source from instance type (type-safe)
+            self.rx_dma.set_request_source::<T::RxDmaRequest>();
+
+            // Configure TCD for peripheral-to-memory transfer
+            self.rx_dma
+                .setup_read_from_peripheral(peri_addr, buf, EnableInterrupt::Yes);
+
+            // Enable UART RX DMA request
+            self.info.regs.baud().modify(|_, w| w.rdmae().enabled());
+
+            // Enable DMA channel request
+            self.rx_dma.enable_request();
+        }
+
+        // Create guard that will abort DMA if this future is dropped
+        let guard = RxDmaGuard::new(&self.rx_dma, self.info.regs);
+
+        // Wait for completion asynchronously
+        core::future::poll_fn(|cx| {
+            self.rx_dma.waker().register(cx.waker());
+            if self.rx_dma.is_done() {
+                core::task::Poll::Ready(())
+            } else {
+                core::task::Poll::Pending
+            }
+        })
+        .await;
+
+        // Transfer completed successfully - clean up without aborting
+        guard.complete();
+
+        Ok(len)
+    }
+
+    /// Blocking read (fallback when DMA is not needed)
+    pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> {
+        for byte in buf.iter_mut() {
+            loop {
+                if has_data(self.info.regs) {
+                    *byte = (self.info.regs.data().read().bits() & 0xFF) as u8;
+                    break;
+                }
+                check_and_clear_rx_errors(self.info.regs)?;
+            }
+        }
+        Ok(())
+    }
+
+    pub fn into_ring_dma_rx<'buf>(self, buf: &'buf mut [u8]) -> LpuartRxRingDma<'a, 'buf, T, C> {
+        unsafe {
+            let ring = self.setup_ring_buffer(buf);
+            self.enable_dma_request();
+            LpuartRxRingDma { _inner: self, ring }
+        }
+    }
+
+    /// Set up a ring buffer for continuous DMA reception.
+    ///
+    /// This configures the DMA channel for circular operation, enabling continuous
+    /// reception of data without gaps. The DMA will continuously write received
+    /// bytes into the buffer, wrapping around when it reaches the end.
+    ///
+    /// This method encapsulates all the low-level setup:
+    /// - Configures the DMA request source for this LPUART instance
+    /// - Enables the RX DMA request in the LPUART peripheral
+    /// - Sets up the circular DMA transfer
+    /// - Enables the NVIC interrupt for async wakeups
+    ///
+    /// # Arguments
+    ///
+    /// * `buf` - Destination buffer for received data (power-of-2 size is ideal for efficiency)
+    ///
+    /// # Returns
+    ///
+    /// A [`RingBuffer`] that can be used to asynchronously read received data.
+    ///
+    /// # Example
+    ///
+    /// ```no_run
+    /// static mut RX_BUF: [u8; 64] = [0; 64];
+    ///
+    /// let rx = LpuartRxDma::new(p.LPUART2, p.P2_3, p.DMA_CH0, config).unwrap();
+    /// let ring_buf = unsafe { rx.setup_ring_buffer(&mut RX_BUF) };
+    ///
+    /// // Read data as it arrives
+    /// let mut buf = [0u8; 16];
+    /// let n = ring_buf.read(&mut buf).await.unwrap();
+    /// ```
+    ///
+    /// # Safety
+    ///
+    /// - The buffer must remain valid for the lifetime of the returned RingBuffer.
+    /// - Only one RingBuffer should exist per LPUART RX channel at a time.
+    /// - The caller must ensure the static buffer is not accessed elsewhere while
+    ///   the ring buffer is active.
+    unsafe fn setup_ring_buffer<'b>(&self, buf: &'b mut [u8]) -> RingBuffer<'b, u8> {
+        // Get the peripheral data register address
+        let peri_addr = self.info.regs.data().as_ptr() as *const u8;
+
+        // Configure DMA request source for this LPUART instance (type-safe)
+        self.rx_dma.set_request_source::<T::RxDmaRequest>();
+
+        // Enable RX DMA request in the LPUART peripheral
+        self.info.regs.baud().modify(|_, w| w.rdmae().enabled());
+
+        // Set up circular DMA transfer (this also enables NVIC interrupt)
+        self.rx_dma.setup_circular_read(peri_addr, buf)
+    }
+
+    /// Enable the DMA channel request.
+    ///
+    /// Call this after `setup_ring_buffer()` to start continuous reception.
+    /// This is separated from setup to allow for any additional configuration
+    /// before starting the transfer.
+    unsafe fn enable_dma_request(&self) {
+        self.rx_dma.enable_request();
+    }
+}
+
+impl<'peri, 'buf, T: Instance, C: DmaChannelTrait> LpuartRxRingDma<'peri, 'buf, T, C> {
+    /// Read from the ring buffer
+    pub fn read<'d>(
+        &mut self,
+        dst: &'d mut [u8],
+    ) -> impl Future<Output = core::result::Result<usize, crate::dma::Error>> + use<'_, 'buf, 'd, T, C> {
+        self.ring.read(dst)
+    }
+
+    /// Clear the current contents of the ring buffer
+    pub fn clear(&mut self) {
+        self.ring.clear();
+    }
+}
+
+impl<'a, T: Instance, TxC: DmaChannelTrait, RxC: DmaChannelTrait> LpuartDma<'a, T, TxC, RxC> {
+    /// Create a new LPUART driver with DMA support for both TX and RX.
+    pub fn new(
+        _inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        tx_dma_ch: Peri<'a, TxC>,
+        rx_dma_ch: Peri<'a, RxC>,
+        config: Config,
+    ) -> Result<Self> {
+        tx_pin.as_tx();
+        rx_pin.as_rx();
+
+        let tx_pin: Peri<'a, AnyPin> = tx_pin.into();
+        let rx_pin: Peri<'a, AnyPin> = rx_pin.into();
+
+        // Initialize LPUART with both TX and RX enabled, no flow control
+        Lpuart::<Async>::init::<T>(true, true, false, false, config)?;
+
+        // Enable DMA interrupts
+        let tx_dma = DmaChannel::new(tx_dma_ch);
+        let rx_dma = DmaChannel::new(rx_dma_ch);
+        tx_dma.enable_interrupt();
+        rx_dma.enable_interrupt();
+
+        Ok(Self {
+            tx: LpuartTxDma {
+                info: T::info(),
+                _tx_pin: tx_pin,
+                tx_dma,
+                _instance: core::marker::PhantomData,
+            },
+            rx: LpuartRxDma {
+                info: T::info(),
+                _rx_pin: rx_pin,
+                rx_dma,
+                _instance: core::marker::PhantomData,
+            },
+        })
+    }
+
+    /// Split into separate TX and RX drivers
+    pub fn split(self) -> (LpuartTxDma<'a, T, TxC>, LpuartRxDma<'a, T, RxC>) {
+        (self.tx, self.rx)
+    }
+
+    /// Write data using DMA
+    pub async fn write_dma(&mut self, buf: &[u8]) -> Result<usize> {
+        self.tx.write_dma(buf).await
+    }
+
+    /// Read data using DMA
+    pub async fn read_dma(&mut self, buf: &mut [u8]) -> Result<usize> {
+        self.rx.read_dma(buf).await
+    }
+}
+
+// ============================================================================
+// EMBEDDED-IO-ASYNC TRAIT IMPLEMENTATIONS
+// ============================================================================
+
+impl<T: Instance, C: DmaChannelTrait> embedded_io::ErrorType for LpuartTxDma<'_, T, C> {
+    type Error = Error;
+}
+
+impl<T: Instance, C: DmaChannelTrait> embedded_io::ErrorType for LpuartRxDma<'_, T, C> {
+    type Error = Error;
+}
+
+impl<T: Instance, TxC: DmaChannelTrait, RxC: DmaChannelTrait> embedded_io::ErrorType for LpuartDma<'_, T, TxC, RxC> {
+    type Error = Error;
+}
+
+// ============================================================================
+// EMBEDDED-HAL 0.2 TRAIT IMPLEMENTATIONS
+// ============================================================================
+
+impl embedded_hal_02::serial::Read<u8> for LpuartRx<'_, Blocking> {
+    type Error = Error;
+
+    fn read(&mut self) -> core::result::Result<u8, nb::Error<Self::Error>> {
+        let mut buf = [0; 1];
+        match self.read(&mut buf) {
+            Ok(_) => Ok(buf[0]),
+            Err(Error::RxFifoEmpty) => Err(nb::Error::WouldBlock),
+            Err(e) => Err(nb::Error::Other(e)),
+        }
+    }
+}
+
+impl embedded_hal_02::serial::Write<u8> for LpuartTx<'_, Blocking> {
+    type Error = Error;
+
+    fn write(&mut self, word: u8) -> core::result::Result<(), nb::Error<Self::Error>> {
+        match self.write(&[word]) {
+            Ok(_) => Ok(()),
+            Err(Error::TxFifoFull) => Err(nb::Error::WouldBlock),
+            Err(e) => Err(nb::Error::Other(e)),
+        }
+    }
+
+    fn flush(&mut self) -> core::result::Result<(), nb::Error<Self::Error>> {
+        match self.flush() {
+            Ok(_) => Ok(()),
+            Err(Error::TxBusy) => Err(nb::Error::WouldBlock),
+            Err(e) => Err(nb::Error::Other(e)),
+        }
+    }
+}
+
+impl embedded_hal_02::blocking::serial::Write<u8> for LpuartTx<'_, Blocking> {
+    type Error = Error;
+
+    fn bwrite_all(&mut self, buffer: &[u8]) -> core::result::Result<(), Self::Error> {
+        self.blocking_write(buffer)
+    }
+
+    fn bflush(&mut self) -> core::result::Result<(), Self::Error> {
+        self.blocking_flush()
+    }
+}
+
+impl embedded_hal_02::serial::Read<u8> for Lpuart<'_, Blocking> {
+    type Error = Error;
+
+    fn read(&mut self) -> core::result::Result<u8, nb::Error<Self::Error>> {
+        embedded_hal_02::serial::Read::read(&mut self.rx)
+    }
+}
+
+impl embedded_hal_02::serial::Write<u8> for Lpuart<'_, Blocking> {
+    type Error = Error;
+
+    fn write(&mut self, word: u8) -> core::result::Result<(), nb::Error<Self::Error>> {
+        embedded_hal_02::serial::Write::write(&mut self.tx, word)
+    }
+
+    fn flush(&mut self) -> core::result::Result<(), nb::Error<Self::Error>> {
+        embedded_hal_02::serial::Write::flush(&mut self.tx)
+    }
+}
+
+impl embedded_hal_02::blocking::serial::Write<u8> for Lpuart<'_, Blocking> {
+    type Error = Error;
+
+    fn bwrite_all(&mut self, buffer: &[u8]) -> core::result::Result<(), Self::Error> {
+        self.blocking_write(buffer)
+    }
+
+    fn bflush(&mut self) -> core::result::Result<(), Self::Error> {
+        self.blocking_flush()
+    }
+}
+
+// ============================================================================
+// EMBEDDED-HAL-NB TRAIT IMPLEMENTATIONS
+// ============================================================================
+
+impl embedded_hal_nb::serial::Error for Error {
+    fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
+        match *self {
+            Self::Framing => embedded_hal_nb::serial::ErrorKind::FrameFormat,
+            Self::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun,
+            Self::Parity => embedded_hal_nb::serial::ErrorKind::Parity,
+            Self::Noise => embedded_hal_nb::serial::ErrorKind::Noise,
+            _ => embedded_hal_nb::serial::ErrorKind::Other,
+        }
+    }
+}
+
+impl embedded_hal_nb::serial::ErrorType for LpuartRx<'_, Blocking> {
+    type Error = Error;
+}
+
+impl embedded_hal_nb::serial::ErrorType for LpuartTx<'_, Blocking> {
+    type Error = Error;
+}
+
+impl embedded_hal_nb::serial::ErrorType for Lpuart<'_, Blocking> {
+    type Error = Error;
+}
+
+impl embedded_hal_nb::serial::Read for LpuartRx<'_, Blocking> {
+    fn read(&mut self) -> nb::Result<u8, Self::Error> {
+        let mut buf = [0; 1];
+        match self.read(&mut buf) {
+            Ok(_) => Ok(buf[0]),
+            Err(Error::RxFifoEmpty) => Err(nb::Error::WouldBlock),
+            Err(e) => Err(nb::Error::Other(e)),
+        }
+    }
+}
+
+impl embedded_hal_nb::serial::Write for LpuartTx<'_, Blocking> {
+    fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
+        match self.write(&[word]) {
+            Ok(_) => Ok(()),
+            Err(Error::TxFifoFull) => Err(nb::Error::WouldBlock),
+            Err(e) => Err(nb::Error::Other(e)),
+        }
+    }
+
+    fn flush(&mut self) -> nb::Result<(), Self::Error> {
+        match self.flush() {
+            Ok(_) => Ok(()),
+            Err(Error::TxBusy) => Err(nb::Error::WouldBlock),
+            Err(e) => Err(nb::Error::Other(e)),
+        }
+    }
+}
+
+impl core::fmt::Write for LpuartTx<'_, Blocking> {
+    fn write_str(&mut self, s: &str) -> core::fmt::Result {
+        self.blocking_write(s.as_bytes()).map_err(|_| core::fmt::Error)
+    }
+}
+
+impl embedded_hal_nb::serial::Read for Lpuart<'_, Blocking> {
+    fn read(&mut self) -> nb::Result<u8, Self::Error> {
+        embedded_hal_nb::serial::Read::read(&mut self.rx)
+    }
+}
+
+impl embedded_hal_nb::serial::Write for Lpuart<'_, Blocking> {
+    fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
+        embedded_hal_nb::serial::Write::write(&mut self.tx, char)
+    }
+
+    fn flush(&mut self) -> nb::Result<(), Self::Error> {
+        embedded_hal_nb::serial::Write::flush(&mut self.tx)
+    }
+}
+
+// ============================================================================
+// EMBEDDED-IO TRAIT IMPLEMENTATIONS
+// ============================================================================
+
+impl embedded_io::Error for Error {
+    fn kind(&self) -> embedded_io::ErrorKind {
+        embedded_io::ErrorKind::Other
+    }
+}
+
+impl embedded_io::ErrorType for LpuartRx<'_, Blocking> {
+    type Error = Error;
+}
+
+impl embedded_io::ErrorType for LpuartTx<'_, Blocking> {
+    type Error = Error;
+}
+
+impl embedded_io::ErrorType for Lpuart<'_, Blocking> {
+    type Error = Error;
+}
+
+impl embedded_io::Read for LpuartRx<'_, Blocking> {
+    fn read(&mut self, buf: &mut [u8]) -> core::result::Result<usize, Self::Error> {
+        self.blocking_read(buf).map(|_| buf.len())
+    }
+}
+
+impl embedded_io::Write for LpuartTx<'_, Blocking> {
+    fn write(&mut self, buf: &[u8]) -> core::result::Result<usize, Self::Error> {
+        self.blocking_write(buf).map(|_| buf.len())
+    }
+
+    fn flush(&mut self) -> core::result::Result<(), Self::Error> {
+        self.blocking_flush()
+    }
+}
+
+impl embedded_io::Read for Lpuart<'_, Blocking> {
+    fn read(&mut self, buf: &mut [u8]) -> core::result::Result<usize, Self::Error> {
+        embedded_io::Read::read(&mut self.rx, buf)
+    }
+}
+
+impl embedded_io::Write for Lpuart<'_, Blocking> {
+    fn write(&mut self, buf: &[u8]) -> core::result::Result<usize, Self::Error> {
+        embedded_io::Write::write(&mut self.tx, buf)
+    }
+
+    fn flush(&mut self) -> core::result::Result<(), Self::Error> {
+        embedded_io::Write::flush(&mut self.tx)
+    }
+}
diff --git a/embassy-mcxa/src/ostimer.rs b/embassy-mcxa/src/ostimer.rs
new file mode 100644
index 000000000..9e66e82d8
--- /dev/null
+++ b/embassy-mcxa/src/ostimer.rs
@@ -0,0 +1,745 @@
+//! # OSTIMER Driver with Robustness Features
+//!
+//! This module provides an async timer driver for the NXP MCXA276 OSTIMER peripheral
+//! with protection against race conditions and timer rollover issues.
+//!
+//! ## Features
+//!
+//! - Async timing with embassy-time integration
+//! - Gray code counter handling (42-bit counter)
+//! - Interrupt-driven wakeups
+//! - Configurable interrupt priority
+//! - **Race condition protection**: Critical sections and atomic operations
+//! - **Timer rollover handling**: Bounds checking and rollover prevention
+//!
+//! ## Clock Frequency Configuration
+//!
+//! The OSTIMER frequency depends on your system's clock configuration. You must provide
+//! the actual frequency when calling `time_driver::init()`.
+//!
+//! ## Race Condition Protection
+//! - Critical sections in interrupt handlers prevent concurrent access
+//! - Atomic register operations with memory barriers
+//! - Proper interrupt flag clearing and validation
+//!
+//! ## Timer Rollover Handling
+//! - Bounds checking prevents scheduling beyond timer capacity
+//! - Immediate wake for timestamps that would cause rollover issues
+#![allow(dead_code)]
+
+use core::sync::atomic::{AtomicBool, Ordering};
+
+use embassy_hal_internal::{Peri, PeripheralType};
+
+use crate::clocks::periph_helpers::{OsTimerConfig, OstimerClockSel};
+use crate::clocks::{Gate, PoweredClock, assert_reset, enable_and_reset, is_reset_released, release_reset};
+use crate::interrupt::InterruptExt;
+use crate::pac;
+
+// PAC defines the shared RegisterBlock under `ostimer0`.
+type Regs = pac::ostimer0::RegisterBlock;
+
+// OSTIMER EVTIMER register layout constants
+/// Total width of the EVTIMER counter in bits (42 bits total)
+const EVTIMER_TOTAL_BITS: u32 = 42;
+/// Width of the low part of EVTIMER (bits 31:0)
+const EVTIMER_LO_BITS: u32 = 32;
+/// Width of the high part of EVTIMER (bits 41:32)
+const EVTIMER_HI_BITS: u32 = 10;
+/// Bit position where high part starts in the combined 64-bit value
+const EVTIMER_HI_SHIFT: u32 = 32;
+
+/// Bit mask for the high part of EVTIMER
+const EVTIMER_HI_MASK: u16 = (1 << EVTIMER_HI_BITS) - 1;
+
+/// Maximum value for MATCH_L register (32-bit)
+const MATCH_L_MAX: u32 = u32::MAX;
+/// Maximum value for MATCH_H register (10-bit)
+const MATCH_H_MAX: u16 = EVTIMER_HI_MASK;
+
+/// Bit mask for extracting the low 32 bits from a 64-bit value
+const LOW_32_BIT_MASK: u64 = u32::MAX as u64;
+
+/// Gray code conversion bit shifts (most significant to least)
+const GRAY_CONVERSION_SHIFTS: [u32; 6] = [32, 16, 8, 4, 2, 1];
+
+/// Maximum timer value before rollover (2^42 - 1 ticks)
+/// Actual rollover time depends on the configured clock frequency
+const TIMER_MAX_VALUE: u64 = (1u64 << EVTIMER_TOTAL_BITS) - 1;
+
+/// Threshold for detecting timer rollover in comparisons (1 second at 1MHz)
+const TIMER_ROLLOVER_THRESHOLD: u64 = 1_000_000;
+
+/// Common default interrupt priority for OSTIMER
+const DEFAULT_INTERRUPT_PRIORITY: u8 = 3;
+
+// Global alarm state for interrupt handling
+static ALARM_ACTIVE: AtomicBool = AtomicBool::new(false);
+static mut ALARM_CALLBACK: Option<fn()> = None;
+static mut ALARM_FLAG: Option<*const AtomicBool> = None;
+static mut ALARM_TARGET_TIME: u64 = 0;
+
+/// Number of tight spin iterations between elapsed time checks while waiting for MATCH writes to return to the idle (0) state.
+const MATCH_WRITE_READY_SPINS: usize = 512;
+/// Maximum time (in OSTIMER ticks) to wait for MATCH registers to become writable (~5 ms at 1 MHz).
+const MATCH_WRITE_READY_TIMEOUT_TICKS: u64 = 5_000;
+/// Short stabilization delay executed after toggling the MRCC reset line to let the OSTIMER bus interface settle.
+const RESET_STABILIZE_SPINS: usize = 512;
+
+pub(super) fn wait_for_match_write_ready(r: &Regs) -> bool {
+    let start = now_ticks_read();
+    let mut spin_budget = 0usize;
+
+    loop {
+        if r.osevent_ctrl().read().match_wr_rdy().bit_is_clear() {
+            return true;
+        }
+
+        cortex_m::asm::nop();
+        spin_budget += 1;
+
+        if spin_budget >= MATCH_WRITE_READY_SPINS {
+            spin_budget = 0;
+
+            let elapsed = now_ticks_read().wrapping_sub(start);
+            if elapsed >= MATCH_WRITE_READY_TIMEOUT_TICKS {
+                return false;
+            }
+        }
+    }
+}
+
+pub(super) fn wait_for_match_write_complete(r: &Regs) -> bool {
+    let start = now_ticks_read();
+    let mut spin_budget = 0usize;
+
+    loop {
+        if r.osevent_ctrl().read().match_wr_rdy().bit_is_clear() {
+            return true;
+        }
+
+        cortex_m::asm::nop();
+        spin_budget += 1;
+
+        if spin_budget >= MATCH_WRITE_READY_SPINS {
+            spin_budget = 0;
+
+            let elapsed = now_ticks_read().wrapping_sub(start);
+            if elapsed >= MATCH_WRITE_READY_TIMEOUT_TICKS {
+                return false;
+            }
+        }
+    }
+}
+
+fn prime_match_registers(r: &Regs) {
+    // Disable the interrupt, clear any pending flag, then wait until the MATCH registers are writable.
+    r.osevent_ctrl()
+        .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit());
+
+    if wait_for_match_write_ready(r) {
+        r.match_l().write(|w| unsafe { w.match_value().bits(MATCH_L_MAX) });
+        r.match_h().write(|w| unsafe { w.match_value().bits(MATCH_H_MAX) });
+        let _ = wait_for_match_write_complete(r);
+    }
+}
+
+/// Single-shot alarm functionality for OSTIMER
+pub struct Alarm<'d> {
+    /// Whether the alarm is currently active
+    active: AtomicBool,
+    /// Callback to execute when alarm expires (optional)
+    callback: Option<fn()>,
+    /// Flag that gets set when alarm expires (optional)
+    flag: Option<&'d AtomicBool>,
+    _phantom: core::marker::PhantomData<&'d mut ()>,
+}
+
+impl<'d> Default for Alarm<'d> {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl<'d> Alarm<'d> {
+    /// Create a new alarm instance
+    pub fn new() -> Self {
+        Self {
+            active: AtomicBool::new(false),
+            callback: None,
+            flag: None,
+            _phantom: core::marker::PhantomData,
+        }
+    }
+
+    /// Set a callback that will be executed when the alarm expires
+    /// Note: Due to interrupt handler constraints, callbacks must be static function pointers
+    pub fn with_callback(mut self, callback: fn()) -> Self {
+        self.callback = Some(callback);
+        self
+    }
+
+    /// Set a flag that will be set to true when the alarm expires
+    pub fn with_flag(mut self, flag: &'d AtomicBool) -> Self {
+        self.flag = Some(flag);
+        self
+    }
+
+    /// Check if the alarm is currently active
+    pub fn is_active(&self) -> bool {
+        self.active.load(Ordering::Acquire)
+    }
+
+    /// Cancel the alarm if it's active
+    pub fn cancel(&self) {
+        self.active.store(false, Ordering::Release);
+    }
+}
+
+/// Configuration for Ostimer::new()
+#[derive(Copy, Clone)]
+pub struct Config {
+    /// Initialize MATCH registers to their max values and mask/clear the interrupt flag.
+    pub init_match_max: bool,
+    pub power: PoweredClock,
+    pub source: OstimerClockSel,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            init_match_max: true,
+            power: PoweredClock::NormalEnabledDeepSleepDisabled,
+            source: OstimerClockSel::Clk1M,
+        }
+    }
+}
+
+/// OSTIMER peripheral instance
+pub struct Ostimer<'d, I: Instance> {
+    _inst: core::marker::PhantomData<I>,
+    clock_frequency_hz: u64,
+    _phantom: core::marker::PhantomData<&'d mut ()>,
+}
+
+impl<'d, I: Instance> Ostimer<'d, I> {
+    /// Construct OSTIMER handle.
+    /// Requires clocks for the instance to be enabled by the board before calling.
+    /// Does not enable NVIC or INTENA; use time_driver::init() for async operation.
+    pub fn new(_inst: Peri<'d, I>, cfg: Config) -> Self {
+        let clock_freq = unsafe {
+            enable_and_reset::<I>(&OsTimerConfig {
+                power: cfg.power,
+                source: cfg.source,
+            })
+            .expect("Enabling OsTimer clock should not fail")
+        };
+
+        assert!(clock_freq > 0, "OSTIMER frequency must be greater than 0");
+
+        if cfg.init_match_max {
+            let r: &Regs = unsafe { &*I::ptr() };
+            // Mask INTENA, clear pending flag, and set MATCH to max so no spurious IRQ fires.
+            prime_match_registers(r);
+        }
+
+        Self {
+            _inst: core::marker::PhantomData,
+            clock_frequency_hz: clock_freq as u64,
+            _phantom: core::marker::PhantomData,
+        }
+    }
+
+    /// Get the configured clock frequency in Hz
+    pub fn clock_frequency_hz(&self) -> u64 {
+        self.clock_frequency_hz
+    }
+
+    /// Read the current timer counter value in timer ticks
+    ///
+    /// # Returns
+    /// Current timer counter value as a 64-bit unsigned integer
+    pub fn now(&self) -> u64 {
+        now_ticks_read()
+    }
+
+    /// Reset the timer counter to zero
+    ///
+    /// This performs a hardware reset of the OSTIMER peripheral, which will reset
+    /// the counter to zero and clear any pending interrupts. Note that this will
+    /// affect all timer operations including embassy-time.
+    ///
+    /// # Safety
+    /// This operation will reset the entire OSTIMER peripheral. Any active alarms
+    /// or time_driver operations will be disrupted. Use with caution.
+    pub fn reset(&self, _peripherals: &crate::pac::Peripherals) {
+        critical_section::with(|_| {
+            let r: &Regs = unsafe { &*I::ptr() };
+
+            // Mask the peripheral interrupt flag before we toggle the reset line so that
+            // no new NVIC activity races with the reset sequence.
+            r.osevent_ctrl()
+                .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit());
+
+            unsafe {
+                assert_reset::<I>();
+
+                for _ in 0..RESET_STABILIZE_SPINS {
+                    cortex_m::asm::nop();
+                }
+
+                release_reset::<I>();
+
+                while !is_reset_released::<I>() {
+                    cortex_m::asm::nop();
+                }
+            }
+
+            for _ in 0..RESET_STABILIZE_SPINS {
+                cortex_m::asm::nop();
+            }
+
+            // Clear alarm bookkeeping before re-arming MATCH registers.
+            ALARM_ACTIVE.store(false, Ordering::Release);
+            unsafe {
+                ALARM_TARGET_TIME = 0;
+                ALARM_CALLBACK = None;
+                ALARM_FLAG = None;
+            }
+
+            prime_match_registers(r);
+        });
+
+        // Ensure no stale OS_EVENT request remains pending after the reset sequence.
+        crate::interrupt::OS_EVENT.unpend();
+    }
+
+    /// Schedule a single-shot alarm to expire after the specified delay in microseconds
+    ///
+    /// # Parameters
+    /// * `alarm` - The alarm instance to schedule
+    /// * `delay_us` - Delay in microseconds from now
+    ///
+    /// # Returns
+    /// `true` if the alarm was scheduled successfully, `false` if it would exceed timer capacity
+    pub fn schedule_alarm_delay(&self, alarm: &Alarm, delay_us: u64) -> bool {
+        let delay_ticks = (delay_us * self.clock_frequency_hz) / 1_000_000;
+        let target_time = now_ticks_read() + delay_ticks;
+        self.schedule_alarm_at(alarm, target_time)
+    }
+
+    /// Schedule a single-shot alarm to expire at the specified absolute time in timer ticks
+    ///
+    /// # Parameters
+    /// * `alarm` - The alarm instance to schedule
+    /// * `target_ticks` - Absolute time in timer ticks when the alarm should expire
+    ///
+    /// # Returns
+    /// `true` if the alarm was scheduled successfully, `false` if it would exceed timer capacity
+    pub fn schedule_alarm_at(&self, alarm: &Alarm, target_ticks: u64) -> bool {
+        let now = now_ticks_read();
+
+        // Check if target time is in the past
+        if target_ticks <= now {
+            // Execute callback immediately if alarm was supposed to be active
+            if alarm.active.load(Ordering::Acquire) {
+                alarm.active.store(false, Ordering::Release);
+                if let Some(callback) = alarm.callback {
+                    callback();
+                }
+                if let Some(flag) = &alarm.flag {
+                    flag.store(true, Ordering::Release);
+                }
+            }
+            return true;
+        }
+
+        // Check for timer rollover
+        let max_future = now + TIMER_MAX_VALUE;
+        if target_ticks > max_future {
+            return false; // Would exceed timer capacity
+        }
+
+        // Program the timer
+        let r: &Regs = unsafe { &*I::ptr() };
+
+        critical_section::with(|_| {
+            // Disable interrupt and clear flag
+            r.osevent_ctrl()
+                .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit());
+
+            if !wait_for_match_write_ready(r) {
+                prime_match_registers(r);
+
+                if !wait_for_match_write_ready(r) {
+                    alarm.active.store(false, Ordering::Release);
+                    ALARM_ACTIVE.store(false, Ordering::Release);
+                    unsafe {
+                        ALARM_TARGET_TIME = 0;
+                        ALARM_CALLBACK = None;
+                        ALARM_FLAG = None;
+                    }
+                    return false;
+                }
+            }
+
+            // Mark alarm as active now that we know the MATCH registers are writable
+            alarm.active.store(true, Ordering::Release);
+
+            // Set global alarm state for interrupt handler
+            ALARM_ACTIVE.store(true, Ordering::Release);
+            unsafe {
+                ALARM_TARGET_TIME = target_ticks;
+                ALARM_CALLBACK = alarm.callback;
+                ALARM_FLAG = alarm.flag.map(|f| f as *const AtomicBool);
+            }
+
+            // Program MATCH registers (Gray-coded)
+            let gray = bin_to_gray(target_ticks);
+            let l = (gray & LOW_32_BIT_MASK) as u32;
+            let h = (((gray >> EVTIMER_HI_SHIFT) as u16) & EVTIMER_HI_MASK) as u16;
+
+            r.match_l().write(|w| unsafe { w.match_value().bits(l) });
+            r.match_h().write(|w| unsafe { w.match_value().bits(h) });
+
+            if !wait_for_match_write_complete(r) {
+                alarm.active.store(false, Ordering::Release);
+                ALARM_ACTIVE.store(false, Ordering::Release);
+                unsafe {
+                    ALARM_TARGET_TIME = 0;
+                    ALARM_CALLBACK = None;
+                    ALARM_FLAG = None;
+                }
+                return false;
+            }
+
+            let now_after_program = now_ticks_read();
+            let intrflag_set = r.osevent_ctrl().read().ostimer_intrflag().bit_is_set();
+            if now_after_program >= target_ticks && !intrflag_set {
+                alarm.active.store(false, Ordering::Release);
+                ALARM_ACTIVE.store(false, Ordering::Release);
+                unsafe {
+                    ALARM_TARGET_TIME = 0;
+                    ALARM_CALLBACK = None;
+                    ALARM_FLAG = None;
+                }
+                return false;
+            }
+
+            // Enable interrupt
+            r.osevent_ctrl().write(|w| w.ostimer_intena().set_bit());
+
+            true
+        })
+    }
+
+    /// Cancel any active alarm
+    pub fn cancel_alarm(&self, alarm: &Alarm) {
+        critical_section::with(|_| {
+            alarm.cancel();
+
+            // Clear global alarm state
+            ALARM_ACTIVE.store(false, Ordering::Release);
+            unsafe { ALARM_TARGET_TIME = 0 };
+
+            // Reset MATCH registers to maximum values to prevent spurious interrupts
+            let r: &Regs = unsafe { &*I::ptr() };
+            prime_match_registers(r);
+        });
+    }
+
+    /// Check if an alarm has expired (call this from your interrupt handler)
+    /// Returns true if the alarm was active and has now expired
+    pub fn check_alarm_expired(&self, alarm: &Alarm) -> bool {
+        if alarm.active.load(Ordering::Acquire) {
+            alarm.active.store(false, Ordering::Release);
+
+            // Execute callback
+            if let Some(callback) = alarm.callback {
+                callback();
+            }
+
+            // Set flag
+            if let Some(flag) = &alarm.flag {
+                flag.store(true, Ordering::Release);
+            }
+
+            true
+        } else {
+            false
+        }
+    }
+}
+
+/// Read current EVTIMER (Gray-coded) and convert to binary ticks.
+#[inline(always)]
+fn now_ticks_read() -> u64 {
+    let r: &Regs = unsafe { &*pac::Ostimer0::ptr() };
+
+    // Read high then low to minimize incoherent snapshots
+    let hi = (r.evtimerh().read().evtimer_count_value().bits() as u64) & (EVTIMER_HI_MASK as u64);
+    let lo = r.evtimerl().read().evtimer_count_value().bits() as u64;
+    // Combine and convert from Gray code to binary
+    let gray = lo | (hi << EVTIMER_HI_SHIFT);
+    gray_to_bin(gray)
+}
+
+// Instance trait like other drivers, providing a PAC pointer for this OSTIMER instance
+pub trait Instance: Gate<MrccPeriphConfig = OsTimerConfig> + PeripheralType {
+    fn ptr() -> *const Regs;
+}
+
+#[cfg(not(feature = "time"))]
+impl Instance for crate::peripherals::OSTIMER0 {
+    #[inline(always)]
+    fn ptr() -> *const Regs {
+        pac::Ostimer0::ptr()
+    }
+}
+
+#[inline(always)]
+fn bin_to_gray(x: u64) -> u64 {
+    x ^ (x >> 1)
+}
+
+#[inline(always)]
+fn gray_to_bin(gray: u64) -> u64 {
+    // More efficient iterative conversion using predefined shifts
+    let mut bin = gray;
+    for &shift in &GRAY_CONVERSION_SHIFTS {
+        bin ^= bin >> shift;
+    }
+    bin
+}
+
+#[cfg(feature = "time")]
+pub mod time_driver {
+    use core::sync::atomic::Ordering;
+    use core::task::Waker;
+
+    use embassy_sync::waitqueue::AtomicWaker;
+    use embassy_time_driver as etd;
+
+    use super::{
+        ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME, EVTIMER_HI_MASK, EVTIMER_HI_SHIFT,
+        LOW_32_BIT_MASK, Regs, bin_to_gray, now_ticks_read,
+    };
+    use crate::clocks::periph_helpers::{OsTimerConfig, OstimerClockSel};
+    use crate::clocks::{PoweredClock, enable_and_reset};
+    use crate::pac;
+
+    #[allow(non_camel_case_types)]
+    pub(crate) struct _OSTIMER0_TIME_DRIVER {
+        _x: (),
+    }
+
+    // #[cfg(feature = "time")]
+    // impl_cc_gate!(_OSTIMER0_TIME_DRIVER, mrcc_glb_cc1, mrcc_glb_rst1, ostimer0, OsTimerConfig);
+
+    impl crate::clocks::Gate for _OSTIMER0_TIME_DRIVER {
+        type MrccPeriphConfig = crate::clocks::periph_helpers::OsTimerConfig;
+
+        #[inline]
+        unsafe fn enable_clock() {
+            let mrcc = unsafe { pac::Mrcc0::steal() };
+            mrcc.mrcc_glb_cc1().modify(|_, w| w.ostimer0().enabled());
+        }
+
+        #[inline]
+        unsafe fn disable_clock() {
+            let mrcc = unsafe { pac::Mrcc0::steal() };
+            mrcc.mrcc_glb_cc1().modify(|_r, w| w.ostimer0().disabled());
+        }
+
+        #[inline]
+        fn is_clock_enabled() -> bool {
+            let mrcc = unsafe { pac::Mrcc0::steal() };
+            mrcc.mrcc_glb_cc1().read().ostimer0().is_enabled()
+        }
+
+        #[inline]
+        unsafe fn release_reset() {
+            let mrcc = unsafe { pac::Mrcc0::steal() };
+            mrcc.mrcc_glb_rst1().modify(|_, w| w.ostimer0().enabled());
+        }
+
+        #[inline]
+        unsafe fn assert_reset() {
+            let mrcc = unsafe { pac::Mrcc0::steal() };
+            mrcc.mrcc_glb_rst1().modify(|_, w| w.ostimer0().disabled());
+        }
+
+        #[inline]
+        fn is_reset_released() -> bool {
+            let mrcc = unsafe { pac::Mrcc0::steal() };
+            mrcc.mrcc_glb_rst1().read().ostimer0().is_enabled()
+        }
+    }
+
+    pub struct Driver;
+    static TIMER_WAKER: AtomicWaker = AtomicWaker::new();
+
+    impl etd::Driver for Driver {
+        fn now(&self) -> u64 {
+            // Use the hardware counter (frequency configured in init)
+            super::now_ticks_read()
+        }
+
+        fn schedule_wake(&self, timestamp: u64, waker: &Waker) {
+            let now = self.now();
+
+            // If timestamp is in the past or very close to now, wake immediately
+            if timestamp <= now {
+                waker.wake_by_ref();
+                return;
+            }
+
+            // Prevent scheduling too far in the future (beyond timer rollover)
+            // This prevents wraparound issues
+            let max_future = now + super::TIMER_MAX_VALUE;
+            if timestamp > max_future {
+                // For very long timeouts, wake immediately to avoid rollover issues
+                waker.wake_by_ref();
+                return;
+            }
+
+            // Register the waker first so any immediate wake below is observed by the executor.
+            TIMER_WAKER.register(waker);
+
+            let r: &Regs = unsafe { &*pac::Ostimer0::ptr() };
+
+            critical_section::with(|_| {
+                // Mask INTENA and clear flag
+                r.osevent_ctrl()
+                    .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit());
+
+                // Read back to ensure W1C took effect on hardware
+                let _ = r.osevent_ctrl().read().ostimer_intrflag().bit();
+
+                if !super::wait_for_match_write_ready(r) {
+                    super::prime_match_registers(r);
+
+                    if !super::wait_for_match_write_ready(r) {
+                        // If we can't safely program MATCH, wake immediately and leave INTENA masked.
+                        waker.wake_by_ref();
+                        return;
+                    }
+                }
+
+                // Program MATCH (Gray-coded). Write low then high, then fence.
+                let gray = bin_to_gray(timestamp);
+                let l = (gray & LOW_32_BIT_MASK) as u32;
+
+                let h = (((gray >> EVTIMER_HI_SHIFT) as u16) & EVTIMER_HI_MASK) as u16;
+
+                r.match_l().write(|w| unsafe { w.match_value().bits(l) });
+                r.match_h().write(|w| unsafe { w.match_value().bits(h) });
+
+                if !super::wait_for_match_write_complete(r) {
+                    waker.wake_by_ref();
+                    return;
+                }
+
+                let now_after_program = super::now_ticks_read();
+                let intrflag_set = r.osevent_ctrl().read().ostimer_intrflag().bit_is_set();
+                if now_after_program >= timestamp && !intrflag_set {
+                    waker.wake_by_ref();
+                    return;
+                }
+
+                // Enable peripheral interrupt
+                r.osevent_ctrl().write(|w| w.ostimer_intena().set_bit());
+            });
+        }
+    }
+
+    /// Install the global embassy-time driver and configure NVIC priority for OS_EVENT.
+    ///
+    /// # Parameters
+    /// * `priority` - Interrupt priority for the OSTIMER interrupt
+    /// * `frequency_hz` - Actual OSTIMER clock frequency in Hz (stored for future use)
+    ///
+    /// Note: The frequency parameter is currently accepted for API compatibility.
+    /// The embassy_time_driver macro handles driver registration automatically.
+    pub fn init(priority: crate::interrupt::Priority, frequency_hz: u64) {
+        let _clock_freq = unsafe {
+            enable_and_reset::<_OSTIMER0_TIME_DRIVER>(&OsTimerConfig {
+                power: PoweredClock::AlwaysEnabled,
+                source: OstimerClockSel::Clk1M,
+            })
+            .expect("Enabling OsTimer clock should not fail")
+        };
+
+        // Mask/clear at peripheral and set default MATCH
+        let r: &Regs = unsafe { &*pac::Ostimer0::ptr() };
+        super::prime_match_registers(r);
+
+        // Configure NVIC for timer operation
+        crate::interrupt::OS_EVENT.configure_for_timer(priority);
+
+        // Note: The embassy_time_driver macro automatically registers the driver
+        // The frequency parameter is accepted for future compatibility
+        let _ = frequency_hz; // Suppress unused parameter warning
+    }
+
+    // Export the global time driver expected by embassy-time
+    embassy_time_driver::time_driver_impl!(static DRIVER: Driver = Driver);
+
+    /// To be called from the OS_EVENT IRQ.
+    pub fn on_interrupt() {
+        let r: &Regs = unsafe { &*pac::Ostimer0::ptr() };
+
+        // Critical section to prevent races with schedule_wake
+        critical_section::with(|_| {
+            // Check if interrupt is actually pending and handle it atomically
+            if r.osevent_ctrl().read().ostimer_intrflag().bit_is_set() {
+                // Clear flag and disable interrupt atomically
+                r.osevent_ctrl().write(|w| {
+                    w.ostimer_intrflag()
+                        .clear_bit_by_one() // Write-1-to-clear using safe helper
+                        .ostimer_intena()
+                        .clear_bit()
+                });
+
+                // Wake the waiting task
+                TIMER_WAKER.wake();
+
+                // Handle alarm callback if active and this interrupt is for the alarm
+                if ALARM_ACTIVE.load(Ordering::SeqCst) {
+                    let current_time = now_ticks_read();
+                    let target_time = unsafe { ALARM_TARGET_TIME };
+
+                    // Check if current time is close to alarm target time (within 1000 ticks for timing variations)
+                    if current_time >= target_time && current_time <= target_time + 1000 {
+                        ALARM_ACTIVE.store(false, Ordering::SeqCst);
+                        unsafe { ALARM_TARGET_TIME = 0 };
+
+                        // Execute callback if set
+                        unsafe {
+                            if let Some(callback) = ALARM_CALLBACK {
+                                callback();
+                            }
+                        }
+
+                        // Set flag if provided
+                        unsafe {
+                            if let Some(flag) = ALARM_FLAG {
+                                (*flag).store(true, Ordering::SeqCst);
+                            }
+                        }
+                    }
+                }
+            }
+        });
+    }
+}
+
+#[cfg(feature = "time")]
+use crate::pac::interrupt;
+
+#[cfg(feature = "time")]
+#[allow(non_snake_case)]
+#[interrupt]
+fn OS_EVENT() {
+    time_driver::on_interrupt()
+}
diff --git a/embassy-mcxa/src/rtc.rs b/embassy-mcxa/src/rtc.rs
new file mode 100644
index 000000000..f975d9c9f
--- /dev/null
+++ b/embassy-mcxa/src/rtc.rs
@@ -0,0 +1,453 @@
+//! RTC DateTime driver.
+use core::marker::PhantomData;
+
+use embassy_hal_internal::{Peri, PeripheralType};
+use maitake_sync::WaitCell;
+
+use crate::clocks::with_clocks;
+use crate::interrupt::typelevel::{Handler, Interrupt};
+use crate::pac;
+use crate::pac::rtc0::cr::Um;
+
+type Regs = pac::rtc0::RegisterBlock;
+
+/// Global wait cell for alarm notifications
+static WAKER: WaitCell = WaitCell::new();
+
+/// RTC interrupt handler.
+pub struct InterruptHandler<I: Instance> {
+    _phantom: PhantomData<I>,
+}
+
+/// Trait for RTC peripheral instances
+pub trait Instance: PeripheralType {
+    type Interrupt: Interrupt;
+    fn ptr() -> *const Regs;
+}
+
+/// Token for RTC0
+pub type Rtc0 = crate::peripherals::RTC0;
+impl Instance for crate::peripherals::RTC0 {
+    type Interrupt = crate::interrupt::typelevel::RTC;
+    #[inline(always)]
+    fn ptr() -> *const Regs {
+        pac::Rtc0::ptr()
+    }
+}
+
+/// Number of days in a standard year
+const DAYS_IN_A_YEAR: u32 = 365;
+/// Number of seconds in a day
+const SECONDS_IN_A_DAY: u32 = 86400;
+/// Number of seconds in an hour
+const SECONDS_IN_A_HOUR: u32 = 3600;
+/// Number of seconds in a minute
+const SECONDS_IN_A_MINUTE: u32 = 60;
+/// Unix epoch start year
+const YEAR_RANGE_START: u16 = 1970;
+
+/// Date and time structure for RTC operations
+#[derive(Debug, Clone, Copy)]
+pub struct RtcDateTime {
+    pub year: u16,
+    pub month: u8,
+    pub day: u8,
+    pub hour: u8,
+    pub minute: u8,
+    pub second: u8,
+}
+#[derive(Copy, Clone)]
+pub struct RtcConfig {
+    #[allow(dead_code)]
+    wakeup_select: bool,
+    update_mode: Um,
+    #[allow(dead_code)]
+    supervisor_access: bool,
+    compensation_interval: u8,
+    compensation_time: u8,
+}
+
+/// RTC interrupt enable flags
+#[derive(Copy, Clone)]
+pub struct RtcInterruptEnable;
+impl RtcInterruptEnable {
+    pub const RTC_TIME_INVALID_INTERRUPT_ENABLE: u32 = 1 << 0;
+    pub const RTC_TIME_OVERFLOW_INTERRUPT_ENABLE: u32 = 1 << 1;
+    pub const RTC_ALARM_INTERRUPT_ENABLE: u32 = 1 << 2;
+    pub const RTC_SECONDS_INTERRUPT_ENABLE: u32 = 1 << 4;
+}
+
+/// Converts a DateTime structure to Unix timestamp (seconds since 1970-01-01)
+///
+/// # Arguments
+///
+/// * `datetime` - The date and time to convert
+///
+/// # Returns
+///
+/// Unix timestamp as u32
+///
+/// # Note
+///
+/// This function handles leap years correctly.
+pub fn convert_datetime_to_seconds(datetime: &RtcDateTime) -> u32 {
+    let month_days: [u16; 13] = [0, 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334];
+
+    let mut seconds = (datetime.year as u32 - 1970) * DAYS_IN_A_YEAR;
+    seconds += (datetime.year as u32 / 4) - (1970 / 4);
+    seconds += month_days[datetime.month as usize] as u32;
+    seconds += datetime.day as u32 - 1;
+
+    if (datetime.year & 3 == 0) && (datetime.month <= 2) {
+        seconds -= 1;
+    }
+
+    seconds = seconds * SECONDS_IN_A_DAY
+        + (datetime.hour as u32 * SECONDS_IN_A_HOUR)
+        + (datetime.minute as u32 * SECONDS_IN_A_MINUTE)
+        + datetime.second as u32;
+
+    seconds
+}
+
+/// Converts Unix timestamp to DateTime structure
+///
+/// # Arguments
+///
+/// * `seconds` - Unix timestamp (seconds since 1970-01-01)
+///
+/// # Returns
+///
+/// RtcDateTime structure with the converted date and time
+///
+/// # Note
+///
+/// This function handles leap years correctly.
+pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime {
+    let mut seconds_remaining = seconds;
+    let mut days = seconds_remaining / SECONDS_IN_A_DAY + 1;
+    seconds_remaining %= SECONDS_IN_A_DAY;
+
+    let hour = (seconds_remaining / SECONDS_IN_A_HOUR) as u8;
+    seconds_remaining %= SECONDS_IN_A_HOUR;
+    let minute = (seconds_remaining / SECONDS_IN_A_MINUTE) as u8;
+    let second = (seconds_remaining % SECONDS_IN_A_MINUTE) as u8;
+
+    let mut year = YEAR_RANGE_START;
+    let mut days_in_year = DAYS_IN_A_YEAR;
+
+    while days > days_in_year {
+        days -= days_in_year;
+        year += 1;
+
+        days_in_year = if year.is_multiple_of(4) {
+            DAYS_IN_A_YEAR + 1
+        } else {
+            DAYS_IN_A_YEAR
+        };
+    }
+
+    let days_per_month = [
+        31,
+        if year.is_multiple_of(4) { 29 } else { 28 },
+        31,
+        30,
+        31,
+        30,
+        31,
+        31,
+        30,
+        31,
+        30,
+        31,
+    ];
+
+    let mut month = 1;
+    for (m, month_days) in days_per_month.iter().enumerate() {
+        let m = m + 1;
+        if days <= *month_days as u32 {
+            month = m;
+            break;
+        } else {
+            days -= *month_days as u32;
+        }
+    }
+
+    let day = days as u8;
+
+    RtcDateTime {
+        year,
+        month: month as u8,
+        day,
+        hour,
+        minute,
+        second,
+    }
+}
+
+/// Returns default RTC configuration
+///
+/// # Returns
+///
+/// RtcConfig with sensible default values:
+/// - No wakeup selection
+/// - Update mode 0 (immediate updates)
+/// - No supervisor access restriction
+/// - No compensation
+pub fn get_default_config() -> RtcConfig {
+    RtcConfig {
+        wakeup_select: false,
+        update_mode: Um::Um0,
+        supervisor_access: false,
+        compensation_interval: 0,
+        compensation_time: 0,
+    }
+}
+/// Minimal RTC handle for a specific instance I (store the zero-sized token like embassy)
+pub struct Rtc<'a, I: Instance> {
+    _inst: core::marker::PhantomData<&'a mut I>,
+}
+
+impl<'a, I: Instance> Rtc<'a, I> {
+    /// Create a new instance of the real time clock.
+    pub fn new(
+        _inst: Peri<'a, I>,
+        _irq: impl crate::interrupt::typelevel::Binding<I::Interrupt, InterruptHandler<I>> + 'a,
+        config: RtcConfig,
+    ) -> Self {
+        let rtc = unsafe { &*I::ptr() };
+
+        // The RTC is NOT gated by the MRCC, but we DO need to make sure the 16k clock
+        // on the vsys domain is active
+        let clocks = with_clocks(|c| c.clk_16k_vsys.clone());
+        match clocks {
+            None => panic!("Clocks have not been initialized"),
+            Some(None) => panic!("Clocks initialized, but clk_16k_vsys not active"),
+            Some(Some(_)) => {}
+        }
+
+        // RTC reset
+        rtc.cr().modify(|_, w| w.swr().set_bit());
+        rtc.cr().modify(|_, w| w.swr().clear_bit());
+        rtc.tsr().write(|w| unsafe { w.bits(1) });
+
+        rtc.cr().modify(|_, w| w.um().variant(config.update_mode));
+
+        rtc.tcr().modify(|_, w| unsafe {
+            w.cir()
+                .bits(config.compensation_interval)
+                .tcr()
+                .bits(config.compensation_time)
+        });
+
+        // Enable RTC interrupt
+        I::Interrupt::unpend();
+        unsafe { I::Interrupt::enable() };
+
+        Self {
+            _inst: core::marker::PhantomData,
+        }
+    }
+
+    /// Set the current date and time
+    ///
+    /// # Arguments
+    ///
+    /// * `datetime` - The date and time to set
+    ///
+    /// # Note
+    ///
+    /// The datetime is converted to Unix timestamp and written to the time seconds register.
+    pub fn set_datetime(&self, datetime: RtcDateTime) {
+        let rtc = unsafe { &*I::ptr() };
+        let seconds = convert_datetime_to_seconds(&datetime);
+        rtc.tsr().write(|w| unsafe { w.bits(seconds) });
+    }
+
+    /// Get the current date and time
+    ///
+    /// # Returns
+    ///
+    /// Current date and time as RtcDateTime
+    ///
+    /// # Note
+    ///
+    /// Reads the current Unix timestamp from the time seconds register and converts it.
+    pub fn get_datetime(&self) -> RtcDateTime {
+        let rtc = unsafe { &*I::ptr() };
+        let seconds = rtc.tsr().read().bits();
+        convert_seconds_to_datetime(seconds)
+    }
+
+    /// Set the alarm date and time
+    ///
+    /// # Arguments
+    ///
+    /// * `alarm` - The date and time when the alarm should trigger
+    ///
+    /// # Note
+    ///
+    /// This function:
+    /// - Clears any existing alarm by writing 0 to the alarm register
+    /// - Waits for the clear operation to complete
+    /// - Sets the new alarm time
+    /// - Waits for the write operation to complete
+    /// - Uses timeouts to prevent infinite loops
+    /// - Enables the alarm interrupt after setting
+    pub fn set_alarm(&self, alarm: RtcDateTime) {
+        let rtc = unsafe { &*I::ptr() };
+        let seconds = convert_datetime_to_seconds(&alarm);
+
+        rtc.tar().write(|w| unsafe { w.bits(0) });
+        let mut timeout = 10000;
+        while rtc.tar().read().bits() != 0 && timeout > 0 {
+            timeout -= 1;
+        }
+
+        rtc.tar().write(|w| unsafe { w.bits(seconds) });
+
+        let mut timeout = 10000;
+        while rtc.tar().read().bits() != seconds && timeout > 0 {
+            timeout -= 1;
+        }
+
+        self.set_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE);
+    }
+
+    /// Get the current alarm date and time
+    ///
+    /// # Returns
+    ///
+    /// Alarm date and time as RtcDateTime
+    ///
+    /// # Note
+    ///
+    /// Reads the alarm timestamp from the time alarm register and converts it.
+    pub fn get_alarm(&self) -> RtcDateTime {
+        let rtc = unsafe { &*I::ptr() };
+        let alarm_seconds = rtc.tar().read().bits();
+        convert_seconds_to_datetime(alarm_seconds)
+    }
+
+    /// Start the RTC time counter
+    ///
+    /// # Note
+    ///
+    /// Sets the Time Counter Enable (TCE) bit in the status register.
+    pub fn start(&self) {
+        let rtc = unsafe { &*I::ptr() };
+        rtc.sr().modify(|_, w| w.tce().set_bit());
+    }
+
+    /// Stop the RTC time counter
+    ///
+    /// # Note
+    ///
+    /// Clears the Time Counter Enable (TCE) bit in the status register.
+    pub fn stop(&self) {
+        let rtc = unsafe { &*I::ptr() };
+        rtc.sr().modify(|_, w| w.tce().clear_bit());
+    }
+
+    /// Enable specific RTC interrupts
+    ///
+    /// # Arguments
+    ///
+    /// * `mask` - Bitmask of interrupts to enable (use RtcInterruptEnable constants)
+    ///
+    /// # Note
+    ///
+    /// This function enables the specified interrupt types and resets the alarm occurred flag.
+    /// Available interrupts:
+    /// - Time Invalid Interrupt
+    /// - Time Overflow Interrupt  
+    /// - Alarm Interrupt
+    /// - Seconds Interrupt
+    pub fn set_interrupt(&self, mask: u32) {
+        let rtc = unsafe { &*I::ptr() };
+
+        if (RtcInterruptEnable::RTC_TIME_INVALID_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.tiie().tiie_1());
+        }
+        if (RtcInterruptEnable::RTC_TIME_OVERFLOW_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.toie().toie_1());
+        }
+        if (RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.taie().taie_1());
+        }
+        if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.tsie().tsie_1());
+        }
+    }
+
+    /// Disable specific RTC interrupts
+    ///
+    /// # Arguments
+    ///
+    /// * `mask` - Bitmask of interrupts to disable (use RtcInterruptEnable constants)
+    ///
+    /// # Note
+    ///
+    /// This function disables the specified interrupt types.
+    pub fn disable_interrupt(&self, mask: u32) {
+        let rtc = unsafe { &*I::ptr() };
+
+        if (RtcInterruptEnable::RTC_TIME_INVALID_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.tiie().tiie_0());
+        }
+        if (RtcInterruptEnable::RTC_TIME_OVERFLOW_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.toie().toie_0());
+        }
+        if (RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.taie().taie_0());
+        }
+        if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.tsie().tsie_0());
+        }
+    }
+
+    /// Clear the alarm interrupt flag
+    ///
+    /// # Note
+    ///
+    /// This function clears the Time Alarm Interrupt Enable bit.
+    pub fn clear_alarm_flag(&self) {
+        let rtc = unsafe { &*I::ptr() };
+        rtc.ier().modify(|_, w| w.taie().clear_bit());
+    }
+
+    /// Wait for an RTC alarm to trigger.
+    ///
+    /// # Arguments
+    ///
+    /// * `alarm` - The date and time when the alarm should trigger
+    /// This function will wait until the RTC alarm is triggered.
+    /// If no alarm is scheduled, it will wait indefinitely until one is scheduled and triggered.
+    pub async fn wait_for_alarm(&mut self, alarm: RtcDateTime) {
+        let wait = WAKER.subscribe().await;
+
+        self.set_alarm(alarm);
+        self.start();
+
+        // REVISIT: propagate error?
+        let _ = wait.await;
+
+        // Clear the interrupt and disable the alarm after waking up
+        self.disable_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE);
+    }
+}
+
+/// RTC interrupt handler
+///
+/// This struct implements the interrupt handler for RTC events.
+impl<T: Instance> Handler<T::Interrupt> for InterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        let rtc = &*pac::Rtc0::ptr();
+        // Check if this is actually a time alarm interrupt
+        let sr = rtc.sr().read();
+        if sr.taf().bit_is_set() {
+            rtc.ier().modify(|_, w| w.taie().clear_bit());
+            WAKER.wake();
+        }
+    }
+}
diff --git a/embassy-net-esp-hosted/CHANGELOG.md b/embassy-net-esp-hosted/CHANGELOG.md
index d8b912295..6991b39fd 100644
--- a/embassy-net-esp-hosted/CHANGELOG.md
+++ b/embassy-net-esp-hosted/CHANGELOG.md
@@ -11,6 +11,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Add an `Interface` trait to allow using other interface transports.
 - Switch to `micropb` for protobuf.
 - Update protos to latest `esp-hosted-fg`.
+- Add support for OTA firmware updates.
 
 ## 0.2.1 - 2025-08-26
 
diff --git a/embassy-net-esp-hosted/src/control.rs b/embassy-net-esp-hosted/src/control.rs
index 38ec648b4..eb79593f6 100644
--- a/embassy-net-esp-hosted/src/control.rs
+++ b/embassy-net-esp-hosted/src/control.rs
@@ -146,6 +146,43 @@ impl<'a> Control<'a> {
         Ok(())
     }
 
+    /// Initiate a firmware update.
+    pub async fn ota_begin(&mut self) -> Result<(), Error> {
+        let req = proto::CtrlMsg_Req_OTABegin {};
+        ioctl!(self, ReqOtaBegin, RespOtaBegin, req, resp);
+        Ok(())
+    }
+
+    /// Write slice of firmware to a device.
+    ///
+    /// [`ota_begin`] must be called first.
+    ///
+    /// The slice is split into chunks that can be sent across
+    /// the ioctl protocol to the wifi adapter.
+    pub async fn ota_write(&mut self, data: &[u8]) -> Result<(), Error> {
+        for chunk in data.chunks(256) {
+            let req = proto::CtrlMsg_Req_OTAWrite {
+                ota_data: heapless::Vec::from_slice(chunk).unwrap(),
+            };
+            ioctl!(self, ReqOtaWrite, RespOtaWrite, req, resp);
+        }
+        Ok(())
+    }
+
+    /// End the OTA session.
+    ///
+    /// [`ota_begin`] must be called first.
+    ///
+    /// NOTE: Will reset the wifi adapter after 5 seconds.
+    pub async fn ota_end(&mut self) -> Result<(), Error> {
+        let req = proto::CtrlMsg_Req_OTAEnd {};
+        ioctl!(self, ReqOtaEnd, RespOtaEnd, req, resp);
+        self.shared.ota_done();
+        // Wait for re-init
+        self.init().await?;
+        Ok(())
+    }
+
     /// duration in seconds, clamped to [10, 3600]
     async fn set_heartbeat(&mut self, duration: u32) -> Result<(), Error> {
         let req = proto::CtrlMsg_Req_ConfigHeartbeat {
@@ -175,7 +212,8 @@ impl<'a> Control<'a> {
     async fn ioctl(&mut self, msg: &mut CtrlMsg) -> Result<(), Error> {
         debug!("ioctl req: {:?}", &msg);
 
-        let mut buf = [0u8; 128];
+        // Theoretical max overhead is 29 bytes. Biggest message is OTA write with 256 bytes.
+        let mut buf = [0u8; 256 + 29];
         let buf_len = buf.len();
 
         let mut encoder = PbEncoder::new(&mut buf[..]);
diff --git a/embassy-net-esp-hosted/src/ioctl.rs b/embassy-net-esp-hosted/src/ioctl.rs
index a516f80c7..de0f867e8 100644
--- a/embassy-net-esp-hosted/src/ioctl.rs
+++ b/embassy-net-esp-hosted/src/ioctl.rs
@@ -23,16 +23,23 @@ pub struct Shared(RefCell<SharedInner>);
 
 struct SharedInner {
     ioctl: IoctlState,
-    is_init: bool,
+    state: ControlState,
     control_waker: WakerRegistration,
     runner_waker: WakerRegistration,
 }
 
+#[derive(Clone, Copy)]
+pub(crate) enum ControlState {
+    Init,
+    Reboot,
+    Ready,
+}
+
 impl Shared {
     pub fn new() -> Self {
         Self(RefCell::new(SharedInner {
             ioctl: IoctlState::Done { resp_len: 0 },
-            is_init: false,
+            state: ControlState::Init,
             control_waker: WakerRegistration::new(),
             runner_waker: WakerRegistration::new(),
         }))
@@ -99,18 +106,30 @@ impl Shared {
         }
     }
 
+    // ota
+    pub fn ota_done(&self) {
+        let mut this = self.0.borrow_mut();
+        this.state = ControlState::Reboot;
+    }
+
     // // // // // // // // // // // // // // // // // // // //
+    //
+    // check if ota is in progress
+    pub(crate) fn state(&self) -> ControlState {
+        let this = self.0.borrow();
+        this.state
+    }
 
     pub fn init_done(&self) {
         let mut this = self.0.borrow_mut();
-        this.is_init = true;
+        this.state = ControlState::Ready;
         this.control_waker.wake();
     }
 
     pub fn init_wait(&self) -> impl Future<Output = ()> + '_ {
         poll_fn(|cx| {
             let mut this = self.0.borrow_mut();
-            if this.is_init {
+            if let ControlState::Ready = this.state {
                 Poll::Ready(())
             } else {
                 this.control_waker.register(cx.waker());
diff --git a/embassy-net-esp-hosted/src/lib.rs b/embassy-net-esp-hosted/src/lib.rs
index d882af8cf..2c7377281 100644
--- a/embassy-net-esp-hosted/src/lib.rs
+++ b/embassy-net-esp-hosted/src/lib.rs
@@ -234,6 +234,11 @@ where
                     tx_buf[..PayloadHeader::SIZE].fill(0);
                 }
                 Either4::Fourth(()) => {
+                    // Extend the deadline if initializing
+                    if let ioctl::ControlState::Reboot = self.shared.state() {
+                        self.heartbeat_deadline = Instant::now() + HEARTBEAT_MAX_GAP;
+                        continue;
+                    }
                     panic!("heartbeat from esp32 stopped")
                 }
             }
diff --git a/embassy-net-esp-hosted/src/proto.rs b/embassy-net-esp-hosted/src/proto.rs
index 74c67bd61..09bec8984 100644
--- a/embassy-net-esp-hosted/src/proto.rs
+++ b/embassy-net-esp-hosted/src/proto.rs
@@ -16,7 +16,7 @@ Switch to a proper script when https://github.com/YuhanLiin/micropb/issues/30 is
     // Special config for things that need to be larger
     g.configure(
         ".CtrlMsg_Req_OTAWrite.ota_data",
-        micropb_gen::Config::new().max_bytes(1024),
+        micropb_gen::Config::new().max_bytes(256),
     );
     g.configure(
         ".CtrlMsg_Event_ESPInit.init_data",
@@ -4296,28 +4296,28 @@ impl ::micropb::MessageEncode for CtrlMsg_Resp_OTABegin {
 #[derive(Debug, Default, PartialEq, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct CtrlMsg_Req_OTAWrite {
-    pub r#ota_data: ::micropb::heapless::Vec<u8, 1024>,
+    pub r#ota_data: ::micropb::heapless::Vec<u8, 256>,
 }
 impl CtrlMsg_Req_OTAWrite {
     ///Return a reference to `ota_data`
     #[inline]
-    pub fn r#ota_data(&self) -> &::micropb::heapless::Vec<u8, 1024> {
+    pub fn r#ota_data(&self) -> &::micropb::heapless::Vec<u8, 256> {
         &self.r#ota_data
     }
     ///Return a mutable reference to `ota_data`
     #[inline]
-    pub fn mut_ota_data(&mut self) -> &mut ::micropb::heapless::Vec<u8, 1024> {
+    pub fn mut_ota_data(&mut self) -> &mut ::micropb::heapless::Vec<u8, 256> {
         &mut self.r#ota_data
     }
     ///Set the value of `ota_data`
     #[inline]
-    pub fn set_ota_data(&mut self, value: ::micropb::heapless::Vec<u8, 1024>) -> &mut Self {
+    pub fn set_ota_data(&mut self, value: ::micropb::heapless::Vec<u8, 256>) -> &mut Self {
         self.r#ota_data = value.into();
         self
     }
     ///Builder method that sets the value of `ota_data`. Useful for initializing the message.
     #[inline]
-    pub fn init_ota_data(mut self, value: ::micropb::heapless::Vec<u8, 1024>) -> Self {
+    pub fn init_ota_data(mut self, value: ::micropb::heapless::Vec<u8, 256>) -> Self {
         self.r#ota_data = value.into();
         self
     }
diff --git a/embassy-net-nrf91/Cargo.toml b/embassy-net-nrf91/Cargo.toml
index 8cf11f1fb..cd9bf2987 100644
--- a/embassy-net-nrf91/Cargo.toml
+++ b/embassy-net-nrf91/Cargo.toml
@@ -18,7 +18,7 @@ log = ["dep:log"]
 defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.14", optional = true }
 
-nrf-pac = { version = "0.1.0", git = "https://github.com/embassy-rs/nrf-pac.git", rev = "176dc4afe1dd8df78f3cbda4479ab5151aa32252" }
+nrf-pac = { version = "0.1.0", git = "https://github.com/embassy-rs/nrf-pac.git", rev = "52fd51ce762a3d3a81660dea62947e6d2d1e9d91" }
 cortex-m = "0.7.7"
 
 embassy-time = { version = "0.5.0", path = "../embassy-time" }
diff --git a/embassy-nrf/CHANGELOG.md b/embassy-nrf/CHANGELOG.md
index 5657ddcfb..9c53e66a7 100644
--- a/embassy-nrf/CHANGELOG.md
+++ b/embassy-nrf/CHANGELOG.md
@@ -29,6 +29,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - changed: add workaround for anomaly 66 on nrf52
 - added: expose PPI events available on SPIS peripheral
 - added: add basic GRTC time driver support for nRF54L
+* added: support for nrf54l10 and nrf54l05
+* added: expose uicr write functions
+* added: support for nrf54lm20a
 
 ## 0.8.0 - 2025-09-30
 
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index f73772682..ee070f0c0 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -25,6 +25,11 @@ build = [
     {target = "thumbv8m.main-none-eabihf", features = ["gpiote", "nrf5340-net", "time", "time-driver-rtc1"]},
     {target = "thumbv8m.main-none-eabihf", features = ["gpiote", "nrf54l15-app-s", "time", "time-driver-grtc"]},
     {target = "thumbv8m.main-none-eabihf", features = ["gpiote", "nrf54l15-app-ns", "time", "time-driver-grtc"]},
+    {target = "thumbv8m.main-none-eabihf", features = ["gpiote", "nrf54l10-app-s", "time", "time-driver-grtc"]},
+    {target = "thumbv8m.main-none-eabihf", features = ["gpiote", "nrf54l10-app-ns", "time", "time-driver-grtc"]},
+    {target = "thumbv8m.main-none-eabihf", features = ["gpiote", "nrf54l05-app-s", "time", "time-driver-grtc"]},
+    {target = "thumbv8m.main-none-eabihf", features = ["gpiote", "nrf54l05-app-ns", "time", "time-driver-grtc"]},
+    {target = "thumbv8m.main-none-eabihf", features = ["gpiote", "nrf54lm20-app-s", "time", "time-driver-grtc"]},
     {target = "thumbv7em-none-eabi", features = ["gpiote", "nrf52840", "time"]},
     {target = "thumbv7em-none-eabi", features = ["gpiote", "nrf52840", "time-driver-rtc1"]},
     {target = "thumbv7em-none-eabi", features = ["gpiote", "nrf52840", "time", "time-driver-rtc1"]},
@@ -130,6 +135,16 @@ nrf5340-net = ["_nrf5340-net"]
 nrf54l15-app-s = ["_nrf54l15-app", "_s", "_multi_wdt"]
 ## nRF54L15 application core in Non-Secure mode
 nrf54l15-app-ns = ["_nrf54l15-app", "_ns"]
+## nRF54L10 application core in Secure mode
+nrf54l10-app-s = ["_nrf54l10-app", "_s", "_multi_wdt"]
+## nRF54L10 application core in Non-Secure mode
+nrf54l10-app-ns = ["_nrf54l10-app", "_ns"]
+## nRF54L05 application core in Secure mode
+nrf54l05-app-s = ["_nrf54l05-app", "_s", "_multi_wdt"]
+## nRF54L05 application core in Non-Secure mode
+nrf54l05-app-ns = ["_nrf54l05-app", "_ns"]
+## nRF54LM20 application core in Secure mode
+nrf54lm20-app-s = ["_nrf54lm20-app", "_s", "_multi_wdt"]
 
 ## nRF9160 in Secure mode
 nrf9160-s = ["_nrf9160", "_s", "_nrf91"]
@@ -153,6 +168,12 @@ _nrf5340-net = ["_nrf5340", "nrf-pac/nrf5340-net"]
 _nrf5340 = ["_gpio-p1", "_dppi"]
 _nrf54l15-app = ["_nrf54l15", "nrf-pac/nrf54l15-app"]
 _nrf54l15 = ["_nrf54l", "_gpio-p1", "_gpio-p2"]
+_nrf54l10-app = ["_nrf54l10", "nrf-pac/nrf54l10-app"]
+_nrf54l10 = ["_nrf54l", "_gpio-p1", "_gpio-p2"]
+_nrf54l05-app = ["_nrf54l05", "nrf-pac/nrf54l05-app"]
+_nrf54l05 = ["_nrf54l", "_gpio-p1", "_gpio-p2"]
+_nrf54lm20-app = ["_nrf54lm20", "nrf-pac/nrf54lm20a-app"]
+_nrf54lm20 = ["_nrf54l", "_gpio-p1", "_gpio-p2"]
 _nrf54l = ["_dppi", "_grtc"]
 
 _nrf9160 = ["nrf-pac/nrf9160", "_dppi", "_spi-v1"]
@@ -202,7 +223,7 @@ embedded-io-async = { version = "0.6.1" }
 rand-core-06 = { package = "rand_core", version = "0.6" }
 rand-core-09 = { package = "rand_core", version = "0.9" }
 
-nrf-pac = { version = "0.1.0", git = "https://github.com/embassy-rs/nrf-pac.git", rev = "176dc4afe1dd8df78f3cbda4479ab5151aa32252" }
+nrf-pac = { version = "0.1.0", git = "https://github.com/embassy-rs/nrf-pac.git", rev = "52fd51ce762a3d3a81660dea62947e6d2d1e9d91" }
 
 defmt = { version = "1.0.1", optional = true }
 bitflags = "2.4.2"
diff --git a/embassy-nrf/src/chips/nrf54l05_app.rs b/embassy-nrf/src/chips/nrf54l05_app.rs
new file mode 100644
index 000000000..8e6595248
--- /dev/null
+++ b/embassy-nrf/src/chips/nrf54l05_app.rs
@@ -0,0 +1,746 @@
+/// Peripheral Access Crate
+#[allow(unused_imports)]
+#[rustfmt::skip]
+pub mod pac {
+    pub use nrf_pac::*;
+
+    #[cfg(feature = "_ns")]
+    #[doc(no_inline)]
+    pub use nrf_pac::{
+        FICR_NS as FICR,
+        DPPIC00_NS as DPPIC00,
+        PPIB00_NS as PPIB00,
+        PPIB01_NS as PPIB01,
+        AAR00_NS as AAR00,
+        CCM00_NS as CCM00,
+        ECB00_NS as ECB00,
+        SPIM00_NS as SPIM00,
+        SPIS00_NS as SPIS00,
+        UARTE00_NS as UARTE00,
+        VPR00_NS as VPR00,
+        P2_NS as P2,
+        CTRLAP_NS as CTRLAP,
+        TAD_NS as TAD,
+        TIMER00_NS as TIMER00,
+        DPPIC10_NS as DPPIC10,
+        PPIB10_NS as PPIB10,
+        PPIB11_NS as PPIB11,
+        TIMER10_NS as TIMER10,
+        EGU10_NS as EGU10,
+        RADIO_NS as RADIO,
+        DPPIC20_NS as DPPIC20,
+        PPIB20_NS as PPIB20,
+        PPIB21_NS as PPIB21,
+        PPIB22_NS as PPIB22,
+        SPIM20_NS as SPIM20,
+        SPIS20_NS as SPIS20,
+        TWIM20_NS as TWIM20,
+        TWIS20_NS as TWIS20,
+        UARTE20_NS as UARTE20,
+        SPIM21_NS as SPIM21,
+        SPIS21_NS as SPIS21,
+        TWIM21_NS as TWIM21,
+        TWIS21_NS as TWIS21,
+        UARTE21_NS as UARTE21,
+        SPIM22_NS as SPIM22,
+        SPIS22_NS as SPIS22,
+        TWIM22_NS as TWIM22,
+        TWIS22_NS as TWIS22,
+        UARTE22_NS as UARTE22,
+        EGU20_NS as EGU20,
+        TIMER20_NS as TIMER20,
+        TIMER21_NS as TIMER21,
+        TIMER22_NS as TIMER22,
+        TIMER23_NS as TIMER23,
+        TIMER24_NS as TIMER24,
+        MEMCONF_NS as MEMCONF,
+        PDM20_NS as PDM20,
+        PDM21_NS as PDM21,
+        PWM20_NS as PWM20,
+        PWM21_NS as PWM21,
+        PWM22_NS as PWM22,
+        SAADC_NS as SAADC,
+        NFCT_NS as NFCT,
+        TEMP_NS as TEMP,
+        P1_NS as P1,
+        GPIOTE20_NS as GPIOTE20,
+        I2S20_NS as I2S20,
+        QDEC20_NS as QDEC20,
+        QDEC21_NS as QDEC21,
+        GRTC_NS as GRTC,
+        DPPIC30_NS as DPPIC30,
+        PPIB30_NS as PPIB30,
+        SPIM30_NS as SPIM30,
+        SPIS30_NS as SPIS30,
+        TWIM30_NS as TWIM30,
+        TWIS30_NS as TWIS30,
+        UARTE30_NS as UARTE30,
+        COMP_NS as COMP,
+        LPCOMP_NS as LPCOMP,
+        WDT31_NS as WDT31,
+        P0_NS as P0,
+        GPIOTE30_NS as GPIOTE30,
+        CLOCK_NS as CLOCK,
+        POWER_NS as POWER,
+        RESET_NS as RESET,
+        OSCILLATORS_NS as OSCILLATORS,
+        REGULATORS_NS as REGULATORS,
+        TPIU_NS as TPIU,
+        ETM_NS as ETM,
+    };
+
+    #[cfg(feature = "_s")]
+    #[doc(no_inline)]
+    pub use nrf_pac::{
+        FICR_NS as FICR,
+        SICR_S as SICR,
+        ICACHEDATA_S as ICACHEDATA,
+        ICACHEINFO_S as ICACHEINFO,
+        SWI00_S as SWI00,
+        SWI01_S as SWI01,
+        SWI02_S as SWI02,
+        SWI03_S as SWI03,
+        SPU00_S as SPU00,
+        MPC00_S as MPC00,
+        DPPIC00_S as DPPIC00,
+        PPIB00_S as PPIB00,
+        PPIB01_S as PPIB01,
+        KMU_S as KMU,
+        AAR00_S as AAR00,
+        CCM00_S as CCM00,
+        ECB00_S as ECB00,
+        CRACEN_S as CRACEN,
+        SPIM00_S as SPIM00,
+        SPIS00_S as SPIS00,
+        UARTE00_S as UARTE00,
+        GLITCHDET_S as GLITCHDET,
+        RRAMC_S as RRAMC,
+        VPR00_S as VPR00,
+        P2_S as P2,
+        CTRLAP_S as CTRLAP,
+        TAD_S as TAD,
+        TIMER00_S as TIMER00,
+        SPU10_S as SPU10,
+        DPPIC10_S as DPPIC10,
+        PPIB10_S as PPIB10,
+        PPIB11_S as PPIB11,
+        TIMER10_S as TIMER10,
+        EGU10_S as EGU10,
+        RADIO_S as RADIO,
+        SPU20_S as SPU20,
+        DPPIC20_S as DPPIC20,
+        PPIB20_S as PPIB20,
+        PPIB21_S as PPIB21,
+        PPIB22_S as PPIB22,
+        SPIM20_S as SPIM20,
+        SPIS20_S as SPIS20,
+        TWIM20_S as TWIM20,
+        TWIS20_S as TWIS20,
+        UARTE20_S as UARTE20,
+        SPIM21_S as SPIM21,
+        SPIS21_S as SPIS21,
+        TWIM21_S as TWIM21,
+        TWIS21_S as TWIS21,
+        UARTE21_S as UARTE21,
+        SPIM22_S as SPIM22,
+        SPIS22_S as SPIS22,
+        TWIM22_S as TWIM22,
+        TWIS22_S as TWIS22,
+        UARTE22_S as UARTE22,
+        EGU20_S as EGU20,
+        TIMER20_S as TIMER20,
+        TIMER21_S as TIMER21,
+        TIMER22_S as TIMER22,
+        TIMER23_S as TIMER23,
+        TIMER24_S as TIMER24,
+        MEMCONF_S as MEMCONF,
+        PDM20_S as PDM20,
+        PDM21_S as PDM21,
+        PWM20_S as PWM20,
+        PWM21_S as PWM21,
+        PWM22_S as PWM22,
+        SAADC_S as SAADC,
+        NFCT_S as NFCT,
+        TEMP_S as TEMP,
+        P1_S as P1,
+        GPIOTE20_S as GPIOTE20,
+        TAMPC_S as TAMPC,
+        I2S20_S as I2S20,
+        QDEC20_S as QDEC20,
+        QDEC21_S as QDEC21,
+        GRTC_S as GRTC,
+        SPU30_S as SPU30,
+        DPPIC30_S as DPPIC30,
+        PPIB30_S as PPIB30,
+        SPIM30_S as SPIM30,
+        SPIS30_S as SPIS30,
+        TWIM30_S as TWIM30,
+        TWIS30_S as TWIS30,
+        UARTE30_S as UARTE30,
+        COMP_S as COMP,
+        LPCOMP_S as LPCOMP,
+        WDT30_S as WDT30,
+        WDT31_S as WDT31,
+        P0_S as P0,
+        GPIOTE30_S as GPIOTE30,
+        CLOCK_S as CLOCK,
+        POWER_S as POWER,
+        RESET_S as RESET,
+        OSCILLATORS_S as OSCILLATORS,
+        REGULATORS_S as REGULATORS,
+        CRACENCORE_S as CRACENCORE,
+        CPUC_S as CPUC,
+        ICACHE_S as ICACHE,
+    };
+}
+
+/// The maximum buffer size that the EasyDMA can send/recv in one operation.
+pub const EASY_DMA_SIZE: usize = (1 << 16) - 1;
+pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
+
+// 1.5 MB NVM
+#[allow(unused)]
+pub const FLASH_SIZE: usize = 1524 * 1024;
+
+embassy_hal_internal::peripherals! {
+    // PPI
+    PPI00_CH0,
+    PPI00_CH1,
+    PPI00_CH2,
+    PPI00_CH3,
+    PPI00_CH4,
+    PPI00_CH5,
+    PPI00_CH6,
+    PPI00_CH7,
+
+    PPI10_CH0,
+    PPI10_CH1,
+    PPI10_CH2,
+    PPI10_CH3,
+    PPI10_CH4,
+    PPI10_CH5,
+    PPI10_CH6,
+    PPI10_CH7,
+    PPI10_CH8,
+    PPI10_CH9,
+    PPI10_CH10,
+    PPI10_CH11,
+    PPI10_CH12,
+    PPI10_CH13,
+    PPI10_CH14,
+    PPI10_CH15,
+    PPI10_CH16,
+    PPI10_CH17,
+    PPI10_CH18,
+    PPI10_CH19,
+    PPI10_CH20,
+    PPI10_CH21,
+    PPI10_CH22,
+    PPI10_CH23,
+
+    PPI20_CH0,
+    PPI20_CH1,
+    PPI20_CH2,
+    PPI20_CH3,
+    PPI20_CH4,
+    PPI20_CH5,
+    PPI20_CH6,
+    PPI20_CH7,
+    PPI20_CH8,
+    PPI20_CH9,
+    PPI20_CH10,
+    PPI20_CH11,
+    PPI20_CH12,
+    PPI20_CH13,
+    PPI20_CH14,
+    PPI20_CH15,
+
+    PPI30_CH0,
+    PPI30_CH1,
+    PPI30_CH2,
+    PPI30_CH3,
+
+    PPI00_GROUP0,
+    PPI00_GROUP1,
+
+    PPI10_GROUP0,
+    PPI10_GROUP1,
+    PPI10_GROUP2,
+    PPI10_GROUP3,
+    PPI10_GROUP4,
+    PPI10_GROUP5,
+
+    PPI20_GROUP0,
+    PPI20_GROUP1,
+    PPI20_GROUP2,
+    PPI20_GROUP3,
+    PPI20_GROUP4,
+    PPI20_GROUP5,
+
+    PPI30_GROUP0,
+    PPI30_GROUP1,
+
+    // PPI BRIDGE channels
+    PPIB00_CH0,
+    PPIB00_CH1,
+    PPIB00_CH2,
+    PPIB00_CH3,
+    PPIB00_CH4,
+    PPIB00_CH5,
+    PPIB00_CH6,
+    PPIB00_CH7,
+
+    PPIB01_CH0,
+    PPIB01_CH1,
+    PPIB01_CH2,
+    PPIB01_CH3,
+    PPIB01_CH4,
+    PPIB01_CH5,
+    PPIB01_CH6,
+    PPIB01_CH7,
+
+    PPIB10_CH0,
+    PPIB10_CH1,
+    PPIB10_CH2,
+    PPIB10_CH3,
+    PPIB10_CH4,
+    PPIB10_CH5,
+    PPIB10_CH6,
+    PPIB10_CH7,
+
+    PPIB11_CH0,
+    PPIB11_CH1,
+    PPIB11_CH2,
+    PPIB11_CH3,
+    PPIB11_CH4,
+    PPIB11_CH5,
+    PPIB11_CH6,
+    PPIB11_CH7,
+    PPIB11_CH8,
+    PPIB11_CH9,
+    PPIB11_CH10,
+    PPIB11_CH11,
+    PPIB11_CH12,
+    PPIB11_CH13,
+    PPIB11_CH14,
+    PPIB11_CH15,
+
+    PPIB20_CH0,
+    PPIB20_CH1,
+    PPIB20_CH2,
+    PPIB20_CH3,
+    PPIB20_CH4,
+    PPIB20_CH5,
+    PPIB20_CH6,
+    PPIB20_CH7,
+
+    PPIB21_CH0,
+    PPIB21_CH1,
+    PPIB21_CH2,
+    PPIB21_CH3,
+    PPIB21_CH4,
+    PPIB21_CH5,
+    PPIB21_CH6,
+    PPIB21_CH7,
+    PPIB21_CH8,
+    PPIB21_CH9,
+    PPIB21_CH10,
+    PPIB21_CH11,
+    PPIB21_CH12,
+    PPIB21_CH13,
+    PPIB21_CH14,
+    PPIB21_CH15,
+
+    PPIB22_CH0,
+    PPIB22_CH1,
+    PPIB22_CH2,
+    PPIB22_CH3,
+
+    PPIB30_CH0,
+    PPIB30_CH1,
+    PPIB30_CH2,
+    PPIB30_CH3,
+
+    // Timers
+    TIMER00,
+    TIMER10,
+    TIMER20,
+    TIMER21,
+    TIMER22,
+    TIMER23,
+    TIMER24,
+
+    // GPIO port 0
+    P0_00,
+    P0_01,
+    P0_02,
+    P0_03,
+    P0_04,
+    P0_05,
+    P0_06,
+
+    // GPIO port 1
+    P1_00,
+    P1_01,
+    P1_02,
+    P1_03,
+    P1_04,
+    P1_05,
+    P1_06,
+    P1_07,
+    P1_08,
+    P1_09,
+    P1_10,
+    P1_11,
+    P1_12,
+    P1_13,
+    P1_14,
+    P1_15,
+    P1_16,
+
+
+    // GPIO port 2
+    P2_00,
+    P2_01,
+    P2_02,
+    P2_03,
+    P2_04,
+    P2_05,
+    P2_06,
+    P2_07,
+    P2_08,
+    P2_09,
+    P2_10,
+
+    // GRTC
+    GRTC_CH0,
+    #[cfg(not(feature = "time-driver-grtc"))]
+    GRTC_CH1,
+    GRTC_CH2,
+    GRTC_CH3,
+    GRTC_CH4,
+    GRTC_CH5,
+    GRTC_CH6,
+    GRTC_CH7,
+    GRTC_CH8,
+    GRTC_CH9,
+    GRTC_CH10,
+    GRTC_CH11,
+
+    // PWM
+    PWM20,
+    PWM21,
+    PWM22,
+
+    // SERIAL
+    SERIAL00,
+    SERIAL20,
+    SERIAL21,
+    SERIAL22,
+    SERIAL30,
+
+    // SAADC
+    SAADC,
+
+    // RADIO
+    RADIO,
+
+
+    // GPIOTE instances
+    GPIOTE20,
+    GPIOTE30,
+
+    // GPIOTE channels
+    GPIOTE20_CH0,
+    GPIOTE20_CH1,
+    GPIOTE20_CH2,
+    GPIOTE20_CH3,
+    GPIOTE20_CH4,
+    GPIOTE20_CH5,
+    GPIOTE20_CH6,
+    GPIOTE20_CH7,
+    GPIOTE30_CH0,
+    GPIOTE30_CH1,
+    GPIOTE30_CH2,
+    GPIOTE30_CH3,
+
+    // CRACEN
+    #[cfg(feature = "_s")]
+    CRACEN,
+
+    #[cfg(feature = "_s")]
+    // RRAMC
+    RRAMC,
+
+    // TEMP
+    TEMP,
+
+    // WDT
+    #[cfg(feature = "_ns")]
+    WDT,
+    #[cfg(feature = "_s")]
+    WDT0,
+    #[cfg(feature = "_s")]
+    WDT1,
+}
+
+impl_pin!(P0_00, 0, 0);
+impl_pin!(P0_01, 0, 1);
+impl_pin!(P0_02, 0, 2);
+impl_pin!(P0_03, 0, 3);
+impl_pin!(P0_04, 0, 4);
+impl_pin!(P0_05, 0, 5);
+impl_pin!(P0_06, 0, 6);
+
+impl_pin!(P1_00, 1, 0);
+impl_pin!(P1_01, 1, 1);
+impl_pin!(P1_02, 1, 2);
+impl_pin!(P1_03, 1, 3);
+impl_pin!(P1_04, 1, 4);
+impl_pin!(P1_05, 1, 5);
+impl_pin!(P1_06, 1, 6);
+impl_pin!(P1_07, 1, 7);
+impl_pin!(P1_08, 1, 8);
+impl_pin!(P1_09, 1, 9);
+impl_pin!(P1_10, 1, 10);
+impl_pin!(P1_11, 1, 11);
+impl_pin!(P1_12, 1, 12);
+impl_pin!(P1_13, 1, 13);
+impl_pin!(P1_14, 1, 14);
+impl_pin!(P1_15, 1, 15);
+impl_pin!(P1_16, 1, 16);
+
+impl_pin!(P2_00, 2, 0);
+impl_pin!(P2_01, 2, 1);
+impl_pin!(P2_02, 2, 2);
+impl_pin!(P2_03, 2, 3);
+impl_pin!(P2_04, 2, 4);
+impl_pin!(P2_05, 2, 5);
+impl_pin!(P2_06, 2, 6);
+impl_pin!(P2_07, 2, 7);
+impl_pin!(P2_08, 2, 8);
+impl_pin!(P2_09, 2, 9);
+impl_pin!(P2_10, 2, 10);
+
+cfg_if::cfg_if! {
+    if #[cfg(feature = "gpiote")] {
+        impl_gpiote_pin!(P0_00, GPIOTE30);
+        impl_gpiote_pin!(P0_01, GPIOTE30);
+        impl_gpiote_pin!(P0_02, GPIOTE30);
+        impl_gpiote_pin!(P0_03, GPIOTE30);
+        impl_gpiote_pin!(P0_04, GPIOTE30);
+        impl_gpiote_pin!(P0_05, GPIOTE30);
+        impl_gpiote_pin!(P0_06, GPIOTE30);
+
+        impl_gpiote_pin!(P1_00, GPIOTE20);
+        impl_gpiote_pin!(P1_01, GPIOTE20);
+        impl_gpiote_pin!(P1_02, GPIOTE20);
+        impl_gpiote_pin!(P1_03, GPIOTE20);
+        impl_gpiote_pin!(P1_04, GPIOTE20);
+        impl_gpiote_pin!(P1_05, GPIOTE20);
+        impl_gpiote_pin!(P1_06, GPIOTE20);
+        impl_gpiote_pin!(P1_07, GPIOTE20);
+        impl_gpiote_pin!(P1_08, GPIOTE20);
+        impl_gpiote_pin!(P1_09, GPIOTE20);
+        impl_gpiote_pin!(P1_10, GPIOTE20);
+        impl_gpiote_pin!(P1_11, GPIOTE20);
+        impl_gpiote_pin!(P1_12, GPIOTE20);
+        impl_gpiote_pin!(P1_13, GPIOTE20);
+        impl_gpiote_pin!(P1_14, GPIOTE20);
+        impl_gpiote_pin!(P1_15, GPIOTE20);
+        impl_gpiote_pin!(P1_16, GPIOTE20);
+    }
+}
+
+#[cfg(feature = "_ns")]
+impl_wdt!(WDT, WDT31, WDT31, 0);
+#[cfg(feature = "_s")]
+impl_wdt!(WDT0, WDT31, WDT31, 0);
+#[cfg(feature = "_s")]
+impl_wdt!(WDT1, WDT30, WDT30, 1);
+// DPPI00 channels
+impl_ppi_channel!(PPI00_CH0, DPPIC00, 0 => configurable);
+impl_ppi_channel!(PPI00_CH1, DPPIC00, 1 => configurable);
+impl_ppi_channel!(PPI00_CH2, DPPIC00, 2 => configurable);
+impl_ppi_channel!(PPI00_CH3, DPPIC00, 3 => configurable);
+impl_ppi_channel!(PPI00_CH4, DPPIC00, 4 => configurable);
+impl_ppi_channel!(PPI00_CH5, DPPIC00, 5 => configurable);
+impl_ppi_channel!(PPI00_CH6, DPPIC00, 6 => configurable);
+impl_ppi_channel!(PPI00_CH7, DPPIC00, 7 => configurable);
+
+// DPPI10 channels
+impl_ppi_channel!(PPI10_CH0, DPPIC10, 0 => static);
+
+// DPPI20 channels
+impl_ppi_channel!(PPI20_CH0, DPPIC20, 0 => configurable);
+impl_ppi_channel!(PPI20_CH1, DPPIC20, 1 => configurable);
+impl_ppi_channel!(PPI20_CH2, DPPIC20, 2 => configurable);
+impl_ppi_channel!(PPI20_CH3, DPPIC20, 3 => configurable);
+impl_ppi_channel!(PPI20_CH4, DPPIC20, 4 => configurable);
+impl_ppi_channel!(PPI20_CH5, DPPIC20, 5 => configurable);
+impl_ppi_channel!(PPI20_CH6, DPPIC20, 6 => configurable);
+impl_ppi_channel!(PPI20_CH7, DPPIC20, 7 => configurable);
+impl_ppi_channel!(PPI20_CH8, DPPIC20, 8 => configurable);
+impl_ppi_channel!(PPI20_CH9, DPPIC20, 9 => configurable);
+impl_ppi_channel!(PPI20_CH10, DPPIC20, 10 => configurable);
+impl_ppi_channel!(PPI20_CH11, DPPIC20, 11 => configurable);
+impl_ppi_channel!(PPI20_CH12, DPPIC20, 12 => configurable);
+impl_ppi_channel!(PPI20_CH13, DPPIC20, 13 => configurable);
+impl_ppi_channel!(PPI20_CH14, DPPIC20, 14 => configurable);
+impl_ppi_channel!(PPI20_CH15, DPPIC20, 15 => configurable);
+
+// DPPI30 channels
+impl_ppi_channel!(PPI30_CH0, DPPIC30, 0 => configurable);
+impl_ppi_channel!(PPI30_CH1, DPPIC30, 1 => configurable);
+impl_ppi_channel!(PPI30_CH2, DPPIC30, 2 => configurable);
+impl_ppi_channel!(PPI30_CH3, DPPIC30, 3 => configurable);
+
+// DPPI00 groups
+impl_ppi_group!(PPI00_GROUP0, DPPIC00, 0);
+impl_ppi_group!(PPI00_GROUP1, DPPIC00, 1);
+
+// DPPI10 groups
+impl_ppi_group!(PPI10_GROUP0, DPPIC10, 0);
+
+// DPPI20 groups
+impl_ppi_group!(PPI20_GROUP0, DPPIC20, 0);
+impl_ppi_group!(PPI20_GROUP1, DPPIC20, 1);
+impl_ppi_group!(PPI20_GROUP2, DPPIC20, 2);
+impl_ppi_group!(PPI20_GROUP3, DPPIC20, 3);
+impl_ppi_group!(PPI20_GROUP4, DPPIC20, 4);
+impl_ppi_group!(PPI20_GROUP5, DPPIC20, 5);
+
+// DPPI30 groups
+impl_ppi_group!(PPI30_GROUP0, DPPIC30, 0);
+impl_ppi_group!(PPI30_GROUP1, DPPIC30, 1);
+
+impl_timer!(TIMER00, TIMER00, TIMER00);
+impl_timer!(TIMER10, TIMER10, TIMER10);
+impl_timer!(TIMER20, TIMER20, TIMER20);
+impl_timer!(TIMER21, TIMER21, TIMER21);
+impl_timer!(TIMER22, TIMER22, TIMER22);
+impl_timer!(TIMER23, TIMER23, TIMER23);
+impl_timer!(TIMER24, TIMER24, TIMER24);
+
+impl_twim!(SERIAL20, TWIM20, SERIAL20);
+impl_twim!(SERIAL21, TWIM21, SERIAL21);
+impl_twim!(SERIAL22, TWIM22, SERIAL22);
+impl_twim!(SERIAL30, TWIM30, SERIAL30);
+
+impl_twis!(SERIAL20, TWIS20, SERIAL20);
+impl_twis!(SERIAL21, TWIS21, SERIAL21);
+impl_twis!(SERIAL22, TWIS22, SERIAL22);
+impl_twis!(SERIAL30, TWIS30, SERIAL30);
+
+impl_pwm!(PWM20, PWM20, PWM20);
+impl_pwm!(PWM21, PWM21, PWM21);
+impl_pwm!(PWM22, PWM22, PWM22);
+
+#[cfg(feature = "_s")]
+impl_spim!(
+    SERIAL00,
+    SPIM00,
+    SERIAL00,
+    match pac::OSCILLATORS_S.pll().currentfreq().read().currentfreq() {
+        pac::oscillators::vals::Currentfreq::CK128M => 128_000_000,
+        pac::oscillators::vals::Currentfreq::CK64M => 64_000_000,
+        _ => unreachable!(),
+    }
+);
+#[cfg(feature = "_ns")]
+impl_spim!(
+    SERIAL00,
+    SPIM00,
+    SERIAL00,
+    match pac::OSCILLATORS_NS.pll().currentfreq().read().currentfreq() {
+        pac::oscillators::vals::Currentfreq::CK128M => 128_000_000,
+        pac::oscillators::vals::Currentfreq::CK64M => 64_000_000,
+        _ => unreachable!(),
+    }
+);
+impl_spim!(SERIAL20, SPIM20, SERIAL20, 16_000_000);
+impl_spim!(SERIAL21, SPIM21, SERIAL21, 16_000_000);
+impl_spim!(SERIAL22, SPIM22, SERIAL22, 16_000_000);
+impl_spim!(SERIAL30, SPIM30, SERIAL30, 16_000_000);
+
+impl_spis!(SERIAL20, SPIS20, SERIAL20);
+impl_spis!(SERIAL21, SPIS21, SERIAL21);
+impl_spis!(SERIAL22, SPIS22, SERIAL22);
+impl_spis!(SERIAL30, SPIS30, SERIAL30);
+
+impl_uarte!(SERIAL00, UARTE00, SERIAL00);
+impl_uarte!(SERIAL20, UARTE20, SERIAL20);
+impl_uarte!(SERIAL21, UARTE21, SERIAL21);
+impl_uarte!(SERIAL22, UARTE22, SERIAL22);
+impl_uarte!(SERIAL30, UARTE30, SERIAL30);
+
+// NB: SAADC uses "pin" abstraction, not "AIN"
+impl_saadc_input!(P1_04, 1, 4);
+impl_saadc_input!(P1_05, 1, 5);
+impl_saadc_input!(P1_06, 1, 6);
+impl_saadc_input!(P1_07, 1, 7);
+impl_saadc_input!(P1_11, 1, 11);
+impl_saadc_input!(P1_12, 1, 12);
+impl_saadc_input!(P1_13, 1, 13);
+impl_saadc_input!(P1_14, 1, 14);
+
+#[cfg(feature = "_s")]
+impl_cracen!(CRACEN, CRACEN, CRACEN);
+
+embassy_hal_internal::interrupt_mod!(
+    SWI00,
+    SWI01,
+    SWI02,
+    SWI03,
+    SPU00,
+    MPC00,
+    AAR00_CCM00,
+    ECB00,
+    CRACEN,
+    SERIAL00,
+    RRAMC,
+    VPR00,
+    CTRLAP,
+    TIMER00,
+    SPU10,
+    TIMER10,
+    EGU10,
+    RADIO_0,
+    RADIO_1,
+    SPU20,
+    SERIAL20,
+    SERIAL21,
+    SERIAL22,
+    EGU20,
+    TIMER20,
+    TIMER21,
+    TIMER22,
+    TIMER23,
+    TIMER24,
+    PDM20,
+    PDM21,
+    PWM20,
+    PWM21,
+    PWM22,
+    SAADC,
+    NFCT,
+    TEMP,
+    GPIOTE20_0,
+    GPIOTE20_1,
+    TAMPC,
+    I2S20,
+    QDEC20,
+    QDEC21,
+    GRTC_0,
+    GRTC_1,
+    GRTC_2,
+    GRTC_3,
+    SPU30,
+    SERIAL30,
+    COMP_LPCOMP,
+    WDT30,
+    WDT31,
+    GPIOTE30_0,
+    GPIOTE30_1,
+    CLOCK_POWER,
+);
diff --git a/embassy-nrf/src/chips/nrf54l10_app.rs b/embassy-nrf/src/chips/nrf54l10_app.rs
new file mode 100644
index 000000000..8e6595248
--- /dev/null
+++ b/embassy-nrf/src/chips/nrf54l10_app.rs
@@ -0,0 +1,746 @@
+/// Peripheral Access Crate
+#[allow(unused_imports)]
+#[rustfmt::skip]
+pub mod pac {
+    pub use nrf_pac::*;
+
+    #[cfg(feature = "_ns")]
+    #[doc(no_inline)]
+    pub use nrf_pac::{
+        FICR_NS as FICR,
+        DPPIC00_NS as DPPIC00,
+        PPIB00_NS as PPIB00,
+        PPIB01_NS as PPIB01,
+        AAR00_NS as AAR00,
+        CCM00_NS as CCM00,
+        ECB00_NS as ECB00,
+        SPIM00_NS as SPIM00,
+        SPIS00_NS as SPIS00,
+        UARTE00_NS as UARTE00,
+        VPR00_NS as VPR00,
+        P2_NS as P2,
+        CTRLAP_NS as CTRLAP,
+        TAD_NS as TAD,
+        TIMER00_NS as TIMER00,
+        DPPIC10_NS as DPPIC10,
+        PPIB10_NS as PPIB10,
+        PPIB11_NS as PPIB11,
+        TIMER10_NS as TIMER10,
+        EGU10_NS as EGU10,
+        RADIO_NS as RADIO,
+        DPPIC20_NS as DPPIC20,
+        PPIB20_NS as PPIB20,
+        PPIB21_NS as PPIB21,
+        PPIB22_NS as PPIB22,
+        SPIM20_NS as SPIM20,
+        SPIS20_NS as SPIS20,
+        TWIM20_NS as TWIM20,
+        TWIS20_NS as TWIS20,
+        UARTE20_NS as UARTE20,
+        SPIM21_NS as SPIM21,
+        SPIS21_NS as SPIS21,
+        TWIM21_NS as TWIM21,
+        TWIS21_NS as TWIS21,
+        UARTE21_NS as UARTE21,
+        SPIM22_NS as SPIM22,
+        SPIS22_NS as SPIS22,
+        TWIM22_NS as TWIM22,
+        TWIS22_NS as TWIS22,
+        UARTE22_NS as UARTE22,
+        EGU20_NS as EGU20,
+        TIMER20_NS as TIMER20,
+        TIMER21_NS as TIMER21,
+        TIMER22_NS as TIMER22,
+        TIMER23_NS as TIMER23,
+        TIMER24_NS as TIMER24,
+        MEMCONF_NS as MEMCONF,
+        PDM20_NS as PDM20,
+        PDM21_NS as PDM21,
+        PWM20_NS as PWM20,
+        PWM21_NS as PWM21,
+        PWM22_NS as PWM22,
+        SAADC_NS as SAADC,
+        NFCT_NS as NFCT,
+        TEMP_NS as TEMP,
+        P1_NS as P1,
+        GPIOTE20_NS as GPIOTE20,
+        I2S20_NS as I2S20,
+        QDEC20_NS as QDEC20,
+        QDEC21_NS as QDEC21,
+        GRTC_NS as GRTC,
+        DPPIC30_NS as DPPIC30,
+        PPIB30_NS as PPIB30,
+        SPIM30_NS as SPIM30,
+        SPIS30_NS as SPIS30,
+        TWIM30_NS as TWIM30,
+        TWIS30_NS as TWIS30,
+        UARTE30_NS as UARTE30,
+        COMP_NS as COMP,
+        LPCOMP_NS as LPCOMP,
+        WDT31_NS as WDT31,
+        P0_NS as P0,
+        GPIOTE30_NS as GPIOTE30,
+        CLOCK_NS as CLOCK,
+        POWER_NS as POWER,
+        RESET_NS as RESET,
+        OSCILLATORS_NS as OSCILLATORS,
+        REGULATORS_NS as REGULATORS,
+        TPIU_NS as TPIU,
+        ETM_NS as ETM,
+    };
+
+    #[cfg(feature = "_s")]
+    #[doc(no_inline)]
+    pub use nrf_pac::{
+        FICR_NS as FICR,
+        SICR_S as SICR,
+        ICACHEDATA_S as ICACHEDATA,
+        ICACHEINFO_S as ICACHEINFO,
+        SWI00_S as SWI00,
+        SWI01_S as SWI01,
+        SWI02_S as SWI02,
+        SWI03_S as SWI03,
+        SPU00_S as SPU00,
+        MPC00_S as MPC00,
+        DPPIC00_S as DPPIC00,
+        PPIB00_S as PPIB00,
+        PPIB01_S as PPIB01,
+        KMU_S as KMU,
+        AAR00_S as AAR00,
+        CCM00_S as CCM00,
+        ECB00_S as ECB00,
+        CRACEN_S as CRACEN,
+        SPIM00_S as SPIM00,
+        SPIS00_S as SPIS00,
+        UARTE00_S as UARTE00,
+        GLITCHDET_S as GLITCHDET,
+        RRAMC_S as RRAMC,
+        VPR00_S as VPR00,
+        P2_S as P2,
+        CTRLAP_S as CTRLAP,
+        TAD_S as TAD,
+        TIMER00_S as TIMER00,
+        SPU10_S as SPU10,
+        DPPIC10_S as DPPIC10,
+        PPIB10_S as PPIB10,
+        PPIB11_S as PPIB11,
+        TIMER10_S as TIMER10,
+        EGU10_S as EGU10,
+        RADIO_S as RADIO,
+        SPU20_S as SPU20,
+        DPPIC20_S as DPPIC20,
+        PPIB20_S as PPIB20,
+        PPIB21_S as PPIB21,
+        PPIB22_S as PPIB22,
+        SPIM20_S as SPIM20,
+        SPIS20_S as SPIS20,
+        TWIM20_S as TWIM20,
+        TWIS20_S as TWIS20,
+        UARTE20_S as UARTE20,
+        SPIM21_S as SPIM21,
+        SPIS21_S as SPIS21,
+        TWIM21_S as TWIM21,
+        TWIS21_S as TWIS21,
+        UARTE21_S as UARTE21,
+        SPIM22_S as SPIM22,
+        SPIS22_S as SPIS22,
+        TWIM22_S as TWIM22,
+        TWIS22_S as TWIS22,
+        UARTE22_S as UARTE22,
+        EGU20_S as EGU20,
+        TIMER20_S as TIMER20,
+        TIMER21_S as TIMER21,
+        TIMER22_S as TIMER22,
+        TIMER23_S as TIMER23,
+        TIMER24_S as TIMER24,
+        MEMCONF_S as MEMCONF,
+        PDM20_S as PDM20,
+        PDM21_S as PDM21,
+        PWM20_S as PWM20,
+        PWM21_S as PWM21,
+        PWM22_S as PWM22,
+        SAADC_S as SAADC,
+        NFCT_S as NFCT,
+        TEMP_S as TEMP,
+        P1_S as P1,
+        GPIOTE20_S as GPIOTE20,
+        TAMPC_S as TAMPC,
+        I2S20_S as I2S20,
+        QDEC20_S as QDEC20,
+        QDEC21_S as QDEC21,
+        GRTC_S as GRTC,
+        SPU30_S as SPU30,
+        DPPIC30_S as DPPIC30,
+        PPIB30_S as PPIB30,
+        SPIM30_S as SPIM30,
+        SPIS30_S as SPIS30,
+        TWIM30_S as TWIM30,
+        TWIS30_S as TWIS30,
+        UARTE30_S as UARTE30,
+        COMP_S as COMP,
+        LPCOMP_S as LPCOMP,
+        WDT30_S as WDT30,
+        WDT31_S as WDT31,
+        P0_S as P0,
+        GPIOTE30_S as GPIOTE30,
+        CLOCK_S as CLOCK,
+        POWER_S as POWER,
+        RESET_S as RESET,
+        OSCILLATORS_S as OSCILLATORS,
+        REGULATORS_S as REGULATORS,
+        CRACENCORE_S as CRACENCORE,
+        CPUC_S as CPUC,
+        ICACHE_S as ICACHE,
+    };
+}
+
+/// The maximum buffer size that the EasyDMA can send/recv in one operation.
+pub const EASY_DMA_SIZE: usize = (1 << 16) - 1;
+pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
+
+// 1.5 MB NVM
+#[allow(unused)]
+pub const FLASH_SIZE: usize = 1524 * 1024;
+
+embassy_hal_internal::peripherals! {
+    // PPI
+    PPI00_CH0,
+    PPI00_CH1,
+    PPI00_CH2,
+    PPI00_CH3,
+    PPI00_CH4,
+    PPI00_CH5,
+    PPI00_CH6,
+    PPI00_CH7,
+
+    PPI10_CH0,
+    PPI10_CH1,
+    PPI10_CH2,
+    PPI10_CH3,
+    PPI10_CH4,
+    PPI10_CH5,
+    PPI10_CH6,
+    PPI10_CH7,
+    PPI10_CH8,
+    PPI10_CH9,
+    PPI10_CH10,
+    PPI10_CH11,
+    PPI10_CH12,
+    PPI10_CH13,
+    PPI10_CH14,
+    PPI10_CH15,
+    PPI10_CH16,
+    PPI10_CH17,
+    PPI10_CH18,
+    PPI10_CH19,
+    PPI10_CH20,
+    PPI10_CH21,
+    PPI10_CH22,
+    PPI10_CH23,
+
+    PPI20_CH0,
+    PPI20_CH1,
+    PPI20_CH2,
+    PPI20_CH3,
+    PPI20_CH4,
+    PPI20_CH5,
+    PPI20_CH6,
+    PPI20_CH7,
+    PPI20_CH8,
+    PPI20_CH9,
+    PPI20_CH10,
+    PPI20_CH11,
+    PPI20_CH12,
+    PPI20_CH13,
+    PPI20_CH14,
+    PPI20_CH15,
+
+    PPI30_CH0,
+    PPI30_CH1,
+    PPI30_CH2,
+    PPI30_CH3,
+
+    PPI00_GROUP0,
+    PPI00_GROUP1,
+
+    PPI10_GROUP0,
+    PPI10_GROUP1,
+    PPI10_GROUP2,
+    PPI10_GROUP3,
+    PPI10_GROUP4,
+    PPI10_GROUP5,
+
+    PPI20_GROUP0,
+    PPI20_GROUP1,
+    PPI20_GROUP2,
+    PPI20_GROUP3,
+    PPI20_GROUP4,
+    PPI20_GROUP5,
+
+    PPI30_GROUP0,
+    PPI30_GROUP1,
+
+    // PPI BRIDGE channels
+    PPIB00_CH0,
+    PPIB00_CH1,
+    PPIB00_CH2,
+    PPIB00_CH3,
+    PPIB00_CH4,
+    PPIB00_CH5,
+    PPIB00_CH6,
+    PPIB00_CH7,
+
+    PPIB01_CH0,
+    PPIB01_CH1,
+    PPIB01_CH2,
+    PPIB01_CH3,
+    PPIB01_CH4,
+    PPIB01_CH5,
+    PPIB01_CH6,
+    PPIB01_CH7,
+
+    PPIB10_CH0,
+    PPIB10_CH1,
+    PPIB10_CH2,
+    PPIB10_CH3,
+    PPIB10_CH4,
+    PPIB10_CH5,
+    PPIB10_CH6,
+    PPIB10_CH7,
+
+    PPIB11_CH0,
+    PPIB11_CH1,
+    PPIB11_CH2,
+    PPIB11_CH3,
+    PPIB11_CH4,
+    PPIB11_CH5,
+    PPIB11_CH6,
+    PPIB11_CH7,
+    PPIB11_CH8,
+    PPIB11_CH9,
+    PPIB11_CH10,
+    PPIB11_CH11,
+    PPIB11_CH12,
+    PPIB11_CH13,
+    PPIB11_CH14,
+    PPIB11_CH15,
+
+    PPIB20_CH0,
+    PPIB20_CH1,
+    PPIB20_CH2,
+    PPIB20_CH3,
+    PPIB20_CH4,
+    PPIB20_CH5,
+    PPIB20_CH6,
+    PPIB20_CH7,
+
+    PPIB21_CH0,
+    PPIB21_CH1,
+    PPIB21_CH2,
+    PPIB21_CH3,
+    PPIB21_CH4,
+    PPIB21_CH5,
+    PPIB21_CH6,
+    PPIB21_CH7,
+    PPIB21_CH8,
+    PPIB21_CH9,
+    PPIB21_CH10,
+    PPIB21_CH11,
+    PPIB21_CH12,
+    PPIB21_CH13,
+    PPIB21_CH14,
+    PPIB21_CH15,
+
+    PPIB22_CH0,
+    PPIB22_CH1,
+    PPIB22_CH2,
+    PPIB22_CH3,
+
+    PPIB30_CH0,
+    PPIB30_CH1,
+    PPIB30_CH2,
+    PPIB30_CH3,
+
+    // Timers
+    TIMER00,
+    TIMER10,
+    TIMER20,
+    TIMER21,
+    TIMER22,
+    TIMER23,
+    TIMER24,
+
+    // GPIO port 0
+    P0_00,
+    P0_01,
+    P0_02,
+    P0_03,
+    P0_04,
+    P0_05,
+    P0_06,
+
+    // GPIO port 1
+    P1_00,
+    P1_01,
+    P1_02,
+    P1_03,
+    P1_04,
+    P1_05,
+    P1_06,
+    P1_07,
+    P1_08,
+    P1_09,
+    P1_10,
+    P1_11,
+    P1_12,
+    P1_13,
+    P1_14,
+    P1_15,
+    P1_16,
+
+
+    // GPIO port 2
+    P2_00,
+    P2_01,
+    P2_02,
+    P2_03,
+    P2_04,
+    P2_05,
+    P2_06,
+    P2_07,
+    P2_08,
+    P2_09,
+    P2_10,
+
+    // GRTC
+    GRTC_CH0,
+    #[cfg(not(feature = "time-driver-grtc"))]
+    GRTC_CH1,
+    GRTC_CH2,
+    GRTC_CH3,
+    GRTC_CH4,
+    GRTC_CH5,
+    GRTC_CH6,
+    GRTC_CH7,
+    GRTC_CH8,
+    GRTC_CH9,
+    GRTC_CH10,
+    GRTC_CH11,
+
+    // PWM
+    PWM20,
+    PWM21,
+    PWM22,
+
+    // SERIAL
+    SERIAL00,
+    SERIAL20,
+    SERIAL21,
+    SERIAL22,
+    SERIAL30,
+
+    // SAADC
+    SAADC,
+
+    // RADIO
+    RADIO,
+
+
+    // GPIOTE instances
+    GPIOTE20,
+    GPIOTE30,
+
+    // GPIOTE channels
+    GPIOTE20_CH0,
+    GPIOTE20_CH1,
+    GPIOTE20_CH2,
+    GPIOTE20_CH3,
+    GPIOTE20_CH4,
+    GPIOTE20_CH5,
+    GPIOTE20_CH6,
+    GPIOTE20_CH7,
+    GPIOTE30_CH0,
+    GPIOTE30_CH1,
+    GPIOTE30_CH2,
+    GPIOTE30_CH3,
+
+    // CRACEN
+    #[cfg(feature = "_s")]
+    CRACEN,
+
+    #[cfg(feature = "_s")]
+    // RRAMC
+    RRAMC,
+
+    // TEMP
+    TEMP,
+
+    // WDT
+    #[cfg(feature = "_ns")]
+    WDT,
+    #[cfg(feature = "_s")]
+    WDT0,
+    #[cfg(feature = "_s")]
+    WDT1,
+}
+
+impl_pin!(P0_00, 0, 0);
+impl_pin!(P0_01, 0, 1);
+impl_pin!(P0_02, 0, 2);
+impl_pin!(P0_03, 0, 3);
+impl_pin!(P0_04, 0, 4);
+impl_pin!(P0_05, 0, 5);
+impl_pin!(P0_06, 0, 6);
+
+impl_pin!(P1_00, 1, 0);
+impl_pin!(P1_01, 1, 1);
+impl_pin!(P1_02, 1, 2);
+impl_pin!(P1_03, 1, 3);
+impl_pin!(P1_04, 1, 4);
+impl_pin!(P1_05, 1, 5);
+impl_pin!(P1_06, 1, 6);
+impl_pin!(P1_07, 1, 7);
+impl_pin!(P1_08, 1, 8);
+impl_pin!(P1_09, 1, 9);
+impl_pin!(P1_10, 1, 10);
+impl_pin!(P1_11, 1, 11);
+impl_pin!(P1_12, 1, 12);
+impl_pin!(P1_13, 1, 13);
+impl_pin!(P1_14, 1, 14);
+impl_pin!(P1_15, 1, 15);
+impl_pin!(P1_16, 1, 16);
+
+impl_pin!(P2_00, 2, 0);
+impl_pin!(P2_01, 2, 1);
+impl_pin!(P2_02, 2, 2);
+impl_pin!(P2_03, 2, 3);
+impl_pin!(P2_04, 2, 4);
+impl_pin!(P2_05, 2, 5);
+impl_pin!(P2_06, 2, 6);
+impl_pin!(P2_07, 2, 7);
+impl_pin!(P2_08, 2, 8);
+impl_pin!(P2_09, 2, 9);
+impl_pin!(P2_10, 2, 10);
+
+cfg_if::cfg_if! {
+    if #[cfg(feature = "gpiote")] {
+        impl_gpiote_pin!(P0_00, GPIOTE30);
+        impl_gpiote_pin!(P0_01, GPIOTE30);
+        impl_gpiote_pin!(P0_02, GPIOTE30);
+        impl_gpiote_pin!(P0_03, GPIOTE30);
+        impl_gpiote_pin!(P0_04, GPIOTE30);
+        impl_gpiote_pin!(P0_05, GPIOTE30);
+        impl_gpiote_pin!(P0_06, GPIOTE30);
+
+        impl_gpiote_pin!(P1_00, GPIOTE20);
+        impl_gpiote_pin!(P1_01, GPIOTE20);
+        impl_gpiote_pin!(P1_02, GPIOTE20);
+        impl_gpiote_pin!(P1_03, GPIOTE20);
+        impl_gpiote_pin!(P1_04, GPIOTE20);
+        impl_gpiote_pin!(P1_05, GPIOTE20);
+        impl_gpiote_pin!(P1_06, GPIOTE20);
+        impl_gpiote_pin!(P1_07, GPIOTE20);
+        impl_gpiote_pin!(P1_08, GPIOTE20);
+        impl_gpiote_pin!(P1_09, GPIOTE20);
+        impl_gpiote_pin!(P1_10, GPIOTE20);
+        impl_gpiote_pin!(P1_11, GPIOTE20);
+        impl_gpiote_pin!(P1_12, GPIOTE20);
+        impl_gpiote_pin!(P1_13, GPIOTE20);
+        impl_gpiote_pin!(P1_14, GPIOTE20);
+        impl_gpiote_pin!(P1_15, GPIOTE20);
+        impl_gpiote_pin!(P1_16, GPIOTE20);
+    }
+}
+
+#[cfg(feature = "_ns")]
+impl_wdt!(WDT, WDT31, WDT31, 0);
+#[cfg(feature = "_s")]
+impl_wdt!(WDT0, WDT31, WDT31, 0);
+#[cfg(feature = "_s")]
+impl_wdt!(WDT1, WDT30, WDT30, 1);
+// DPPI00 channels
+impl_ppi_channel!(PPI00_CH0, DPPIC00, 0 => configurable);
+impl_ppi_channel!(PPI00_CH1, DPPIC00, 1 => configurable);
+impl_ppi_channel!(PPI00_CH2, DPPIC00, 2 => configurable);
+impl_ppi_channel!(PPI00_CH3, DPPIC00, 3 => configurable);
+impl_ppi_channel!(PPI00_CH4, DPPIC00, 4 => configurable);
+impl_ppi_channel!(PPI00_CH5, DPPIC00, 5 => configurable);
+impl_ppi_channel!(PPI00_CH6, DPPIC00, 6 => configurable);
+impl_ppi_channel!(PPI00_CH7, DPPIC00, 7 => configurable);
+
+// DPPI10 channels
+impl_ppi_channel!(PPI10_CH0, DPPIC10, 0 => static);
+
+// DPPI20 channels
+impl_ppi_channel!(PPI20_CH0, DPPIC20, 0 => configurable);
+impl_ppi_channel!(PPI20_CH1, DPPIC20, 1 => configurable);
+impl_ppi_channel!(PPI20_CH2, DPPIC20, 2 => configurable);
+impl_ppi_channel!(PPI20_CH3, DPPIC20, 3 => configurable);
+impl_ppi_channel!(PPI20_CH4, DPPIC20, 4 => configurable);
+impl_ppi_channel!(PPI20_CH5, DPPIC20, 5 => configurable);
+impl_ppi_channel!(PPI20_CH6, DPPIC20, 6 => configurable);
+impl_ppi_channel!(PPI20_CH7, DPPIC20, 7 => configurable);
+impl_ppi_channel!(PPI20_CH8, DPPIC20, 8 => configurable);
+impl_ppi_channel!(PPI20_CH9, DPPIC20, 9 => configurable);
+impl_ppi_channel!(PPI20_CH10, DPPIC20, 10 => configurable);
+impl_ppi_channel!(PPI20_CH11, DPPIC20, 11 => configurable);
+impl_ppi_channel!(PPI20_CH12, DPPIC20, 12 => configurable);
+impl_ppi_channel!(PPI20_CH13, DPPIC20, 13 => configurable);
+impl_ppi_channel!(PPI20_CH14, DPPIC20, 14 => configurable);
+impl_ppi_channel!(PPI20_CH15, DPPIC20, 15 => configurable);
+
+// DPPI30 channels
+impl_ppi_channel!(PPI30_CH0, DPPIC30, 0 => configurable);
+impl_ppi_channel!(PPI30_CH1, DPPIC30, 1 => configurable);
+impl_ppi_channel!(PPI30_CH2, DPPIC30, 2 => configurable);
+impl_ppi_channel!(PPI30_CH3, DPPIC30, 3 => configurable);
+
+// DPPI00 groups
+impl_ppi_group!(PPI00_GROUP0, DPPIC00, 0);
+impl_ppi_group!(PPI00_GROUP1, DPPIC00, 1);
+
+// DPPI10 groups
+impl_ppi_group!(PPI10_GROUP0, DPPIC10, 0);
+
+// DPPI20 groups
+impl_ppi_group!(PPI20_GROUP0, DPPIC20, 0);
+impl_ppi_group!(PPI20_GROUP1, DPPIC20, 1);
+impl_ppi_group!(PPI20_GROUP2, DPPIC20, 2);
+impl_ppi_group!(PPI20_GROUP3, DPPIC20, 3);
+impl_ppi_group!(PPI20_GROUP4, DPPIC20, 4);
+impl_ppi_group!(PPI20_GROUP5, DPPIC20, 5);
+
+// DPPI30 groups
+impl_ppi_group!(PPI30_GROUP0, DPPIC30, 0);
+impl_ppi_group!(PPI30_GROUP1, DPPIC30, 1);
+
+impl_timer!(TIMER00, TIMER00, TIMER00);
+impl_timer!(TIMER10, TIMER10, TIMER10);
+impl_timer!(TIMER20, TIMER20, TIMER20);
+impl_timer!(TIMER21, TIMER21, TIMER21);
+impl_timer!(TIMER22, TIMER22, TIMER22);
+impl_timer!(TIMER23, TIMER23, TIMER23);
+impl_timer!(TIMER24, TIMER24, TIMER24);
+
+impl_twim!(SERIAL20, TWIM20, SERIAL20);
+impl_twim!(SERIAL21, TWIM21, SERIAL21);
+impl_twim!(SERIAL22, TWIM22, SERIAL22);
+impl_twim!(SERIAL30, TWIM30, SERIAL30);
+
+impl_twis!(SERIAL20, TWIS20, SERIAL20);
+impl_twis!(SERIAL21, TWIS21, SERIAL21);
+impl_twis!(SERIAL22, TWIS22, SERIAL22);
+impl_twis!(SERIAL30, TWIS30, SERIAL30);
+
+impl_pwm!(PWM20, PWM20, PWM20);
+impl_pwm!(PWM21, PWM21, PWM21);
+impl_pwm!(PWM22, PWM22, PWM22);
+
+#[cfg(feature = "_s")]
+impl_spim!(
+    SERIAL00,
+    SPIM00,
+    SERIAL00,
+    match pac::OSCILLATORS_S.pll().currentfreq().read().currentfreq() {
+        pac::oscillators::vals::Currentfreq::CK128M => 128_000_000,
+        pac::oscillators::vals::Currentfreq::CK64M => 64_000_000,
+        _ => unreachable!(),
+    }
+);
+#[cfg(feature = "_ns")]
+impl_spim!(
+    SERIAL00,
+    SPIM00,
+    SERIAL00,
+    match pac::OSCILLATORS_NS.pll().currentfreq().read().currentfreq() {
+        pac::oscillators::vals::Currentfreq::CK128M => 128_000_000,
+        pac::oscillators::vals::Currentfreq::CK64M => 64_000_000,
+        _ => unreachable!(),
+    }
+);
+impl_spim!(SERIAL20, SPIM20, SERIAL20, 16_000_000);
+impl_spim!(SERIAL21, SPIM21, SERIAL21, 16_000_000);
+impl_spim!(SERIAL22, SPIM22, SERIAL22, 16_000_000);
+impl_spim!(SERIAL30, SPIM30, SERIAL30, 16_000_000);
+
+impl_spis!(SERIAL20, SPIS20, SERIAL20);
+impl_spis!(SERIAL21, SPIS21, SERIAL21);
+impl_spis!(SERIAL22, SPIS22, SERIAL22);
+impl_spis!(SERIAL30, SPIS30, SERIAL30);
+
+impl_uarte!(SERIAL00, UARTE00, SERIAL00);
+impl_uarte!(SERIAL20, UARTE20, SERIAL20);
+impl_uarte!(SERIAL21, UARTE21, SERIAL21);
+impl_uarte!(SERIAL22, UARTE22, SERIAL22);
+impl_uarte!(SERIAL30, UARTE30, SERIAL30);
+
+// NB: SAADC uses "pin" abstraction, not "AIN"
+impl_saadc_input!(P1_04, 1, 4);
+impl_saadc_input!(P1_05, 1, 5);
+impl_saadc_input!(P1_06, 1, 6);
+impl_saadc_input!(P1_07, 1, 7);
+impl_saadc_input!(P1_11, 1, 11);
+impl_saadc_input!(P1_12, 1, 12);
+impl_saadc_input!(P1_13, 1, 13);
+impl_saadc_input!(P1_14, 1, 14);
+
+#[cfg(feature = "_s")]
+impl_cracen!(CRACEN, CRACEN, CRACEN);
+
+embassy_hal_internal::interrupt_mod!(
+    SWI00,
+    SWI01,
+    SWI02,
+    SWI03,
+    SPU00,
+    MPC00,
+    AAR00_CCM00,
+    ECB00,
+    CRACEN,
+    SERIAL00,
+    RRAMC,
+    VPR00,
+    CTRLAP,
+    TIMER00,
+    SPU10,
+    TIMER10,
+    EGU10,
+    RADIO_0,
+    RADIO_1,
+    SPU20,
+    SERIAL20,
+    SERIAL21,
+    SERIAL22,
+    EGU20,
+    TIMER20,
+    TIMER21,
+    TIMER22,
+    TIMER23,
+    TIMER24,
+    PDM20,
+    PDM21,
+    PWM20,
+    PWM21,
+    PWM22,
+    SAADC,
+    NFCT,
+    TEMP,
+    GPIOTE20_0,
+    GPIOTE20_1,
+    TAMPC,
+    I2S20,
+    QDEC20,
+    QDEC21,
+    GRTC_0,
+    GRTC_1,
+    GRTC_2,
+    GRTC_3,
+    SPU30,
+    SERIAL30,
+    COMP_LPCOMP,
+    WDT30,
+    WDT31,
+    GPIOTE30_0,
+    GPIOTE30_1,
+    CLOCK_POWER,
+);
diff --git a/embassy-nrf/src/chips/nrf54lm20_app.rs b/embassy-nrf/src/chips/nrf54lm20_app.rs
new file mode 100644
index 000000000..c5fdf02e4
--- /dev/null
+++ b/embassy-nrf/src/chips/nrf54lm20_app.rs
@@ -0,0 +1,841 @@
+/// Peripheral Access Crate
+#[allow(unused_imports)]
+#[rustfmt::skip]
+pub mod pac {
+    pub use nrf_pac::*;
+
+    #[cfg(feature = "_ns")]
+    #[doc(no_inline)]
+    pub use nrf_pac::{
+        FICR_NS as FICR,
+        DPPIC00_NS as DPPIC00,
+        PPIB00_NS as PPIB00,
+        PPIB01_NS as PPIB01,
+        AAR00_NS as AAR00,
+        CCM00_NS as CCM00,
+        ECB00_NS as ECB00,
+        SPIM00_NS as SPIM00,
+        SPIS00_NS as SPIS00,
+        UARTE00_NS as UARTE00,
+        VPR00_NS as VPR00,
+        P2_NS as P2,
+        CTRLAP_NS as CTRLAP,
+        TAD_NS as TAD,
+        TIMER00_NS as TIMER00,
+        DPPIC10_NS as DPPIC10,
+        PPIB10_NS as PPIB10,
+        PPIB11_NS as PPIB11,
+        TIMER10_NS as TIMER10,
+        EGU10_NS as EGU10,
+        RADIO_NS as RADIO,
+        DPPIC20_NS as DPPIC20,
+        PPIB20_NS as PPIB20,
+        PPIB21_NS as PPIB21,
+        PPIB22_NS as PPIB22,
+        SPIM20_NS as SPIM20,
+        SPIS20_NS as SPIS20,
+        TWIM20_NS as TWIM20,
+        TWIS20_NS as TWIS20,
+        UARTE20_NS as UARTE20,
+        SPIM21_NS as SPIM21,
+        SPIS21_NS as SPIS21,
+        TWIM21_NS as TWIM21,
+        TWIS21_NS as TWIS21,
+        UARTE21_NS as UARTE21,
+        SPIM22_NS as SPIM22,
+        SPIS22_NS as SPIS22,
+        TWIM22_NS as TWIM22,
+        TWIS22_NS as TWIS22,
+        UARTE22_NS as UARTE22,
+        EGU20_NS as EGU20,
+        TIMER20_NS as TIMER20,
+        TIMER21_NS as TIMER21,
+        TIMER22_NS as TIMER22,
+        TIMER23_NS as TIMER23,
+        TIMER24_NS as TIMER24,
+        MEMCONF_NS as MEMCONF,
+        PDM20_NS as PDM20,
+        PDM21_NS as PDM21,
+        PWM20_NS as PWM20,
+        PWM21_NS as PWM21,
+        PWM22_NS as PWM22,
+        SAADC_NS as SAADC,
+        NFCT_NS as NFCT,
+        TEMP_NS as TEMP,
+        P1_NS as P1,
+        GPIOTE20_NS as GPIOTE20,
+        I2S20_NS as I2S20,
+        QDEC20_NS as QDEC20,
+        QDEC21_NS as QDEC21,
+        GRTC_NS as GRTC,
+        DPPIC30_NS as DPPIC30,
+        PPIB30_NS as PPIB30,
+        SPIM30_NS as SPIM30,
+        SPIS30_NS as SPIS30,
+        TWIM30_NS as TWIM30,
+        TWIS30_NS as TWIS30,
+        UARTE30_NS as UARTE30,
+        COMP_NS as COMP,
+        LPCOMP_NS as LPCOMP,
+        WDT31_NS as WDT31,
+        P0_NS as P0,
+        GPIOTE30_NS as GPIOTE30,
+        CLOCK_NS as CLOCK,
+        POWER_NS as POWER,
+        RESET_NS as RESET,
+        OSCILLATORS_NS as OSCILLATORS,
+        REGULATORS_NS as REGULATORS,
+        TPIU_NS as TPIU,
+        ETM_NS as ETM,
+    };
+
+    #[cfg(feature = "_s")]
+    #[doc(no_inline)]
+    pub use nrf_pac::{
+        FICR_NS as FICR,
+        SICR_S as SICR,
+        ICACHEDATA_S as ICACHEDATA,
+        ICACHEINFO_S as ICACHEINFO,
+        SWI00_S as SWI00,
+        SWI01_S as SWI01,
+        SWI02_S as SWI02,
+        SWI03_S as SWI03,
+        SPU00_S as SPU00,
+        MPC00_S as MPC00,
+        DPPIC00_S as DPPIC00,
+        PPIB00_S as PPIB00,
+        PPIB01_S as PPIB01,
+        KMU_S as KMU,
+        AAR00_S as AAR00,
+        CCM00_S as CCM00,
+        ECB00_S as ECB00,
+        CRACEN_S as CRACEN,
+        SPIM00_S as SPIM00,
+        SPIS00_S as SPIS00,
+        UARTE00_S as UARTE00,
+        GLITCHDET_S as GLITCHDET,
+        RRAMC_S as RRAMC,
+        VPR00_S as VPR00,
+        P2_S as P2,
+        CTRLAP_S as CTRLAP,
+        TAD_S as TAD,
+        TIMER00_S as TIMER00,
+        SPU10_S as SPU10,
+        DPPIC10_S as DPPIC10,
+        PPIB10_S as PPIB10,
+        PPIB11_S as PPIB11,
+        TIMER10_S as TIMER10,
+        EGU10_S as EGU10,
+        RADIO_S as RADIO,
+        SPU20_S as SPU20,
+        DPPIC20_S as DPPIC20,
+        PPIB20_S as PPIB20,
+        PPIB21_S as PPIB21,
+        PPIB22_S as PPIB22,
+        SPIM20_S as SPIM20,
+        SPIS20_S as SPIS20,
+        TWIM20_S as TWIM20,
+        TWIS20_S as TWIS20,
+        UARTE20_S as UARTE20,
+        SPIM21_S as SPIM21,
+        SPIS21_S as SPIS21,
+        TWIM21_S as TWIM21,
+        TWIS21_S as TWIS21,
+        UARTE21_S as UARTE21,
+        SPIM22_S as SPIM22,
+        SPIS22_S as SPIS22,
+        TWIM22_S as TWIM22,
+        TWIS22_S as TWIS22,
+        UARTE22_S as UARTE22,
+        EGU20_S as EGU20,
+        TIMER20_S as TIMER20,
+        TIMER21_S as TIMER21,
+        TIMER22_S as TIMER22,
+        TIMER23_S as TIMER23,
+        TIMER24_S as TIMER24,
+        MEMCONF_S as MEMCONF,
+        PDM20_S as PDM20,
+        PDM21_S as PDM21,
+        PWM20_S as PWM20,
+        PWM21_S as PWM21,
+        PWM22_S as PWM22,
+        SAADC_S as SAADC,
+        NFCT_S as NFCT,
+        TEMP_S as TEMP,
+        P1_S as P1,
+        GPIOTE20_S as GPIOTE20,
+        TAMPC_S as TAMPC,
+        QDEC20_S as QDEC20,
+        QDEC21_S as QDEC21,
+        GRTC_S as GRTC,
+        SPU30_S as SPU30,
+        DPPIC30_S as DPPIC30,
+        PPIB30_S as PPIB30,
+        SPIM30_S as SPIM30,
+        SPIS30_S as SPIS30,
+        TWIM30_S as TWIM30,
+        TWIS30_S as TWIS30,
+        UARTE30_S as UARTE30,
+        COMP_S as COMP,
+        LPCOMP_S as LPCOMP,
+        WDT30_S as WDT30,
+        WDT31_S as WDT31,
+        P0_S as P0,
+        GPIOTE30_S as GPIOTE30,
+        CLOCK_S as CLOCK,
+        POWER_S as POWER,
+        RESET_S as RESET,
+        OSCILLATORS_S as OSCILLATORS,
+        REGULATORS_S as REGULATORS,
+        CRACENCORE_S as CRACENCORE,
+        CPUC_S as CPUC,
+        ICACHE_S as ICACHE,
+    };
+}
+
+/// The maximum buffer size that the EasyDMA can send/recv in one operation.
+pub const EASY_DMA_SIZE: usize = (1 << 16) - 1;
+pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
+
+// 2 MB NVM
+#[allow(unused)]
+pub const FLASH_SIZE: usize = 2048 * 1024;
+
+embassy_hal_internal::peripherals! {
+    // PPI
+    PPI00_CH0,
+    PPI00_CH1,
+    PPI00_CH2,
+    PPI00_CH3,
+    PPI00_CH4,
+    PPI00_CH5,
+    PPI00_CH6,
+    PPI00_CH7,
+
+    PPI10_CH0,
+    PPI10_CH1,
+    PPI10_CH2,
+    PPI10_CH3,
+    PPI10_CH4,
+    PPI10_CH5,
+    PPI10_CH6,
+    PPI10_CH7,
+    PPI10_CH8,
+    PPI10_CH9,
+    PPI10_CH10,
+    PPI10_CH11,
+    PPI10_CH12,
+    PPI10_CH13,
+    PPI10_CH14,
+    PPI10_CH15,
+    PPI10_CH16,
+    PPI10_CH17,
+    PPI10_CH18,
+    PPI10_CH19,
+    PPI10_CH20,
+    PPI10_CH21,
+    PPI10_CH22,
+    PPI10_CH23,
+
+    PPI20_CH0,
+    PPI20_CH1,
+    PPI20_CH2,
+    PPI20_CH3,
+    PPI20_CH4,
+    PPI20_CH5,
+    PPI20_CH6,
+    PPI20_CH7,
+    PPI20_CH8,
+    PPI20_CH9,
+    PPI20_CH10,
+    PPI20_CH11,
+    PPI20_CH12,
+    PPI20_CH13,
+    PPI20_CH14,
+    PPI20_CH15,
+
+    PPI30_CH0,
+    PPI30_CH1,
+    PPI30_CH2,
+    PPI30_CH3,
+
+    PPI00_GROUP0,
+    PPI00_GROUP1,
+
+    PPI10_GROUP0,
+    PPI10_GROUP1,
+    PPI10_GROUP2,
+    PPI10_GROUP3,
+    PPI10_GROUP4,
+    PPI10_GROUP5,
+
+    PPI20_GROUP0,
+    PPI20_GROUP1,
+    PPI20_GROUP2,
+    PPI20_GROUP3,
+    PPI20_GROUP4,
+    PPI20_GROUP5,
+
+    PPI30_GROUP0,
+    PPI30_GROUP1,
+
+    // PPI BRIDGE channels
+    PPIB00_CH0,
+    PPIB00_CH1,
+    PPIB00_CH2,
+    PPIB00_CH3,
+    PPIB00_CH4,
+    PPIB00_CH5,
+    PPIB00_CH6,
+    PPIB00_CH7,
+
+    PPIB01_CH0,
+    PPIB01_CH1,
+    PPIB01_CH2,
+    PPIB01_CH3,
+    PPIB01_CH4,
+    PPIB01_CH5,
+    PPIB01_CH6,
+    PPIB01_CH7,
+
+    PPIB10_CH0,
+    PPIB10_CH1,
+    PPIB10_CH2,
+    PPIB10_CH3,
+    PPIB10_CH4,
+    PPIB10_CH5,
+    PPIB10_CH6,
+    PPIB10_CH7,
+
+    PPIB11_CH0,
+    PPIB11_CH1,
+    PPIB11_CH2,
+    PPIB11_CH3,
+    PPIB11_CH4,
+    PPIB11_CH5,
+    PPIB11_CH6,
+    PPIB11_CH7,
+    PPIB11_CH8,
+    PPIB11_CH9,
+    PPIB11_CH10,
+    PPIB11_CH11,
+    PPIB11_CH12,
+    PPIB11_CH13,
+    PPIB11_CH14,
+    PPIB11_CH15,
+
+    PPIB20_CH0,
+    PPIB20_CH1,
+    PPIB20_CH2,
+    PPIB20_CH3,
+    PPIB20_CH4,
+    PPIB20_CH5,
+    PPIB20_CH6,
+    PPIB20_CH7,
+
+    PPIB21_CH0,
+    PPIB21_CH1,
+    PPIB21_CH2,
+    PPIB21_CH3,
+    PPIB21_CH4,
+    PPIB21_CH5,
+    PPIB21_CH6,
+    PPIB21_CH7,
+    PPIB21_CH8,
+    PPIB21_CH9,
+    PPIB21_CH10,
+    PPIB21_CH11,
+    PPIB21_CH12,
+    PPIB21_CH13,
+    PPIB21_CH14,
+    PPIB21_CH15,
+
+    PPIB22_CH0,
+    PPIB22_CH1,
+    PPIB22_CH2,
+    PPIB22_CH3,
+
+    PPIB30_CH0,
+    PPIB30_CH1,
+    PPIB30_CH2,
+    PPIB30_CH3,
+
+    // Timers
+    TIMER00,
+    TIMER10,
+    TIMER20,
+    TIMER21,
+    TIMER22,
+    TIMER23,
+    TIMER24,
+
+    // GPIO port 0
+    P0_00,
+    P0_01,
+    P0_02,
+    P0_03,
+    P0_04,
+    P0_05,
+    P0_06,
+    P0_07,
+    P0_08,
+    P0_09,
+
+    // GPIO port 1
+    P1_00,
+    P1_01,
+    P1_02,
+    P1_03,
+    P1_04,
+    P1_05,
+    P1_06,
+    P1_07,
+    P1_08,
+    P1_09,
+    P1_10,
+    P1_11,
+    P1_12,
+    P1_13,
+    P1_14,
+    P1_15,
+    P1_16,
+    P1_17,
+    P1_18,
+    P1_19,
+    P1_20,
+    P1_21,
+    P1_22,
+    P1_23,
+    P1_24,
+    P1_25,
+    P1_26,
+    P1_27,
+    P1_28,
+    P1_29,
+    P1_30,
+    P1_31,
+
+
+    // GPIO port 2
+    P2_00,
+    P2_01,
+    P2_02,
+    P2_03,
+    P2_04,
+    P2_05,
+    P2_06,
+    P2_07,
+    P2_08,
+    P2_09,
+    P2_10,
+
+    // GPIO port 3
+    P3_00,
+    P3_01,
+    P3_02,
+    P3_03,
+    P3_04,
+    P3_05,
+    P3_06,
+    P3_07,
+    P3_08,
+    P3_09,
+    P3_10,
+    P3_11,
+    P3_12,
+
+    // GRTC
+    GRTC_CH0,
+    #[cfg(not(feature = "time-driver-grtc"))]
+    GRTC_CH1,
+    GRTC_CH2,
+    GRTC_CH3,
+    GRTC_CH4,
+    GRTC_CH5,
+    GRTC_CH6,
+    GRTC_CH7,
+    GRTC_CH8,
+    GRTC_CH9,
+    GRTC_CH10,
+    GRTC_CH11,
+
+    // PWM
+    PWM20,
+    PWM21,
+    PWM22,
+
+    // SERIAL
+    SERIAL00,
+    SERIAL20,
+    SERIAL21,
+    SERIAL22,
+    SERIAL30,
+
+    // SAADC
+    SAADC,
+
+    // RADIO
+    RADIO,
+
+
+    // GPIOTE instances
+    GPIOTE20,
+    GPIOTE30,
+
+    // GPIOTE channels
+    GPIOTE20_CH0,
+    GPIOTE20_CH1,
+    GPIOTE20_CH2,
+    GPIOTE20_CH3,
+    GPIOTE20_CH4,
+    GPIOTE20_CH5,
+    GPIOTE20_CH6,
+    GPIOTE20_CH7,
+    GPIOTE30_CH0,
+    GPIOTE30_CH1,
+    GPIOTE30_CH2,
+    GPIOTE30_CH3,
+
+    // CRACEN
+    #[cfg(feature = "_s")]
+    CRACEN,
+
+    #[cfg(feature = "_s")]
+    // RRAMC
+    RRAMC,
+
+    // TEMP
+    TEMP,
+
+    // WDT
+    #[cfg(feature = "_ns")]
+    WDT,
+    #[cfg(feature = "_s")]
+    WDT0,
+    #[cfg(feature = "_s")]
+    WDT1,
+}
+
+impl_pin!(P0_00, 0, 0);
+impl_pin!(P0_01, 0, 1);
+impl_pin!(P0_02, 0, 2);
+impl_pin!(P0_03, 0, 3);
+impl_pin!(P0_04, 0, 4);
+impl_pin!(P0_05, 0, 5);
+impl_pin!(P0_06, 0, 6);
+impl_pin!(P0_07, 0, 7);
+impl_pin!(P0_08, 0, 8);
+impl_pin!(P0_09, 0, 9);
+
+impl_pin!(P1_00, 1, 0);
+impl_pin!(P1_01, 1, 1);
+impl_pin!(P1_02, 1, 2);
+impl_pin!(P1_03, 1, 3);
+impl_pin!(P1_04, 1, 4);
+impl_pin!(P1_05, 1, 5);
+impl_pin!(P1_06, 1, 6);
+impl_pin!(P1_07, 1, 7);
+impl_pin!(P1_08, 1, 8);
+impl_pin!(P1_09, 1, 9);
+impl_pin!(P1_10, 1, 10);
+impl_pin!(P1_11, 1, 11);
+impl_pin!(P1_12, 1, 12);
+impl_pin!(P1_13, 1, 13);
+impl_pin!(P1_14, 1, 14);
+impl_pin!(P1_15, 1, 15);
+impl_pin!(P1_16, 1, 16);
+impl_pin!(P1_17, 1, 17);
+impl_pin!(P1_18, 1, 18);
+impl_pin!(P1_19, 1, 19);
+impl_pin!(P1_20, 1, 20);
+impl_pin!(P1_21, 1, 21);
+impl_pin!(P1_22, 1, 22);
+impl_pin!(P1_23, 1, 23);
+impl_pin!(P1_24, 1, 24);
+impl_pin!(P1_25, 1, 25);
+impl_pin!(P1_26, 1, 26);
+impl_pin!(P1_27, 1, 27);
+impl_pin!(P1_28, 1, 28);
+impl_pin!(P1_29, 1, 29);
+impl_pin!(P1_30, 1, 30);
+impl_pin!(P1_31, 1, 31);
+
+impl_pin!(P2_00, 2, 0);
+impl_pin!(P2_01, 2, 1);
+impl_pin!(P2_02, 2, 2);
+impl_pin!(P2_03, 2, 3);
+impl_pin!(P2_04, 2, 4);
+impl_pin!(P2_05, 2, 5);
+impl_pin!(P2_06, 2, 6);
+impl_pin!(P2_07, 2, 7);
+impl_pin!(P2_08, 2, 8);
+impl_pin!(P2_09, 2, 9);
+impl_pin!(P2_10, 2, 10);
+
+impl_pin!(P3_00, 3, 0);
+impl_pin!(P3_01, 3, 1);
+impl_pin!(P3_02, 3, 2);
+impl_pin!(P3_03, 3, 3);
+impl_pin!(P3_04, 3, 4);
+impl_pin!(P3_05, 3, 5);
+impl_pin!(P3_06, 3, 6);
+impl_pin!(P3_07, 3, 7);
+impl_pin!(P3_08, 3, 8);
+impl_pin!(P3_09, 3, 9);
+impl_pin!(P3_10, 3, 10);
+impl_pin!(P3_11, 3, 11);
+impl_pin!(P3_12, 3, 12);
+
+cfg_if::cfg_if! {
+    if #[cfg(feature = "gpiote")] {
+        impl_gpiote_pin!(P0_00, GPIOTE30);
+        impl_gpiote_pin!(P0_01, GPIOTE30);
+        impl_gpiote_pin!(P0_02, GPIOTE30);
+        impl_gpiote_pin!(P0_03, GPIOTE30);
+        impl_gpiote_pin!(P0_04, GPIOTE30);
+        impl_gpiote_pin!(P0_05, GPIOTE30);
+        impl_gpiote_pin!(P0_06, GPIOTE30);
+        impl_gpiote_pin!(P0_07, GPIOTE30);
+        impl_gpiote_pin!(P0_08, GPIOTE30);
+        impl_gpiote_pin!(P0_09, GPIOTE30);
+
+        impl_gpiote_pin!(P1_00, GPIOTE20);
+        impl_gpiote_pin!(P1_01, GPIOTE20);
+        impl_gpiote_pin!(P1_02, GPIOTE20);
+        impl_gpiote_pin!(P1_03, GPIOTE20);
+        impl_gpiote_pin!(P1_04, GPIOTE20);
+        impl_gpiote_pin!(P1_05, GPIOTE20);
+        impl_gpiote_pin!(P1_06, GPIOTE20);
+        impl_gpiote_pin!(P1_07, GPIOTE20);
+        impl_gpiote_pin!(P1_08, GPIOTE20);
+        impl_gpiote_pin!(P1_09, GPIOTE20);
+        impl_gpiote_pin!(P1_10, GPIOTE20);
+        impl_gpiote_pin!(P1_11, GPIOTE20);
+        impl_gpiote_pin!(P1_12, GPIOTE20);
+        impl_gpiote_pin!(P1_13, GPIOTE20);
+        impl_gpiote_pin!(P1_14, GPIOTE20);
+        impl_gpiote_pin!(P1_15, GPIOTE20);
+        impl_gpiote_pin!(P1_16, GPIOTE20);
+        impl_gpiote_pin!(P1_17, GPIOTE20);
+        impl_gpiote_pin!(P1_18, GPIOTE20);
+        impl_gpiote_pin!(P1_19, GPIOTE20);
+        impl_gpiote_pin!(P1_20, GPIOTE20);
+        impl_gpiote_pin!(P1_21, GPIOTE20);
+        impl_gpiote_pin!(P1_22, GPIOTE20);
+        impl_gpiote_pin!(P1_23, GPIOTE20);
+        impl_gpiote_pin!(P1_24, GPIOTE20);
+        impl_gpiote_pin!(P1_25, GPIOTE20);
+        impl_gpiote_pin!(P1_26, GPIOTE20);
+        impl_gpiote_pin!(P1_27, GPIOTE20);
+        impl_gpiote_pin!(P1_28, GPIOTE20);
+        impl_gpiote_pin!(P1_29, GPIOTE20);
+        impl_gpiote_pin!(P1_30, GPIOTE20);
+        impl_gpiote_pin!(P1_31, GPIOTE20);
+
+        impl_gpiote_pin!(P3_00, GPIOTE20);
+        impl_gpiote_pin!(P3_01, GPIOTE20);
+        impl_gpiote_pin!(P3_02, GPIOTE20);
+        impl_gpiote_pin!(P3_03, GPIOTE20);
+        impl_gpiote_pin!(P3_04, GPIOTE20);
+        impl_gpiote_pin!(P3_05, GPIOTE20);
+        impl_gpiote_pin!(P3_06, GPIOTE20);
+        impl_gpiote_pin!(P3_07, GPIOTE20);
+        impl_gpiote_pin!(P3_08, GPIOTE20);
+        impl_gpiote_pin!(P3_09, GPIOTE20);
+        impl_gpiote_pin!(P3_10, GPIOTE20);
+        impl_gpiote_pin!(P3_11, GPIOTE20);
+        impl_gpiote_pin!(P3_12, GPIOTE20);
+    }
+}
+
+#[cfg(feature = "_ns")]
+impl_wdt!(WDT, WDT31, WDT31, 0);
+#[cfg(feature = "_s")]
+impl_wdt!(WDT0, WDT31, WDT31, 0);
+#[cfg(feature = "_s")]
+impl_wdt!(WDT1, WDT30, WDT30, 1);
+// DPPI00 channels
+impl_ppi_channel!(PPI00_CH0, DPPIC00, 0 => configurable);
+impl_ppi_channel!(PPI00_CH1, DPPIC00, 1 => configurable);
+impl_ppi_channel!(PPI00_CH2, DPPIC00, 2 => configurable);
+impl_ppi_channel!(PPI00_CH3, DPPIC00, 3 => configurable);
+impl_ppi_channel!(PPI00_CH4, DPPIC00, 4 => configurable);
+impl_ppi_channel!(PPI00_CH5, DPPIC00, 5 => configurable);
+impl_ppi_channel!(PPI00_CH6, DPPIC00, 6 => configurable);
+impl_ppi_channel!(PPI00_CH7, DPPIC00, 7 => configurable);
+
+// DPPI10 channels
+impl_ppi_channel!(PPI10_CH0, DPPIC10, 0 => static);
+
+// DPPI20 channels
+impl_ppi_channel!(PPI20_CH0, DPPIC20, 0 => configurable);
+impl_ppi_channel!(PPI20_CH1, DPPIC20, 1 => configurable);
+impl_ppi_channel!(PPI20_CH2, DPPIC20, 2 => configurable);
+impl_ppi_channel!(PPI20_CH3, DPPIC20, 3 => configurable);
+impl_ppi_channel!(PPI20_CH4, DPPIC20, 4 => configurable);
+impl_ppi_channel!(PPI20_CH5, DPPIC20, 5 => configurable);
+impl_ppi_channel!(PPI20_CH6, DPPIC20, 6 => configurable);
+impl_ppi_channel!(PPI20_CH7, DPPIC20, 7 => configurable);
+impl_ppi_channel!(PPI20_CH8, DPPIC20, 8 => configurable);
+impl_ppi_channel!(PPI20_CH9, DPPIC20, 9 => configurable);
+impl_ppi_channel!(PPI20_CH10, DPPIC20, 10 => configurable);
+impl_ppi_channel!(PPI20_CH11, DPPIC20, 11 => configurable);
+impl_ppi_channel!(PPI20_CH12, DPPIC20, 12 => configurable);
+impl_ppi_channel!(PPI20_CH13, DPPIC20, 13 => configurable);
+impl_ppi_channel!(PPI20_CH14, DPPIC20, 14 => configurable);
+impl_ppi_channel!(PPI20_CH15, DPPIC20, 15 => configurable);
+
+// DPPI30 channels
+impl_ppi_channel!(PPI30_CH0, DPPIC30, 0 => configurable);
+impl_ppi_channel!(PPI30_CH1, DPPIC30, 1 => configurable);
+impl_ppi_channel!(PPI30_CH2, DPPIC30, 2 => configurable);
+impl_ppi_channel!(PPI30_CH3, DPPIC30, 3 => configurable);
+
+// DPPI00 groups
+impl_ppi_group!(PPI00_GROUP0, DPPIC00, 0);
+impl_ppi_group!(PPI00_GROUP1, DPPIC00, 1);
+
+// DPPI10 groups
+impl_ppi_group!(PPI10_GROUP0, DPPIC10, 0);
+
+// DPPI20 groups
+impl_ppi_group!(PPI20_GROUP0, DPPIC20, 0);
+impl_ppi_group!(PPI20_GROUP1, DPPIC20, 1);
+impl_ppi_group!(PPI20_GROUP2, DPPIC20, 2);
+impl_ppi_group!(PPI20_GROUP3, DPPIC20, 3);
+impl_ppi_group!(PPI20_GROUP4, DPPIC20, 4);
+impl_ppi_group!(PPI20_GROUP5, DPPIC20, 5);
+
+// DPPI30 groups
+impl_ppi_group!(PPI30_GROUP0, DPPIC30, 0);
+impl_ppi_group!(PPI30_GROUP1, DPPIC30, 1);
+
+impl_timer!(TIMER00, TIMER00, TIMER00);
+impl_timer!(TIMER10, TIMER10, TIMER10);
+impl_timer!(TIMER20, TIMER20, TIMER20);
+impl_timer!(TIMER21, TIMER21, TIMER21);
+impl_timer!(TIMER22, TIMER22, TIMER22);
+impl_timer!(TIMER23, TIMER23, TIMER23);
+impl_timer!(TIMER24, TIMER24, TIMER24);
+
+impl_twim!(SERIAL20, TWIM20, SERIAL20);
+impl_twim!(SERIAL21, TWIM21, SERIAL21);
+impl_twim!(SERIAL22, TWIM22, SERIAL22);
+impl_twim!(SERIAL30, TWIM30, SERIAL30);
+
+impl_twis!(SERIAL20, TWIS20, SERIAL20);
+impl_twis!(SERIAL21, TWIS21, SERIAL21);
+impl_twis!(SERIAL22, TWIS22, SERIAL22);
+impl_twis!(SERIAL30, TWIS30, SERIAL30);
+
+impl_pwm!(PWM20, PWM20, PWM20);
+impl_pwm!(PWM21, PWM21, PWM21);
+impl_pwm!(PWM22, PWM22, PWM22);
+
+#[cfg(feature = "_s")]
+impl_spim!(
+    SERIAL00,
+    SPIM00,
+    SERIAL00,
+    match pac::OSCILLATORS_S.pll().currentfreq().read().currentfreq() {
+        pac::oscillators::vals::Currentfreq::CK128M => 128_000_000,
+        pac::oscillators::vals::Currentfreq::CK64M => 64_000_000,
+        _ => unreachable!(),
+    }
+);
+#[cfg(feature = "_ns")]
+impl_spim!(
+    SERIAL00,
+    SPIM00,
+    SERIAL00,
+    match pac::OSCILLATORS_NS.pll().currentfreq().read().currentfreq() {
+        pac::oscillators::vals::Currentfreq::CK128M => 128_000_000,
+        pac::oscillators::vals::Currentfreq::CK64M => 64_000_000,
+        _ => unreachable!(),
+    }
+);
+impl_spim!(SERIAL20, SPIM20, SERIAL20, 16_000_000);
+impl_spim!(SERIAL21, SPIM21, SERIAL21, 16_000_000);
+impl_spim!(SERIAL22, SPIM22, SERIAL22, 16_000_000);
+impl_spim!(SERIAL30, SPIM30, SERIAL30, 16_000_000);
+
+impl_spis!(SERIAL20, SPIS20, SERIAL20);
+impl_spis!(SERIAL21, SPIS21, SERIAL21);
+impl_spis!(SERIAL22, SPIS22, SERIAL22);
+impl_spis!(SERIAL30, SPIS30, SERIAL30);
+
+impl_uarte!(SERIAL00, UARTE00, SERIAL00);
+impl_uarte!(SERIAL20, UARTE20, SERIAL20);
+impl_uarte!(SERIAL21, UARTE21, SERIAL21);
+impl_uarte!(SERIAL22, UARTE22, SERIAL22);
+impl_uarte!(SERIAL30, UARTE30, SERIAL30);
+
+// NB: SAADC uses "pin" abstraction, not "AIN"
+impl_saadc_input!(P1_04, 1, 4);
+impl_saadc_input!(P1_05, 1, 5);
+impl_saadc_input!(P1_06, 1, 6);
+impl_saadc_input!(P1_07, 1, 7);
+impl_saadc_input!(P1_11, 1, 11);
+impl_saadc_input!(P1_12, 1, 12);
+impl_saadc_input!(P1_13, 1, 13);
+impl_saadc_input!(P1_14, 1, 14);
+
+#[cfg(feature = "_s")]
+impl_cracen!(CRACEN, CRACEN, CRACEN);
+
+embassy_hal_internal::interrupt_mod!(
+    SWI00,
+    SWI01,
+    SWI02,
+    SWI03,
+    SPU00,
+    MPC00,
+    AAR00_CCM00,
+    ECB00,
+    CRACEN,
+    SERIAL00,
+    RRAMC,
+    VPR00,
+    CTRLAP,
+    TIMER00,
+    SPU10,
+    TIMER10,
+    EGU10,
+    RADIO_0,
+    RADIO_1,
+    SPU20,
+    SERIAL20,
+    SERIAL21,
+    SERIAL22,
+    EGU20,
+    TIMER20,
+    TIMER21,
+    TIMER22,
+    TIMER23,
+    TIMER24,
+    PDM20,
+    PDM21,
+    PWM20,
+    PWM21,
+    PWM22,
+    SAADC,
+    NFCT,
+    TEMP,
+    GPIOTE20_0,
+    GPIOTE20_1,
+    TAMPC,
+    QDEC20,
+    QDEC21,
+    GRTC_0,
+    GRTC_1,
+    GRTC_2,
+    GRTC_3,
+    SPU30,
+    SERIAL30,
+    COMP_LPCOMP,
+    WDT30,
+    WDT31,
+    GPIOTE30_0,
+    GPIOTE30_1,
+    CLOCK_POWER,
+);
diff --git a/embassy-nrf/src/cracen.rs b/embassy-nrf/src/cracen.rs
index 47ef1cd87..6381701c0 100644
--- a/embassy-nrf/src/cracen.rs
+++ b/embassy-nrf/src/cracen.rs
@@ -18,10 +18,7 @@ pub struct Cracen<'d, M: Mode> {
 impl<'d> Cracen<'d, Blocking> {
     /// Create a new CRACEN driver.
     pub fn new_blocking(_peri: Peri<'d, peripherals::CRACEN>) -> Self {
-        let me = Self { _peri, _p: PhantomData };
-
-        me.stop();
-        me
+        Self { _peri, _p: PhantomData }
     }
 }
 
@@ -48,7 +45,14 @@ impl<'d, M: Mode> Cracen<'d, M> {
         while r.rngcontrol().status().read().state() == pac::cracencore::vals::State::STARTUP {}
     }
 
-    fn stop(&self) {
+    fn stop_rng(&self) {
+        let r = Self::core();
+        r.rngcontrol().control().write(|w| {
+            w.set_enable(false);
+        });
+
+        while r.rngcontrol().status().read().state() != pac::cracencore::vals::State::RESET {}
+
         let r = Self::regs();
         r.enable().write(|w| {
             w.set_cryptomaster(false);
@@ -69,7 +73,7 @@ impl<'d, M: Mode> Cracen<'d, M> {
             chunk[..to_copy].copy_from_slice(&word[..to_copy]);
         }
 
-        self.stop();
+        self.stop_rng();
     }
 
     /// Generate a random u32
@@ -90,19 +94,7 @@ impl<'d, M: Mode> Cracen<'d, M> {
 
 impl<'d, M: Mode> Drop for Cracen<'d, M> {
     fn drop(&mut self) {
-        let r = Self::core();
-        r.rngcontrol().control().write(|w| {
-            w.set_enable(false);
-        });
-
-        while r.rngcontrol().status().read().state() != pac::cracencore::vals::State::RESET {}
-
-        let r = Self::regs();
-        r.enable().write(|w| {
-            w.set_cryptomaster(false);
-            w.set_rng(false);
-            w.set_pkeikg(false);
-        });
+        // nothing to do here, since we stop+disable rng for each operation.
     }
 }
 
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index d4f6668f3..1f6000b13 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -33,14 +33,18 @@ const CHANNELS_PER_PORT: usize = 8;
     feature = "nrf52833",
     feature = "nrf52840",
     feature = "_nrf5340",
-    feature = "_nrf54l"
+    feature = "_nrf54l15",
+    feature = "_nrf54l10",
+    feature = "_nrf54l05"
 ))]
 const PIN_COUNT: usize = 48;
+#[cfg(feature = "_nrf54lm20")]
+const PIN_COUNT: usize = 66;
 #[cfg(not(any(
     feature = "nrf52833",
     feature = "nrf52840",
     feature = "_nrf5340",
-    feature = "_nrf54l"
+    feature = "_nrf54l",
 )))]
 const PIN_COUNT: usize = 32;
 
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index e8762b00d..db71dee10 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -25,6 +25,11 @@
     feature = "nrf5340-net",
     feature = "nrf54l15-app-s",
     feature = "nrf54l15-app-ns",
+    feature = "nrf54l10-app-s",
+    feature = "nrf54l10-app-ns",
+    feature = "nrf54l05-app-s",
+    feature = "nrf54l05-app-ns",
+    feature = "nrf54lm20-app-s",
     feature = "nrf9160-s",
     feature = "nrf9160-ns",
     feature = "nrf9120-s",
@@ -49,6 +54,11 @@ compile_error!(
     nrf5340-net,
     nrf54l15-app-s,
     nrf54l15-app-ns,
+    nrf54l10-app-s,
+    nrf54l10-app-ns,
+    nrf54l05-app-s,
+    nrf54l05-app-ns,
+    nrf54lm20-app-s,
     nrf9160-s,
     nrf9160-ns,
     nrf9120-s,
@@ -99,9 +109,9 @@ pub mod ipc;
 pub mod nfct;
 #[cfg(not(feature = "_nrf54l"))]
 pub mod nvmc;
-#[cfg(feature = "nrf54l15-app-s")]
+#[cfg(all(feature = "_nrf54l", feature = "_s"))]
 pub mod rramc;
-#[cfg(feature = "nrf54l15-app-s")]
+#[cfg(all(feature = "_nrf54l", feature = "_s"))]
 pub use rramc as nvmc;
 #[cfg(not(feature = "_nrf54l"))] // TODO
 #[cfg(any(
@@ -192,6 +202,9 @@ pub mod wdt;
 #[cfg_attr(feature = "_nrf5340-app", path = "chips/nrf5340_app.rs")]
 #[cfg_attr(feature = "_nrf5340-net", path = "chips/nrf5340_net.rs")]
 #[cfg_attr(feature = "_nrf54l15-app", path = "chips/nrf54l15_app.rs")]
+#[cfg_attr(feature = "_nrf54l10-app", path = "chips/nrf54l10_app.rs")]
+#[cfg_attr(feature = "_nrf54l05-app", path = "chips/nrf54l05_app.rs")]
+#[cfg_attr(feature = "_nrf54lm20-app", path = "chips/nrf54lm20_app.rs")]
 #[cfg_attr(feature = "_nrf9160", path = "chips/nrf9160.rs")]
 #[cfg_attr(feature = "_nrf9120", path = "chips/nrf9120.rs")]
 mod chip;
@@ -657,10 +670,11 @@ mod consts {
     pub const APPROTECT_DISABLED: u32 = 0x0000_005a;
 }
 
+/// Result from writing UICR.
 #[cfg(not(any(feature = "_nrf51", feature = "_nrf54l")))]
 #[derive(Debug, Copy, Clone, Eq, PartialEq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-enum WriteResult {
+pub enum WriteResult {
     /// Word was written successfully, needs reset.
     Written,
     /// Word was already set to the value we wanted to write, nothing was done.
@@ -669,13 +683,21 @@ enum WriteResult {
     Failed,
 }
 
+/// Write the UICR value at the provided address, ensuring that flash
+/// settings are correctly apply to persist the value.
+///
+/// Safety: the address must be a valid UICR register.
 #[cfg(not(any(feature = "_nrf51", feature = "_nrf54l")))]
-unsafe fn uicr_write(address: *mut u32, value: u32) -> WriteResult {
+pub unsafe fn uicr_write(address: *mut u32, value: u32) -> WriteResult {
     uicr_write_masked(address, value, 0xFFFF_FFFF)
 }
 
 #[cfg(not(any(feature = "_nrf51", feature = "_nrf54l")))]
-unsafe fn uicr_write_masked(address: *mut u32, value: u32, mask: u32) -> WriteResult {
+/// Write the UICR value at the provided address, ensuring that flash
+/// settings are correctly apply to persist the value.
+///
+/// Safety: the address must be a valid UICR register.
+pub unsafe fn uicr_write_masked(address: *mut u32, value: u32, mask: u32) -> WriteResult {
     let curr_val = address.read_volatile();
     if curr_val & mask == value & mask {
         return WriteResult::Noop;
diff --git a/embassy-nrf/src/saadc.rs b/embassy-nrf/src/saadc.rs
index ab0e2b86a..e89338416 100644
--- a/embassy-nrf/src/saadc.rs
+++ b/embassy-nrf/src/saadc.rs
@@ -195,6 +195,7 @@ impl<'d, const N: usize> Saadc<'d, N> {
                 w.set_resp(cc.resistor.into());
                 #[cfg(not(feature = "_nrf54l"))]
                 w.set_resn(vals::Resn::BYPASS);
+                #[cfg(not(feature = "_nrf54l"))]
                 w.set_burst(!matches!(oversample, Oversample::BYPASS));
             });
         }
diff --git a/embassy-stm32-wpan/CHANGELOG.md b/embassy-stm32-wpan/CHANGELOG.md
index eb17856fc..a6089d6cf 100644
--- a/embassy-stm32-wpan/CHANGELOG.md
+++ b/embassy-stm32-wpan/CHANGELOG.md
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 <!-- next-header -->
 ## Unreleased - ReleaseDate
 
+- refactor into wb55 crate and add feature for wba
 - wpan: restructure hil and test wpan mac
 - restructure to allow embassy net driver to work.
 - First release with changelog.
diff --git a/embassy-stm32-wpan/Cargo.toml b/embassy-stm32-wpan/Cargo.toml
index 05d76f4a6..103dedead 100644
--- a/embassy-stm32-wpan/Cargo.toml
+++ b/embassy-stm32-wpan/Cargo.toml
@@ -20,10 +20,10 @@ build = [
 src_base = "https://github.com/embassy-rs/embassy/blob/embassy-stm32-wpan-v$VERSION/embassy-stm32-wpan/src/"
 src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-stm32-wpan/src/"
 target = "thumbv7em-none-eabihf"
-features = ["stm32wb55rg", "ble", "mac"]
+features = ["stm32wb55rg", "wb55_ble", "wb55_mac"]
 
 [package.metadata.docs.rs]
-features = ["stm32wb55rg", "ble", "mac"]
+features = ["stm32wb55rg", "wb55_ble", "wb55_mac"]
 
 [dependencies]
 embassy-stm32 = { version = "0.4.0", path = "../embassy-stm32" }
@@ -34,6 +34,7 @@ embassy-hal-internal = { version = "0.3.0", path = "../embassy-hal-internal" }
 embassy-embedded-hal = { version = "0.5.0", path = "../embassy-embedded-hal" }
 embassy-net-driver = { version = "0.2.0", path = "../embassy-net-driver", optional=true }
 smoltcp = { version = "0.12.0", optional=true, default-features = false }
+stm32-bindings = { version = "0.1.3", optional=true, default-features = false }
 
 defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.17", optional = true }
@@ -52,24 +53,63 @@ bitflags = { version = "2.3.3", optional = true }
 [features]
 defmt = ["dep:defmt", "embassy-sync/defmt", "embassy-embedded-hal/defmt", "embassy-hal-internal/defmt", "stm32wb-hci?/defmt"]
 
-ble = ["dep:stm32wb-hci"]
-mac = ["dep:bitflags", "dep:embassy-net-driver", "dep:smoltcp", "smoltcp/medium-ieee802154"]
+wb55 = []
+wb55_ble = ["dep:stm32wb-hci"]
+wb55_mac = ["dep:bitflags", "dep:embassy-net-driver", "dep:smoltcp", "smoltcp/medium-ieee802154"]
+
+wba = [ "dep:stm32-bindings" ]
+wba_ble = [ "stm32-bindings/wba_wpan_mac" , "stm32-bindings/wba_wpan" ]
+wba_mac = [ "stm32-bindings/wba_wpan_mac", "stm32-bindings/wba_wpan_ble" , "stm32-bindings/lib_wba5_linklayer15_4", "stm32-bindings/lib_wba_mac_lib" , "stm32-bindings/wba_wpan" ]
 
 extended = []
 
-stm32wb10cc = [ "embassy-stm32/stm32wb10cc" ]
-stm32wb15cc = [ "embassy-stm32/stm32wb15cc" ]
-stm32wb30ce = [ "embassy-stm32/stm32wb30ce" ]
-stm32wb35cc = [ "embassy-stm32/stm32wb35cc" ]
-stm32wb35ce = [ "embassy-stm32/stm32wb35ce" ]
-stm32wb50cg = [ "embassy-stm32/stm32wb50cg" ]
-stm32wb55cc = [ "embassy-stm32/stm32wb55cc" ]
-stm32wb55ce = [ "embassy-stm32/stm32wb55ce" ]
-stm32wb55cg = [ "embassy-stm32/stm32wb55cg" ]
-stm32wb55rc = [ "embassy-stm32/stm32wb55rc" ]
-stm32wb55re = [ "embassy-stm32/stm32wb55re" ]
-stm32wb55rg = [ "embassy-stm32/stm32wb55rg" ]
-stm32wb55vc = [ "embassy-stm32/stm32wb55vc" ]
-stm32wb55ve = [ "embassy-stm32/stm32wb55ve" ]
-stm32wb55vg = [ "embassy-stm32/stm32wb55vg" ]
-stm32wb55vy = [ "embassy-stm32/stm32wb55vy" ]
+stm32wb10cc = [ "embassy-stm32/stm32wb10cc" , "wb55" ]
+stm32wb15cc = [ "embassy-stm32/stm32wb15cc" , "wb55" ]
+stm32wb30ce = [ "embassy-stm32/stm32wb30ce" , "wb55" ]
+stm32wb35cc = [ "embassy-stm32/stm32wb35cc" , "wb55" ]
+stm32wb35ce = [ "embassy-stm32/stm32wb35ce" , "wb55" ]
+stm32wb50cg = [ "embassy-stm32/stm32wb50cg" , "wb55" ]
+stm32wb55cc = [ "embassy-stm32/stm32wb55cc" , "wb55" ]
+stm32wb55ce = [ "embassy-stm32/stm32wb55ce" , "wb55" ]
+stm32wb55cg = [ "embassy-stm32/stm32wb55cg" , "wb55" ]
+stm32wb55rc = [ "embassy-stm32/stm32wb55rc" , "wb55" ]
+stm32wb55re = [ "embassy-stm32/stm32wb55re" , "wb55" ]
+stm32wb55rg = [ "embassy-stm32/stm32wb55rg" , "wb55" ]
+stm32wb55vc = [ "embassy-stm32/stm32wb55vc" , "wb55" ]
+stm32wb55ve = [ "embassy-stm32/stm32wb55ve" , "wb55" ]
+stm32wb55vg = [ "embassy-stm32/stm32wb55vg" , "wb55" ]
+stm32wb55vy = [ "embassy-stm32/stm32wb55vy" , "wb55" ]
+stm32wba50ke = [ "embassy-stm32/stm32wba50ke", "wba" ]
+stm32wba50kg = [ "embassy-stm32/stm32wba50kg", "wba" ]
+stm32wba52ce = [ "embassy-stm32/stm32wba52ce", "wba" ]
+stm32wba52cg = [ "embassy-stm32/stm32wba52cg", "wba" ]
+stm32wba52ke = [ "embassy-stm32/stm32wba52ke", "wba" ]
+stm32wba52kg = [ "embassy-stm32/stm32wba52kg", "wba" ]
+stm32wba54ce = [ "embassy-stm32/stm32wba54ce", "wba" ]
+stm32wba54cg = [ "embassy-stm32/stm32wba54cg", "wba" ]
+stm32wba54ke = [ "embassy-stm32/stm32wba54ke", "wba" ]
+stm32wba54kg = [ "embassy-stm32/stm32wba54kg", "wba" ]
+stm32wba55ce = [ "embassy-stm32/stm32wba55ce", "wba" ]
+stm32wba55cg = [ "embassy-stm32/stm32wba55cg", "wba" ]
+stm32wba55he = [ "embassy-stm32/stm32wba55he", "wba" ]
+stm32wba55hg = [ "embassy-stm32/stm32wba55hg", "wba" ]
+stm32wba55ue = [ "embassy-stm32/stm32wba55ue", "wba" ]
+stm32wba55ug = [ "embassy-stm32/stm32wba55ug", "wba" ]
+stm32wba62cg = [ "embassy-stm32/stm32wba62cg", "wba" ]
+stm32wba62ci = [ "embassy-stm32/stm32wba62ci", "wba" ]
+stm32wba62mg = [ "embassy-stm32/stm32wba62mg", "wba" ]
+stm32wba62mi = [ "embassy-stm32/stm32wba62mi", "wba" ]
+stm32wba62pg = [ "embassy-stm32/stm32wba62pg", "wba" ]
+stm32wba62pi = [ "embassy-stm32/stm32wba62pi", "wba" ]
+stm32wba63cg = [ "embassy-stm32/stm32wba63cg", "wba" ]
+stm32wba63ci = [ "embassy-stm32/stm32wba63ci", "wba" ]
+stm32wba64cg = [ "embassy-stm32/stm32wba64cg", "wba" ]
+stm32wba64ci = [ "embassy-stm32/stm32wba64ci", "wba" ]
+stm32wba65cg = [ "embassy-stm32/stm32wba65cg", "wba" ]
+stm32wba65ci = [ "embassy-stm32/stm32wba65ci", "wba" ]
+stm32wba65mg = [ "embassy-stm32/stm32wba65mg", "wba" ]
+stm32wba65mi = [ "embassy-stm32/stm32wba65mi", "wba" ]
+stm32wba65pg = [ "embassy-stm32/stm32wba65pg", "wba" ]
+stm32wba65pi = [ "embassy-stm32/stm32wba65pi", "wba" ]
+stm32wba65rg = [ "embassy-stm32/stm32wba65rg", "wba" ]
+stm32wba65ri = [ "embassy-stm32/stm32wba65ri", "wba" ]
diff --git a/embassy-stm32-wpan/src/lib.rs b/embassy-stm32-wpan/src/lib.rs
index 18b0feada..3fabe112a 100644
--- a/embassy-stm32-wpan/src/lib.rs
+++ b/embassy-stm32-wpan/src/lib.rs
@@ -18,201 +18,14 @@
 // #![warn(missing_docs)]
 #![allow(static_mut_refs)] // TODO: Fix
 
-// This must go FIRST so that all the other modules see its macros.
-mod fmt;
+#[cfg(feature = "wb55")]
+mod wb55;
 
-use core::mem::MaybeUninit;
-use core::sync::atomic::{Ordering, compiler_fence};
+#[cfg(feature = "wb55")]
+pub use wb55::*;
 
-use embassy_hal_internal::Peri;
-use embassy_stm32::interrupt;
-use embassy_stm32::ipcc::{Config, Ipcc, IpccRxChannel, ReceiveInterruptHandler, TransmitInterruptHandler};
-use embassy_stm32::peripherals::IPCC;
-use sub::mm::MemoryManager;
-use sub::sys::Sys;
-use tables::*;
-use unsafe_linked_list::LinkedListNode;
+#[cfg(feature = "wba")]
+mod wba;
 
-pub mod channels;
-pub mod cmd;
-pub mod consts;
-pub mod evt;
-pub mod lhci;
-pub mod shci;
-pub mod sub;
-pub mod tables;
-pub mod unsafe_linked_list;
-
-#[cfg(feature = "mac")]
-pub mod mac;
-
-#[cfg(feature = "ble")]
-pub use crate::sub::ble::hci;
-
-type PacketHeader = LinkedListNode;
-
-/// Transport Layer for the Mailbox interface
-pub struct TlMbox<'d> {
-    pub sys_subsystem: Sys<'d>,
-    pub mm_subsystem: MemoryManager<'d>,
-    #[cfg(feature = "ble")]
-    pub ble_subsystem: sub::ble::Ble<'d>,
-    #[cfg(feature = "mac")]
-    pub mac_subsystem: sub::mac::Mac<'d>,
-    pub traces: IpccRxChannel<'d>,
-}
-
-impl<'d> TlMbox<'d> {
-    /// Initialise the Transport Layer, and creates and returns a wrapper around it.
-    ///
-    /// This method performs the initialisation laid out in AN5289 annex 14.1. However, it differs
-    /// from the implementation documented in Figure 64, to avoid needing to reference any C
-    /// function pointers.
-    ///
-    /// Annex 14.1 lays out the following methods that should be called:
-    ///     1. tl_mbox.c/TL_Init, which initialises the reference table that is shared between CPU1
-    ///        and CPU2.
-    ///     2. shci_tl.c/shci_init(), which initialises the system transport layer, and in turn
-    ///        calls tl_mbox.c/TL_SYS_Init, which initialises SYSTEM_EVT_QUEUE channel.
-    ///     3. tl_mbox.c/TL_MM_Init(), which initialises the channel used for sending memory
-    ///        manager commands.
-    ///     4. tl_mbox.c/TL_Enable(), which enables the IPCC, and starts CPU2.
-    /// This implementation initialises all of the shared refernce tables and all IPCC channel that
-    /// would be initialised by this process. The developer should therefore treat this method as
-    /// completing all steps in Figure 64.
-    ///
-    /// Once this method has been called, no system commands may be sent until the CPU2 ready
-    /// signal is received, via [sys_subsystem.read]; this completes the procedure laid out in
-    /// Figure 65.
-    ///
-    /// If the `ble` feature is enabled, at this point, the user should call
-    /// [sys_subsystem.shci_c2_ble_init], before any commands are written to the
-    /// [TlMbox.ble_subsystem] ([sub::ble::Ble::new()] completes the process that would otherwise
-    /// be handled by `TL_BLE_Init`; see Figure 66). This completes the procedure laid out in
-    /// Figure 66.
-    // TODO: document what the user should do after calling init to use the mac_802_15_4 subsystem
-    pub async fn init(
-        ipcc: Peri<'d, IPCC>,
-        _irqs: impl interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_RX, ReceiveInterruptHandler>
-        + interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_TX, TransmitInterruptHandler>,
-        config: Config,
-    ) -> Self {
-        // this is an inlined version of TL_Init from the STM32WB firmware as requested by AN5289.
-        // HW_IPCC_Init is not called, and its purpose is (presumably?) covered by this
-        // implementation
-        unsafe {
-            TL_REF_TABLE.as_mut_ptr().write_volatile(RefTable {
-                device_info_table: TL_DEVICE_INFO_TABLE.as_ptr(),
-                ble_table: TL_BLE_TABLE.as_ptr(),
-                thread_table: TL_THREAD_TABLE.as_ptr(),
-                sys_table: TL_SYS_TABLE.as_ptr(),
-                mem_manager_table: TL_MEM_MANAGER_TABLE.as_ptr(),
-                traces_table: TL_TRACES_TABLE.as_ptr(),
-                mac_802_15_4_table: TL_MAC_802_15_4_TABLE.as_ptr(),
-                zigbee_table: TL_ZIGBEE_TABLE.as_ptr(),
-                lld_tests_table: TL_LLD_TESTS_TABLE.as_ptr(),
-                ble_lld_table: TL_BLE_LLD_TABLE.as_ptr(),
-            });
-
-            TL_SYS_TABLE
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-            TL_DEVICE_INFO_TABLE
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-            TL_BLE_TABLE
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-            TL_THREAD_TABLE
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-            TL_MEM_MANAGER_TABLE
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-
-            TL_TRACES_TABLE
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-            TL_MAC_802_15_4_TABLE
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-            TL_ZIGBEE_TABLE
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-            TL_LLD_TESTS_TABLE
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-            TL_BLE_LLD_TABLE
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-
-            EVT_POOL
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-            SYS_SPARE_EVT_BUF
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-            CS_BUFFER
-                .as_mut_ptr()
-                .write_volatile(MaybeUninit::zeroed().assume_init());
-
-            #[cfg(feature = "ble")]
-            {
-                BLE_SPARE_EVT_BUF
-                    .as_mut_ptr()
-                    .write_volatile(MaybeUninit::zeroed().assume_init());
-
-                BLE_CMD_BUFFER
-                    .as_mut_ptr()
-                    .write_volatile(MaybeUninit::zeroed().assume_init());
-                HCI_ACL_DATA_BUFFER
-                    .as_mut_ptr()
-                    .write_volatile(MaybeUninit::zeroed().assume_init());
-            }
-
-            #[cfg(feature = "mac")]
-            {
-                MAC_802_15_4_CMD_BUFFER
-                    .as_mut_ptr()
-                    .write_volatile(MaybeUninit::zeroed().assume_init());
-                MAC_802_15_4_NOTIF_RSP_EVT_BUFFER
-                    .as_mut_ptr()
-                    .write_volatile(MaybeUninit::zeroed().assume_init());
-            }
-        }
-
-        compiler_fence(Ordering::SeqCst);
-
-        // this is equivalent to `HW_IPCC_Enable`, which is called by `TL_Enable`
-        let [
-            (_hw_ipcc_ble_cmd_channel, _ipcc_ble_event_channel),
-            (ipcc_system_cmd_rsp_channel, ipcc_system_event_channel),
-            (_ipcc_mac_802_15_4_cmd_rsp_channel, _ipcc_mac_802_15_4_notification_ack_channel),
-            (ipcc_mm_release_buffer_channel, _ipcc_traces_channel),
-            (_ipcc_ble_lld_cmd_channel, _ipcc_ble_lld_rsp_channel),
-            (_ipcc_hci_acl_data_channel, _),
-        ] = Ipcc::new(ipcc, _irqs, config).split();
-
-        let mm = sub::mm::MemoryManager::new(ipcc_mm_release_buffer_channel);
-        let mut sys = sub::sys::Sys::new(ipcc_system_cmd_rsp_channel, ipcc_system_event_channel);
-
-        debug!("sys event: {}", sys.read().await.payload());
-
-        Self {
-            sys_subsystem: sys,
-            #[cfg(feature = "ble")]
-            ble_subsystem: sub::ble::Ble::new(
-                _hw_ipcc_ble_cmd_channel,
-                _ipcc_ble_event_channel,
-                _ipcc_hci_acl_data_channel,
-            ),
-            #[cfg(feature = "mac")]
-            mac_subsystem: sub::mac::Mac::new(
-                _ipcc_mac_802_15_4_cmd_rsp_channel,
-                _ipcc_mac_802_15_4_notification_ack_channel,
-            ),
-            mm_subsystem: mm,
-            traces: _ipcc_traces_channel,
-        }
-    }
-}
+#[cfg(feature = "wba")]
+pub use wba::*;
diff --git a/embassy-stm32-wpan/src/sub/mod.rs b/embassy-stm32-wpan/src/sub/mod.rs
deleted file mode 100644
index bee3dbdf1..000000000
--- a/embassy-stm32-wpan/src/sub/mod.rs
+++ /dev/null
@@ -1,6 +0,0 @@
-#[cfg(feature = "ble")]
-pub mod ble;
-#[cfg(feature = "mac")]
-pub mod mac;
-pub mod mm;
-pub mod sys;
diff --git a/embassy-stm32-wpan/src/channels.rs b/embassy-stm32-wpan/src/wb55/channels.rs
index 58f857136..58f857136 100644
--- a/embassy-stm32-wpan/src/channels.rs
+++ b/embassy-stm32-wpan/src/wb55/channels.rs
diff --git a/embassy-stm32-wpan/src/cmd.rs b/embassy-stm32-wpan/src/wb55/cmd.rs
index 787c22c4b..34f02d6e7 100644
--- a/embassy-stm32-wpan/src/cmd.rs
+++ b/embassy-stm32-wpan/src/wb55/cmd.rs
@@ -1,8 +1,8 @@
 use core::ptr;
 use core::sync::atomic::{Ordering, compiler_fence};
 
-use crate::PacketHeader;
 use crate::consts::TlPacketType;
+use crate::wb55::PacketHeader;
 
 #[derive(Copy, Clone)]
 #[repr(C, packed)]
diff --git a/embassy-stm32-wpan/src/consts.rs b/embassy-stm32-wpan/src/wb55/consts.rs
index 7ecb22974..659e74e69 100644
--- a/embassy-stm32-wpan/src/consts.rs
+++ b/embassy-stm32-wpan/src/wb55/consts.rs
@@ -1,5 +1,5 @@
-use crate::PacketHeader;
 use crate::evt::CsEvt;
+use crate::wb55::PacketHeader;
 
 #[derive(Debug)]
 #[repr(C)]
diff --git a/embassy-stm32-wpan/src/evt.rs b/embassy-stm32-wpan/src/wb55/evt.rs
index f32821269..f32821269 100644
--- a/embassy-stm32-wpan/src/evt.rs
+++ b/embassy-stm32-wpan/src/wb55/evt.rs
diff --git a/embassy-stm32-wpan/src/fmt.rs b/embassy-stm32-wpan/src/wb55/fmt.rs
index 8ca61bc39..8ca61bc39 100644
--- a/embassy-stm32-wpan/src/fmt.rs
+++ b/embassy-stm32-wpan/src/wb55/fmt.rs
diff --git a/embassy-stm32-wpan/src/lhci.rs b/embassy-stm32-wpan/src/wb55/lhci.rs
index 59c8bfb5d..59c8bfb5d 100644
--- a/embassy-stm32-wpan/src/lhci.rs
+++ b/embassy-stm32-wpan/src/wb55/lhci.rs
diff --git a/embassy-stm32-wpan/src/mac/commands.rs b/embassy-stm32-wpan/src/wb55/mac/commands.rs
index d96f0094a..d96f0094a 100644
--- a/embassy-stm32-wpan/src/mac/commands.rs
+++ b/embassy-stm32-wpan/src/wb55/mac/commands.rs
diff --git a/embassy-stm32-wpan/src/mac/consts.rs b/embassy-stm32-wpan/src/wb55/mac/consts.rs
index 56903d980..56903d980 100644
--- a/embassy-stm32-wpan/src/mac/consts.rs
+++ b/embassy-stm32-wpan/src/wb55/mac/consts.rs
diff --git a/embassy-stm32-wpan/src/mac/control.rs b/embassy-stm32-wpan/src/wb55/mac/control.rs
index 14c6fdd2b..14c6fdd2b 100644
--- a/embassy-stm32-wpan/src/mac/control.rs
+++ b/embassy-stm32-wpan/src/wb55/mac/control.rs
diff --git a/embassy-stm32-wpan/src/mac/driver.rs b/embassy-stm32-wpan/src/wb55/mac/driver.rs
index 41171ce3d..41171ce3d 100644
--- a/embassy-stm32-wpan/src/mac/driver.rs
+++ b/embassy-stm32-wpan/src/wb55/mac/driver.rs
diff --git a/embassy-stm32-wpan/src/mac/event.rs b/embassy-stm32-wpan/src/wb55/mac/event.rs
index 39856e185..39856e185 100644
--- a/embassy-stm32-wpan/src/mac/event.rs
+++ b/embassy-stm32-wpan/src/wb55/mac/event.rs
diff --git a/embassy-stm32-wpan/src/mac/indications.rs b/embassy-stm32-wpan/src/wb55/mac/indications.rs
index 5673514c9..5673514c9 100644
--- a/embassy-stm32-wpan/src/mac/indications.rs
+++ b/embassy-stm32-wpan/src/wb55/mac/indications.rs
diff --git a/embassy-stm32-wpan/src/mac/macros.rs b/embassy-stm32-wpan/src/wb55/mac/macros.rs
index 1a988a779..1a988a779 100644
--- a/embassy-stm32-wpan/src/mac/macros.rs
+++ b/embassy-stm32-wpan/src/wb55/mac/macros.rs
diff --git a/embassy-stm32-wpan/src/mac/mod.rs b/embassy-stm32-wpan/src/wb55/mac/mod.rs
index ac50a6b29..ac50a6b29 100644
--- a/embassy-stm32-wpan/src/mac/mod.rs
+++ b/embassy-stm32-wpan/src/wb55/mac/mod.rs
diff --git a/embassy-stm32-wpan/src/mac/opcodes.rs b/embassy-stm32-wpan/src/wb55/mac/opcodes.rs
index fd7011873..fd7011873 100644
--- a/embassy-stm32-wpan/src/mac/opcodes.rs
+++ b/embassy-stm32-wpan/src/wb55/mac/opcodes.rs
diff --git a/embassy-stm32-wpan/src/mac/responses.rs b/embassy-stm32-wpan/src/wb55/mac/responses.rs
index 544fdaae8..544fdaae8 100644
--- a/embassy-stm32-wpan/src/mac/responses.rs
+++ b/embassy-stm32-wpan/src/wb55/mac/responses.rs
diff --git a/embassy-stm32-wpan/src/mac/runner.rs b/embassy-stm32-wpan/src/wb55/mac/runner.rs
index 3b7d895df..3b7d895df 100644
--- a/embassy-stm32-wpan/src/mac/runner.rs
+++ b/embassy-stm32-wpan/src/wb55/mac/runner.rs
diff --git a/embassy-stm32-wpan/src/mac/typedefs.rs b/embassy-stm32-wpan/src/wb55/mac/typedefs.rs
index 175d4a37d..175d4a37d 100644
--- a/embassy-stm32-wpan/src/mac/typedefs.rs
+++ b/embassy-stm32-wpan/src/wb55/mac/typedefs.rs
diff --git a/embassy-stm32-wpan/src/wb55/mod.rs b/embassy-stm32-wpan/src/wb55/mod.rs
new file mode 100644
index 000000000..95cfe09f1
--- /dev/null
+++ b/embassy-stm32-wpan/src/wb55/mod.rs
@@ -0,0 +1,198 @@
+// This must go FIRST so that all the other modules see its macros.
+mod fmt;
+
+use core::mem::MaybeUninit;
+use core::sync::atomic::{Ordering, compiler_fence};
+
+use embassy_hal_internal::Peri;
+use embassy_stm32::interrupt;
+use embassy_stm32::ipcc::{Config, Ipcc, IpccRxChannel, ReceiveInterruptHandler, TransmitInterruptHandler};
+use embassy_stm32::peripherals::IPCC;
+use sub::mm::MemoryManager;
+use sub::sys::Sys;
+use tables::*;
+use unsafe_linked_list::LinkedListNode;
+
+pub mod channels;
+pub mod cmd;
+pub mod consts;
+pub mod evt;
+pub mod lhci;
+pub mod shci;
+pub mod sub;
+pub mod tables;
+pub mod unsafe_linked_list;
+
+#[cfg(feature = "wb55_mac")]
+pub mod mac;
+
+#[cfg(feature = "wb55_ble")]
+pub use crate::sub::ble::hci;
+
+type PacketHeader = LinkedListNode;
+
+/// Transport Layer for the Mailbox interface
+pub struct TlMbox<'d> {
+    pub sys_subsystem: Sys<'d>,
+    pub mm_subsystem: MemoryManager<'d>,
+    #[cfg(feature = "wb55_ble")]
+    pub ble_subsystem: sub::ble::Ble<'d>,
+    #[cfg(feature = "wb55_mac")]
+    pub mac_subsystem: sub::mac::Mac<'d>,
+    pub traces: IpccRxChannel<'d>,
+}
+
+impl<'d> TlMbox<'d> {
+    /// Initialise the Transport Layer, and creates and returns a wrapper around it.
+    ///
+    /// This method performs the initialisation laid out in AN5289 annex 14.1. However, it differs
+    /// from the implementation documented in Figure 64, to avoid needing to reference any C
+    /// function pointers.
+    ///
+    /// Annex 14.1 lays out the following methods that should be called:
+    ///     1. tl_mbox.c/TL_Init, which initialises the reference table that is shared between CPU1
+    ///        and CPU2.
+    ///     2. shci_tl.c/shci_init(), which initialises the system transport layer, and in turn
+    ///        calls tl_mbox.c/TL_SYS_Init, which initialises SYSTEM_EVT_QUEUE channel.
+    ///     3. tl_mbox.c/TL_MM_Init(), which initialises the channel used for sending memory
+    ///        manager commands.
+    ///     4. tl_mbox.c/TL_Enable(), which enables the IPCC, and starts CPU2.
+    /// This implementation initialises all of the shared refernce tables and all IPCC channel that
+    /// would be initialised by this process. The developer should therefore treat this method as
+    /// completing all steps in Figure 64.
+    ///
+    /// Once this method has been called, no system commands may be sent until the CPU2 ready
+    /// signal is received, via [sys_subsystem.read]; this completes the procedure laid out in
+    /// Figure 65.
+    ///
+    /// If the `ble` feature is enabled, at this point, the user should call
+    /// [sys_subsystem.shci_c2_ble_init], before any commands are written to the
+    /// [TlMbox.ble_subsystem] ([sub::ble::Ble::new()] completes the process that would otherwise
+    /// be handled by `TL_BLE_Init`; see Figure 66). This completes the procedure laid out in
+    /// Figure 66.
+    // TODO: document what the user should do after calling init to use the mac_802_15_4 subsystem
+    pub async fn init(
+        ipcc: Peri<'d, IPCC>,
+        _irqs: impl interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_RX, ReceiveInterruptHandler>
+        + interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_TX, TransmitInterruptHandler>,
+        config: Config,
+    ) -> Self {
+        // this is an inlined version of TL_Init from the STM32WB firmware as requested by AN5289.
+        // HW_IPCC_Init is not called, and its purpose is (presumably?) covered by this
+        // implementation
+        unsafe {
+            TL_REF_TABLE.as_mut_ptr().write_volatile(RefTable {
+                device_info_table: TL_DEVICE_INFO_TABLE.as_ptr(),
+                ble_table: TL_BLE_TABLE.as_ptr(),
+                thread_table: TL_THREAD_TABLE.as_ptr(),
+                sys_table: TL_SYS_TABLE.as_ptr(),
+                mem_manager_table: TL_MEM_MANAGER_TABLE.as_ptr(),
+                traces_table: TL_TRACES_TABLE.as_ptr(),
+                mac_802_15_4_table: TL_MAC_802_15_4_TABLE.as_ptr(),
+                zigbee_table: TL_ZIGBEE_TABLE.as_ptr(),
+                lld_tests_table: TL_LLD_TESTS_TABLE.as_ptr(),
+                ble_lld_table: TL_BLE_LLD_TABLE.as_ptr(),
+            });
+
+            TL_SYS_TABLE
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+            TL_DEVICE_INFO_TABLE
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+            TL_BLE_TABLE
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+            TL_THREAD_TABLE
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+            TL_MEM_MANAGER_TABLE
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+
+            TL_TRACES_TABLE
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+            TL_MAC_802_15_4_TABLE
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+            TL_ZIGBEE_TABLE
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+            TL_LLD_TESTS_TABLE
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+            TL_BLE_LLD_TABLE
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+
+            EVT_POOL
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+            SYS_SPARE_EVT_BUF
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+            CS_BUFFER
+                .as_mut_ptr()
+                .write_volatile(MaybeUninit::zeroed().assume_init());
+
+            #[cfg(feature = "wb55_ble")]
+            {
+                BLE_SPARE_EVT_BUF
+                    .as_mut_ptr()
+                    .write_volatile(MaybeUninit::zeroed().assume_init());
+
+                BLE_CMD_BUFFER
+                    .as_mut_ptr()
+                    .write_volatile(MaybeUninit::zeroed().assume_init());
+                HCI_ACL_DATA_BUFFER
+                    .as_mut_ptr()
+                    .write_volatile(MaybeUninit::zeroed().assume_init());
+            }
+
+            #[cfg(feature = "wb55_mac")]
+            {
+                MAC_802_15_4_CMD_BUFFER
+                    .as_mut_ptr()
+                    .write_volatile(MaybeUninit::zeroed().assume_init());
+                MAC_802_15_4_NOTIF_RSP_EVT_BUFFER
+                    .as_mut_ptr()
+                    .write_volatile(MaybeUninit::zeroed().assume_init());
+            }
+        }
+
+        compiler_fence(Ordering::SeqCst);
+
+        // this is equivalent to `HW_IPCC_Enable`, which is called by `TL_Enable`
+        let [
+            (_hw_ipcc_ble_cmd_channel, _ipcc_ble_event_channel),
+            (ipcc_system_cmd_rsp_channel, ipcc_system_event_channel),
+            (_ipcc_mac_802_15_4_cmd_rsp_channel, _ipcc_mac_802_15_4_notification_ack_channel),
+            (ipcc_mm_release_buffer_channel, _ipcc_traces_channel),
+            (_ipcc_ble_lld_cmd_channel, _ipcc_ble_lld_rsp_channel),
+            (_ipcc_hci_acl_data_channel, _),
+        ] = Ipcc::new(ipcc, _irqs, config).split();
+
+        let mm = sub::mm::MemoryManager::new(ipcc_mm_release_buffer_channel);
+        let mut sys = sub::sys::Sys::new(ipcc_system_cmd_rsp_channel, ipcc_system_event_channel);
+
+        debug!("sys event: {}", sys.read().await.payload());
+
+        Self {
+            sys_subsystem: sys,
+            #[cfg(feature = "wb55_ble")]
+            ble_subsystem: sub::ble::Ble::new(
+                _hw_ipcc_ble_cmd_channel,
+                _ipcc_ble_event_channel,
+                _ipcc_hci_acl_data_channel,
+            ),
+            #[cfg(feature = "wb55_mac")]
+            mac_subsystem: sub::mac::Mac::new(
+                _ipcc_mac_802_15_4_cmd_rsp_channel,
+                _ipcc_mac_802_15_4_notification_ack_channel,
+            ),
+            mm_subsystem: mm,
+            traces: _ipcc_traces_channel,
+        }
+    }
+}
diff --git a/embassy-stm32-wpan/src/shci.rs b/embassy-stm32-wpan/src/wb55/shci.rs
index 2d94a9cda..3faa79209 100644
--- a/embassy-stm32-wpan/src/shci.rs
+++ b/embassy-stm32-wpan/src/wb55/shci.rs
@@ -1,10 +1,10 @@
 use core::sync::atomic::{Ordering, compiler_fence};
 use core::{mem, ptr, slice};
 
-use crate::PacketHeader;
 use crate::cmd::CmdPacket;
 use crate::consts::{TL_CS_EVT_SIZE, TL_EVT_HEADER_SIZE, TL_PACKET_HEADER_SIZE};
 use crate::evt::{CcEvt, EvtStub};
+use crate::wb55::PacketHeader;
 
 const SHCI_OGF: u16 = 0x3F;
 
diff --git a/embassy-stm32-wpan/src/sub/ble.rs b/embassy-stm32-wpan/src/wb55/sub/ble.rs
index afc4a510a..afc4a510a 100644
--- a/embassy-stm32-wpan/src/sub/ble.rs
+++ b/embassy-stm32-wpan/src/wb55/sub/ble.rs
diff --git a/embassy-stm32-wpan/src/sub/mac.rs b/embassy-stm32-wpan/src/wb55/sub/mac.rs
index ce2903e61..ce2903e61 100644
--- a/embassy-stm32-wpan/src/sub/mac.rs
+++ b/embassy-stm32-wpan/src/wb55/sub/mac.rs
diff --git a/embassy-stm32-wpan/src/sub/mm.rs b/embassy-stm32-wpan/src/wb55/sub/mm.rs
index aac252929..cbb5f130b 100644
--- a/embassy-stm32-wpan/src/sub/mm.rs
+++ b/embassy-stm32-wpan/src/wb55/sub/mm.rs
@@ -11,7 +11,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 use crate::consts::POOL_SIZE;
 use crate::evt;
 use crate::evt::EvtPacket;
-#[cfg(feature = "ble")]
+#[cfg(feature = "wb55_ble")]
 use crate::tables::BLE_SPARE_EVT_BUF;
 use crate::tables::{EVT_POOL, FREE_BUF_QUEUE, MemManagerTable, SYS_SPARE_EVT_BUF, TL_MEM_MANAGER_TABLE};
 use crate::unsafe_linked_list::LinkedListNode;
@@ -30,9 +30,9 @@ impl<'a> MemoryManager<'a> {
             LinkedListNode::init_head(LOCAL_FREE_BUF_QUEUE.as_mut_ptr());
 
             TL_MEM_MANAGER_TABLE.as_mut_ptr().write_volatile(MemManagerTable {
-                #[cfg(feature = "ble")]
+                #[cfg(feature = "wb55_ble")]
                 spare_ble_buffer: BLE_SPARE_EVT_BUF.as_ptr().cast(),
-                #[cfg(not(feature = "ble"))]
+                #[cfg(not(feature = "wb55_ble"))]
                 spare_ble_buffer: core::ptr::null(),
                 spare_sys_buffer: SYS_SPARE_EVT_BUF.as_ptr().cast(),
                 blepool: EVT_POOL.as_ptr().cast(),
diff --git a/embassy-stm32-wpan/src/wb55/sub/mod.rs b/embassy-stm32-wpan/src/wb55/sub/mod.rs
new file mode 100644
index 000000000..d3ebd822a
--- /dev/null
+++ b/embassy-stm32-wpan/src/wb55/sub/mod.rs
@@ -0,0 +1,6 @@
+#[cfg(feature = "wb55_ble")]
+pub mod ble;
+#[cfg(feature = "wb55_mac")]
+pub mod mac;
+pub mod mm;
+pub mod sys;
diff --git a/embassy-stm32-wpan/src/sub/sys.rs b/embassy-stm32-wpan/src/wb55/sub/sys.rs
index 3ee539bb9..4376314c7 100644
--- a/embassy-stm32-wpan/src/sub/sys.rs
+++ b/embassy-stm32-wpan/src/wb55/sub/sys.rs
@@ -3,13 +3,13 @@ use embassy_stm32::ipcc::{IpccRxChannel, IpccTxChannel};
 use crate::cmd::CmdPacket;
 use crate::consts::TlPacketType;
 use crate::evt::EvtBox;
-#[cfg(feature = "ble")]
+#[cfg(feature = "wb55_ble")]
 use crate::shci::ShciBleInitCmdParam;
 use crate::shci::{SchiCommandStatus, ShciOpcode};
 use crate::sub::mm;
 use crate::tables::{SysTable, WirelessFwInfoTable};
 use crate::unsafe_linked_list::LinkedListNode;
-use crate::{SYS_CMD_BUF, SYSTEM_EVT_QUEUE, TL_DEVICE_INFO_TABLE, TL_SYS_TABLE};
+use crate::wb55::{SYS_CMD_BUF, SYSTEM_EVT_QUEUE, TL_DEVICE_INFO_TABLE, TL_SYS_TABLE};
 
 /// A guard that, once constructed, allows for sys commands to be sent to CPU2.
 pub struct Sys<'a> {
@@ -66,7 +66,7 @@ impl<'a> Sys<'a> {
         unsafe { SchiCommandStatus::from_packet(SYS_CMD_BUF.as_ptr()) }
     }
 
-    #[cfg(feature = "mac")]
+    #[cfg(feature = "wb55_mac")]
     pub async fn shci_c2_mac_802_15_4_init(&mut self) -> Result<SchiCommandStatus, ()> {
         self.write_and_get_response(ShciOpcode::Mac802_15_4Init, &[]).await
     }
@@ -77,7 +77,7 @@ impl<'a> Sys<'a> {
     /// AN5289, Figures 65 and 66). It should only be called after CPU2 sends a system event, via
     /// `HW_IPCC_SYS_EvtNot`, aka `IoBusCallBackUserEvt` (as detailed in Figure 65), aka
     /// [crate::sub::ble::hci::host::uart::UartHci::read].
-    #[cfg(feature = "ble")]
+    #[cfg(feature = "wb55_ble")]
     pub async fn shci_c2_ble_init(&mut self, param: ShciBleInitCmdParam) -> Result<SchiCommandStatus, ()> {
         self.write_and_get_response(ShciOpcode::BleInit, param.payload()).await
     }
diff --git a/embassy-stm32-wpan/src/tables.rs b/embassy-stm32-wpan/src/wb55/tables.rs
index 20d2c190f..2e6a9199b 100644
--- a/embassy-stm32-wpan/src/tables.rs
+++ b/embassy-stm32-wpan/src/wb55/tables.rs
@@ -4,7 +4,7 @@ use aligned::{A4, Aligned};
 use bit_field::BitField;
 
 use crate::cmd::{AclDataPacket, CmdPacket};
-#[cfg(feature = "mac")]
+#[cfg(feature = "wb55_mac")]
 use crate::consts::C_SIZE_CMD_STRING;
 use crate::consts::{POOL_SIZE, TL_CS_EVT_SIZE, TL_EVT_HEADER_SIZE, TL_PACKET_HEADER_SIZE};
 use crate::unsafe_linked_list::LinkedListNode;
@@ -242,11 +242,11 @@ pub static mut EVT_QUEUE: Aligned<A4, MaybeUninit<LinkedListNode>> = Aligned(May
 pub static mut SYSTEM_EVT_QUEUE: Aligned<A4, MaybeUninit<LinkedListNode>> = Aligned(MaybeUninit::zeroed());
 
 // --------------------- app tables ---------------------
-#[cfg(feature = "mac")]
+#[cfg(feature = "wb55_mac")]
 #[unsafe(link_section = "MB_MEM2")]
 pub static mut MAC_802_15_4_CMD_BUFFER: Aligned<A4, MaybeUninit<CmdPacket>> = Aligned(MaybeUninit::zeroed());
 
-#[cfg(feature = "mac")]
+#[cfg(feature = "wb55_mac")]
 #[unsafe(link_section = "MB_MEM2")]
 pub static mut MAC_802_15_4_NOTIF_RSP_EVT_BUFFER: MaybeUninit<
     Aligned<A4, [u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + 255]>,
@@ -262,21 +262,21 @@ pub static mut SYS_CMD_BUF: Aligned<A4, MaybeUninit<CmdPacket>> = Aligned(MaybeU
 pub static mut SYS_SPARE_EVT_BUF: Aligned<A4, MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + 255]>> =
     Aligned(MaybeUninit::zeroed());
 
-#[cfg(feature = "mac")]
+#[cfg(feature = "wb55_mac")]
 #[unsafe(link_section = "MB_MEM2")]
 pub static mut MAC_802_15_4_CNFINDNOT: Aligned<A4, MaybeUninit<[u8; C_SIZE_CMD_STRING]>> =
     Aligned(MaybeUninit::zeroed());
 
-#[cfg(feature = "ble")]
+#[cfg(feature = "wb55_ble")]
 #[unsafe(link_section = "MB_MEM1")]
 pub static mut BLE_CMD_BUFFER: Aligned<A4, MaybeUninit<CmdPacket>> = Aligned(MaybeUninit::zeroed());
 
-#[cfg(feature = "ble")]
+#[cfg(feature = "wb55_ble")]
 #[unsafe(link_section = "MB_MEM2")]
 pub static mut BLE_SPARE_EVT_BUF: Aligned<A4, MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + 255]>> =
     Aligned(MaybeUninit::zeroed());
 
-#[cfg(feature = "ble")]
+#[cfg(feature = "wb55_ble")]
 #[unsafe(link_section = "MB_MEM2")]
 //                                                 fuck these "magic" numbers from ST ---v---v
 pub static mut HCI_ACL_DATA_BUFFER: Aligned<A4, MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + 5 + 251]>> =
diff --git a/embassy-stm32-wpan/src/unsafe_linked_list.rs b/embassy-stm32-wpan/src/wb55/unsafe_linked_list.rs
index d8bc29763..d8bc29763 100644
--- a/embassy-stm32-wpan/src/unsafe_linked_list.rs
+++ b/embassy-stm32-wpan/src/wb55/unsafe_linked_list.rs
diff --git a/embassy-stm32-wpan/src/wba/bindings.rs b/embassy-stm32-wpan/src/wba/bindings.rs
new file mode 100644
index 000000000..d2030cfb8
--- /dev/null
+++ b/embassy-stm32-wpan/src/wba/bindings.rs
@@ -0,0 +1 @@
+pub use stm32_bindings::bindings::{mac, wba_ble_stack as ble, wba_link_layer as link_layer};
diff --git a/embassy-stm32-wpan/src/wba/linklayer_plat.rs b/embassy-stm32-wpan/src/wba/linklayer_plat.rs
new file mode 100644
index 000000000..c011b3bcb
--- /dev/null
+++ b/embassy-stm32-wpan/src/wba/linklayer_plat.rs
@@ -0,0 +1,645 @@
+#[allow(dead_code)]
+fn test_fn() {}
+
+// /* USER CODE BEGIN Header */
+// /**
+//   ******************************************************************************
+//   * @file    linklayer_plat.c
+//   * @author  MCD Application Team
+//   * @brief   Source file for the linklayer plateform adaptation layer
+//   ******************************************************************************
+//   * @attention
+//   *
+//   * Copyright (c) 2024 STMicroelectronics.
+//   * All rights reserved.
+//   *
+//   * This software is licensed under terms that can be found in the LICENSE file
+//   * in the root directory of this software component.
+//   * If no LICENSE file comes with this software, it is provided AS-IS.
+//   *
+//   ******************************************************************************
+//   */
+// /* USER CODE END Header */
+//
+// #include "stm32wbaxx_hal.h"
+// #include "stm32wbaxx_hal_conf.h"
+// #include "stm32wbaxx_ll_rcc.h"
+//
+// #include "app_common.h"
+// #include "app_conf.h"
+// #include "linklayer_plat.h"
+// #include "scm.h"
+// #include "log_module.h"
+// #if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1)
+// #include "adc_ctrl.h"
+// #endif /* (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) */
+//
+// #if (CFG_LPM_LEVEL != 0)
+// #include "stm32_lpm.h"
+// #include "stm32_lpm_if.h"
+// #endif /* (CFG_LPM_LEVEL != 0) */
+//
+// /* USER CODE BEGIN Includes */
+//
+// /* USER CODE END Includes */
+//
+// #define max(a,b) ((a) > (b) ? a : b)
+//
+// /* 2.4GHz RADIO ISR callbacks */
+// void (*radio_callback)(void) = NULL;
+// void (*low_isr_callback)(void) = NULL;
+//
+// /* RNG handle */
+// extern RNG_HandleTypeDef hrng;
+//
+// #if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1)
+// /* Link Layer temperature request from background */
+// extern void ll_sys_bg_temperature_measurement(void);
+// #endif /* (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) */
+//
+// /* Radio critical sections */
+// static uint32_t primask_bit = 0;
+// volatile int32_t prio_high_isr_counter = 0;
+// volatile int32_t prio_low_isr_counter = 0;
+// volatile int32_t prio_sys_isr_counter = 0;
+// volatile int32_t irq_counter = 0;
+// volatile uint32_t local_basepri_value = 0;
+//
+// /* Radio SW low ISR global variable */
+// volatile uint8_t radio_sw_low_isr_is_running_high_prio = 0;
+//
+// /* Radio bus clock control variables */
+// uint8_t AHB5_SwitchedOff = 0;
+// uint32_t radio_sleep_timer_val = 0;
+//
+// /**
+//   * @brief  Configure the necessary clock sources for the radio.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_ClockInit()
+// {
+//   uint32_t linklayer_slp_clk_src = LL_RCC_RADIOSLEEPSOURCE_NONE;
+//
+//   /* Get the Link Layer sleep timer clock source */
+//   linklayer_slp_clk_src = LL_RCC_RADIO_GetSleepTimerClockSource();
+//   if(linklayer_slp_clk_src == LL_RCC_RADIOSLEEPSOURCE_NONE)
+//   {
+//     /* If there is no clock source defined, should be selected before */
+//     assert_param(0);
+//   }
+//
+//   /* Enable AHB5ENR peripheral clock (bus CLK) */
+//   __HAL_RCC_RADIO_CLK_ENABLE();
+// }
+//
+// /**
+//   * @brief  Link Layer active waiting loop.
+//   * @param  delay: delay in us
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_DelayUs(uint32_t delay)
+// {
+//   static uint8_t lock = 0;
+//   uint32_t t0;
+//   uint32_t primask_bit;
+//
+//   /* Enter critical section */
+//   primask_bit= __get_PRIMASK();
+//   __disable_irq();
+//
+//   if (lock == 0U)
+//   {
+//     /* Initialize counter */
+//     /* Reset cycle counter to prevent overflow
+//        As a us counter, it is assumed than even with re-entrancy,
+//        overflow will never happen before re-initializing this counter */
+//     DWT->CYCCNT = 0U;
+//     /* Enable DWT by safety but should be useless (as already set) */
+//     SET_BIT(DCB->DEMCR, DCB_DEMCR_TRCENA_Msk);
+//     /* Enable counter */
+//     SET_BIT(DWT->CTRL, DWT_CTRL_CYCCNTENA_Msk);
+//   }
+//   /* Increment 're-entrance' counter */
+//   lock++;
+//   /* Get starting time stamp */
+//   t0 = DWT->CYCCNT;
+//   /* Exit critical section */
+//  __set_PRIMASK(primask_bit);
+//
+//   /* Turn us into cycles */
+//   delay = delay * (SystemCoreClock / 1000000U);
+//   delay += t0;
+//
+//   /* Busy waiting loop */
+//   while (DWT->CYCCNT < delay)
+//   {
+//   };
+//
+//   /* Enter critical section */
+//   primask_bit= __get_PRIMASK();
+//   __disable_irq();
+//   if (lock == 1U)
+//   {
+//     /* Disable counter */
+//     CLEAR_BIT(DWT->CTRL, DWT_CTRL_CYCCNTENA_Msk);
+//   }
+//   /* Decrement 're-entrance' counter */
+//   lock--;
+//   /* Exit critical section */
+//  __set_PRIMASK(primask_bit);
+//
+// }
+//
+// /**
+//   * @brief  Link Layer assertion API
+//   * @param  condition: conditional statement to be checked.
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_Assert(uint8_t condition)
+// {
+//   assert_param(condition);
+// }
+//
+// /**
+//   * @brief  Enable/disable the Link Layer active clock (baseband clock).
+//   * @param  enable: boolean value to enable (1) or disable (0) the clock.
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_WaitHclkRdy(void)
+// {
+//   /* Wait on radio bus clock readiness if it has been turned of */
+//   if (AHB5_SwitchedOff == 1)
+//   {
+//     AHB5_SwitchedOff = 0;
+//     while (radio_sleep_timer_val == ll_intf_cmn_get_slptmr_value());
+//   }
+// }
+//
+// /**
+//   * @brief  Notify the Link Layer platform layer the system will enter in WFI
+//   *         and AHB5 clock may be turned of regarding the 2.4Ghz radio state.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_NotifyWFIEnter(void)
+// {
+//   /* Check if Radio state will allow the AHB5 clock to be cut */
+//
+//   /* AHB5 clock will be cut in the following cases:
+//    * - 2.4GHz radio is not in ACTIVE mode (in SLEEP or DEEPSLEEP mode).
+//    * - RADIOSMEN and STRADIOCLKON bits are at 0.
+//    */
+//   if((LL_PWR_GetRadioMode() != LL_PWR_RADIO_ACTIVE_MODE) ||
+//      ((__HAL_RCC_RADIO_IS_CLK_SLEEP_ENABLED() == 0) && (LL_RCC_RADIO_IsEnabledSleepTimerClock() == 0)))
+//   {
+//     AHB5_SwitchedOff = 1;
+//   }
+// }
+//
+// /**
+//   * @brief  Notify the Link Layer platform layer the system exited WFI and AHB5
+//   *         clock may be resynchronized as is may have been turned of during
+//   *         low power mode entry.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_NotifyWFIExit(void)
+// {
+//   /* Check if AHB5 clock has been turned of and needs resynchronisation */
+//   if (AHB5_SwitchedOff)
+//   {
+//     /* Read sleep register as earlier as possible */
+//     radio_sleep_timer_val = ll_intf_cmn_get_slptmr_value();
+//   }
+// }
+//
+// /**
+//   * @brief  Active wait on bus clock readiness.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_AclkCtrl(uint8_t enable)
+// {
+//   if(enable != 0u)
+//   {
+// #if (CFG_SCM_SUPPORTED == 1)
+//     /* SCM HSE BEGIN */
+//     /* Polling on HSE32 activation */
+//     SCM_HSE_WaitUntilReady();
+//     /* Enable RADIO baseband clock (active CLK) */
+//     HAL_RCCEx_EnableRadioBBClock();
+//     /* SCM HSE END */
+// #else
+//     /* Enable RADIO baseband clock (active CLK) */
+//     HAL_RCCEx_EnableRadioBBClock();
+//     /* Polling on HSE32 activation */
+//     while ( LL_RCC_HSE_IsReady() == 0);
+// #endif /* CFG_SCM_SUPPORTED */
+//   }
+//   else
+//   {
+//     /* Disable RADIO baseband clock (active CLK) */
+//     HAL_RCCEx_DisableRadioBBClock();
+//   }
+// }
+//
+// /**
+//   * @brief  Link Layer RNG request.
+//   * @param  ptr_rnd: pointer to the variable that hosts the number.
+//   * @param  len: number of byte of anthropy to get.
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_GetRNG(uint8_t *ptr_rnd, uint32_t len)
+// {
+//   uint32_t nb_remaining_rng = len;
+//   uint32_t generated_rng;
+//
+//   /* Get the requested RNGs (4 bytes by 4bytes) */
+//   while(nb_remaining_rng >= 4)
+//   {
+//     generated_rng = 0;
+//     HW_RNG_Get(1, &generated_rng);
+//     memcpy((ptr_rnd+(len-nb_remaining_rng)), &generated_rng, 4);
+//     nb_remaining_rng -=4;
+//   }
+//
+//   /* Get the remaining number of RNGs */
+//   if(nb_remaining_rng>0){
+//     generated_rng = 0;
+//     HW_RNG_Get(1, &generated_rng);
+//     memcpy((ptr_rnd+(len-nb_remaining_rng)), &generated_rng, nb_remaining_rng);
+//   }
+// }
+//
+// /**
+//   * @brief  Initialize Link Layer radio high priority interrupt.
+//   * @param  intr_cb: function pointer to assign for the radio high priority ISR routine.
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_SetupRadioIT(void (*intr_cb)())
+// {
+//   radio_callback = intr_cb;
+//   HAL_NVIC_SetPriority((IRQn_Type) RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH, 0);
+//   HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_INTR_NUM);
+// }
+//
+// /**
+//   * @brief  Initialize Link Layer SW low priority interrupt.
+//   * @param  intr_cb: function pointer to assign for the SW low priority ISR routine.
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_SetupSwLowIT(void (*intr_cb)())
+// {
+//   low_isr_callback = intr_cb;
+//
+//   HAL_NVIC_SetPriority((IRQn_Type) RADIO_SW_LOW_INTR_NUM, RADIO_SW_LOW_INTR_PRIO, 0);
+//   HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_SW_LOW_INTR_NUM);
+// }
+//
+// /**
+//   * @brief  Trigger the link layer SW low interrupt.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_TriggerSwLowIT(uint8_t priority)
+// {
+//   uint8_t low_isr_priority = RADIO_INTR_PRIO_LOW;
+//
+//   /* Check if a SW low interrupt as already been raised.
+//    * Nested call far radio low isr are not supported
+//    **/
+//
+//   if(NVIC_GetActive(RADIO_SW_LOW_INTR_NUM) == 0)
+//   {
+//     /* No nested SW low ISR, default behavior */
+//
+//     if(priority == 0)
+//     {
+//       low_isr_priority = RADIO_SW_LOW_INTR_PRIO;
+//     }
+//
+//     HAL_NVIC_SetPriority((IRQn_Type) RADIO_SW_LOW_INTR_NUM, low_isr_priority, 0);
+//   }
+//   else
+//   {
+//     /* Nested call detected */
+//     /* No change for SW radio low interrupt priority for the moment */
+//
+//     if(priority != 0)
+//     {
+//       /* At the end of current SW radio low ISR, this pending SW low interrupt
+//        * will run with RADIO_INTR_PRIO_LOW priority
+//        **/
+//       radio_sw_low_isr_is_running_high_prio = 1;
+//     }
+//   }
+//
+//   HAL_NVIC_SetPendingIRQ((IRQn_Type) RADIO_SW_LOW_INTR_NUM);
+// }
+//
+// /**
+//   * @brief  Enable interrupts.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_EnableIRQ(void)
+// {
+//   irq_counter = max(0,irq_counter-1);
+//
+//   if(irq_counter == 0)
+//   {
+//     /* When irq_counter reaches 0, restore primask bit */
+//     __set_PRIMASK(primask_bit);
+//   }
+// }
+//
+// /**
+//   * @brief  Disable interrupts.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_DisableIRQ(void)
+// {
+//   if(irq_counter == 0)
+//   {
+//     /* Save primask bit at first interrupt disablement */
+//     primask_bit= __get_PRIMASK();
+//   }
+//   __disable_irq();
+//   irq_counter ++;
+// }
+//
+// /**
+//   * @brief  Enable specific interrupt group.
+//   * @param  isr_type: mask for interrupt group to enable.
+//   *         This parameter can be one of the following:
+//   *         @arg LL_HIGH_ISR_ONLY: enable link layer high priority ISR.
+//   *         @arg LL_LOW_ISR_ONLY: enable link layer SW low priority ISR.
+//   *         @arg SYS_LOW_ISR: mask interrupts for all the other system ISR with
+//   *              lower priority that link layer SW low interrupt.
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_EnableSpecificIRQ(uint8_t isr_type)
+// {
+//   if( (isr_type & LL_HIGH_ISR_ONLY) != 0 )
+//   {
+//     prio_high_isr_counter--;
+//     if(prio_high_isr_counter == 0)
+//     {
+//       /* When specific counter for link layer high ISR reaches 0, interrupt is enabled */
+//       HAL_NVIC_EnableIRQ(RADIO_INTR_NUM);
+//       /* USER CODE BEGIN LINKLAYER_PLAT_EnableSpecificIRQ_1 */
+//
+//       /* USER CODE END LINKLAYER_PLAT_EnableSpecificIRQ_1 */
+//     }
+//   }
+//
+//   if( (isr_type & LL_LOW_ISR_ONLY) != 0 )
+//   {
+//     prio_low_isr_counter--;
+//     if(prio_low_isr_counter == 0)
+//     {
+//       /* When specific counter for link layer SW low ISR reaches 0, interrupt is enabled */
+//       HAL_NVIC_EnableIRQ(RADIO_SW_LOW_INTR_NUM);
+//     }
+//
+//   }
+//
+//   if( (isr_type & SYS_LOW_ISR) != 0 )
+//   {
+//     prio_sys_isr_counter--;
+//     if(prio_sys_isr_counter == 0)
+//     {
+//       /* Restore basepri value */
+//       __set_BASEPRI(local_basepri_value);
+//     }
+//   }
+// }
+//
+// /**
+//   * @brief  Disable specific interrupt group.
+//   * @param  isr_type: mask for interrupt group to disable.
+//   *         This parameter can be one of the following:
+//   *         @arg LL_HIGH_ISR_ONLY: disable link layer high priority ISR.
+//   *         @arg LL_LOW_ISR_ONLY: disable link layer SW low priority ISR.
+//   *         @arg SYS_LOW_ISR: unmask interrupts for all the other system ISR with
+//   *              lower priority that link layer SW low interrupt.
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_DisableSpecificIRQ(uint8_t isr_type)
+// {
+//   if( (isr_type & LL_HIGH_ISR_ONLY) != 0 )
+//   {
+//     prio_high_isr_counter++;
+//     if(prio_high_isr_counter == 1)
+//     {
+//       /* USER CODE BEGIN LINKLAYER_PLAT_DisableSpecificIRQ_1 */
+//
+//       /* USER CODE END LINKLAYER_PLAT_DisableSpecificIRQ_1 */
+//       /* When specific counter for link layer high ISR value is 1, interrupt is disabled */
+//       HAL_NVIC_DisableIRQ(RADIO_INTR_NUM);
+//     }
+//   }
+//
+//   if( (isr_type & LL_LOW_ISR_ONLY) != 0 )
+//   {
+//     prio_low_isr_counter++;
+//     if(prio_low_isr_counter == 1)
+//     {
+//       /* When specific counter for link layer SW low ISR value is 1, interrupt is disabled */
+//       HAL_NVIC_DisableIRQ(RADIO_SW_LOW_INTR_NUM);
+//     }
+//   }
+//
+//   if( (isr_type & SYS_LOW_ISR) != 0 )
+//   {
+//     prio_sys_isr_counter++;
+//     if(prio_sys_isr_counter == 1)
+//     {
+//       /* Save basepri register value */
+//       local_basepri_value = __get_BASEPRI();
+//
+//       /* Mask all other interrupts with lower priority that link layer SW low ISR */
+//       __set_BASEPRI_MAX(RADIO_INTR_PRIO_LOW<<4);
+//     }
+//   }
+// }
+//
+// /**
+//   * @brief  Enable link layer high priority ISR only.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_EnableRadioIT(void)
+// {
+//   /* USER CODE BEGIN LINKLAYER_PLAT_EnableRadioIT_1 */
+//
+//   /* USER CODE END LINKLAYER_PLAT_EnableRadioIT_1 */
+//
+//   HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_INTR_NUM);
+//
+//   /* USER CODE BEGIN LINKLAYER_PLAT_EnableRadioIT_2 */
+//
+//   /* USER CODE END LINKLAYER_PLAT_EnableRadioIT_2 */
+// }
+//
+// /**
+//   * @brief  Disable link layer high priority ISR only.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_DisableRadioIT(void)
+// {
+//   /* USER CODE BEGIN LINKLAYER_PLAT_DisableRadioIT_1 */
+//
+//   /* USER CODE END LINKLAYER_PLAT_DisableRadioIT_1 */
+//
+//   HAL_NVIC_DisableIRQ((IRQn_Type) RADIO_INTR_NUM);
+//
+//   /* USER CODE BEGIN LINKLAYER_PLAT_DisableRadioIT_2 */
+//
+//   /* USER CODE END LINKLAYER_PLAT_DisableRadioIT_2 */
+// }
+//
+// /**
+//   * @brief  Link Layer notification for radio activity start.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_StartRadioEvt(void)
+// {
+//   __HAL_RCC_RADIO_CLK_SLEEP_ENABLE();
+//   NVIC_SetPriority(RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH);
+// #if (CFG_SCM_SUPPORTED == 1)
+//   scm_notifyradiostate(SCM_RADIO_ACTIVE);
+// #endif /* CFG_SCM_SUPPORTED */
+// }
+//
+// /**
+//   * @brief  Link Layer notification for radio activity end.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_StopRadioEvt(void)
+// {
+//   __HAL_RCC_RADIO_CLK_SLEEP_DISABLE();
+//   NVIC_SetPriority(RADIO_INTR_NUM, RADIO_INTR_PRIO_LOW);
+// #if (CFG_SCM_SUPPORTED == 1)
+//   scm_notifyradiostate(SCM_RADIO_NOT_ACTIVE);
+// #endif /* CFG_SCM_SUPPORTED */
+// }
+//
+// /**
+//   * @brief  Link Layer notification for RCO calibration start.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_RCOStartClbr(void)
+// {
+// #if (CFG_LPM_LEVEL != 0)
+//   PWR_DisableSleepMode();
+//   /* Disabling stop mode prevents also from entering in standby */
+//   UTIL_LPM_SetStopMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_DISABLE);
+// #endif /* (CFG_LPM_LEVEL != 0) */
+// #if (CFG_SCM_SUPPORTED == 1)
+//   scm_setsystemclock(SCM_USER_LL_HW_RCO_CLBR, HSE_32MHZ);
+//   while (LL_PWR_IsActiveFlag_VOS() == 0);
+// #endif /* (CFG_SCM_SUPPORTED == 1) */
+// }
+//
+// /**
+//   * @brief  Link Layer notification for RCO calibration end.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_RCOStopClbr(void)
+// {
+// #if (CFG_LPM_LEVEL != 0)
+//   PWR_EnableSleepMode();
+//   UTIL_LPM_SetStopMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_ENABLE);
+// #endif /* (CFG_LPM_LEVEL != 0) */
+// #if (CFG_SCM_SUPPORTED == 1)
+//   scm_setsystemclock(SCM_USER_LL_HW_RCO_CLBR, HSE_16MHZ);
+// #endif /* (CFG_SCM_SUPPORTED == 1) */
+// }
+//
+// /**
+//   * @brief  Link Layer requests temperature.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_RequestTemperature(void)
+// {
+// #if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1)
+//   ll_sys_bg_temperature_measurement();
+// #endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */
+// }
+//
+// /**
+//   * @brief  PHY Start calibration.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_PhyStartClbr(void)
+// {
+//   /* USER CODE BEGIN LINKLAYER_PLAT_PhyStartClbr_0 */
+//
+//   /* USER CODE END LINKLAYER_PLAT_PhyStartClbr_0 */
+//
+//   /* USER CODE BEGIN LINKLAYER_PLAT_PhyStartClbr_1 */
+//
+//   /* USER CODE END LINKLAYER_PLAT_PhyStartClbr_1 */
+// }
+//
+// /**
+//   * @brief  PHY Stop calibration.
+//   * @param  None
+//   * @retval None
+//   */
+// void LINKLAYER_PLAT_PhyStopClbr(void)
+// {
+//   /* USER CODE BEGIN LINKLAYER_PLAT_PhyStopClbr_0 */
+//
+//   /* USER CODE END LINKLAYER_PLAT_PhyStopClbr_0 */
+//
+//   /* USER CODE BEGIN LINKLAYER_PLAT_PhyStopClbr_1 */
+//
+//   /* USER CODE END LINKLAYER_PLAT_PhyStopClbr_1 */
+// }
+//
+// /**
+//  * @brief Notify the upper layer that new Link Layer timings have been applied.
+//  * @param evnt_timing[in]: Evnt_timing_t pointer to structure contains drift time , execution time and scheduling time
+//  * @retval None.
+//  */
+// void LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT(Evnt_timing_t * p_evnt_timing)
+// {
+//   /* USER CODE BEGIN LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT_0 */
+//
+//   /* USER CODE END LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT_0 */
+// }
+//
+// /**
+//   * @brief  Get the ST company ID.
+//   * @param  None
+//   * @retval Company ID
+//   */
+// uint32_t LINKLAYER_PLAT_GetSTCompanyID(void)
+// {
+//   return LL_FLASH_GetSTCompanyID();
+// }
+//
+// /**
+//   * @brief  Get the Unique Device Number (UDN).
+//   * @param  None
+//   * @retval UDN
+//   */
+// uint32_t LINKLAYER_PLAT_GetUDN(void)
+// {
+//   return LL_FLASH_GetUDN();
+// }
+//
+// /* USER CODE BEGIN LINKLAYER_PLAT 0 */
+//
+// /* USER CODE END LINKLAYER_PLAT 0 */
diff --git a/embassy-stm32-wpan/src/wba/ll_sys/ll_sys_cs.rs b/embassy-stm32-wpan/src/wba/ll_sys/ll_sys_cs.rs
new file mode 100644
index 000000000..30103ba27
--- /dev/null
+++ b/embassy-stm32-wpan/src/wba/ll_sys/ll_sys_cs.rs
@@ -0,0 +1,77 @@
+use crate::bindings::link_layer::{
+    LINKLAYER_PLAT_DisableIRQ, LINKLAYER_PLAT_DisableSpecificIRQ, LINKLAYER_PLAT_EnableIRQ,
+    LINKLAYER_PLAT_EnableSpecificIRQ, LINKLAYER_PLAT_PhyStartClbr, LINKLAYER_PLAT_PhyStopClbr,
+};
+
+// /**
+//   ******************************************************************************
+//   * @file    ll_sys_cs.c
+//   * @author  MCD Application Team
+//   * @brief   Link Layer IP system interface critical sections management
+//   ******************************************************************************
+//   * @attention
+//   *
+//   * Copyright (c) 2022 STMicroelectronics.
+//   * All rights reserved.
+//   *
+//   * This software is licensed under terms that can be found in the LICENSE file
+//   * in the root directory of this software component.
+//   * If no LICENSE file comes with this software, it is provided AS-IS.
+//   *
+//   ******************************************************************************
+//   */
+//
+// #include "linklayer_plat.h"
+// #include "ll_sys.h"
+// #include <stdint.h>
+//
+/**
+ * @brief  Enable interrupts
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_enable_irq() {
+    LINKLAYER_PLAT_EnableIRQ();
+}
+//
+// /**
+//   * @brief  Disable interrupts
+//   * @param  None
+//   * @retval None
+//   */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_disable_irq() {
+    LINKLAYER_PLAT_DisableIRQ();
+}
+//
+// /**
+//   * @brief  Set the Current Interrupt Priority Mask.
+//   *         All interrupts with low priority level will be masked.
+//   * @param  None
+//   * @retval None
+//   */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_enable_specific_irq(isr_type: u8) {
+    LINKLAYER_PLAT_EnableSpecificIRQ(isr_type);
+}
+//
+// /**
+//   * @brief  Restore the previous interrupt priority level
+//   * @param  None
+//   * @retval None
+//   */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_disable_specific_irq(isr_type: u8) {
+    LINKLAYER_PLAT_DisableSpecificIRQ(isr_type);
+}
+//
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_phy_start_clbr() {
+    LINKLAYER_PLAT_PhyStartClbr();
+}
+//
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_phy_stop_clbr() {
+    LINKLAYER_PLAT_PhyStopClbr();
+}
diff --git a/embassy-stm32-wpan/src/wba/ll_sys/ll_sys_dp_slp.rs b/embassy-stm32-wpan/src/wba/ll_sys/ll_sys_dp_slp.rs
new file mode 100644
index 000000000..ae8223a5a
--- /dev/null
+++ b/embassy-stm32-wpan/src/wba/ll_sys/ll_sys_dp_slp.rs
@@ -0,0 +1,163 @@
+use crate::bindings::link_layer::{
+    _NULL as NULL, DPSLP_STATE_DEEP_SLEEP_DISABLE, DPSLP_STATE_DEEP_SLEEP_ENABLE, LINKLAYER_PLAT_DisableRadioIT,
+    LINKLAYER_PLAT_EnableRadioIT, LL_SYS_DP_SLP_STATE_T_LL_SYS_DP_SLP_DISABLED,
+    LL_SYS_DP_SLP_STATE_T_LL_SYS_DP_SLP_ENABLED, LL_SYS_STATUS_T_LL_SYS_ERROR, LL_SYS_STATUS_T_LL_SYS_OK,
+    OS_TIMER_PRIO_HG_PRIO_TMR, OS_TIMER_STATE_OSTIMERSTOPPED, OS_TIMER_TYPE_OS_TIMER_ONCE, SUCCESS, ble_stat_t,
+    ll_intf_cmn_le_set_dp_slp_mode, ll_sys_dp_slp_state_t, ll_sys_status_t, os_get_tmr_state, os_timer_create,
+    os_timer_id, os_timer_set_prio, os_timer_start, os_timer_stop,
+};
+
+macro_rules! LL_DP_SLP_NO_WAKEUP {
+    () => {
+        !0u32
+    };
+}
+
+macro_rules! LL_INTERNAL_TMR_US_TO_STEPS {
+    ($us:expr) => {
+        ((($us) * 4) / 125)
+    };
+}
+
+// /**
+//   ******************************************************************************
+//   * @file    ll_sys_dp_slp.c
+//   * @author  MCD Application Team
+//   * @brief   Link Layer IP system interface deep sleep management
+//   ******************************************************************************
+//   * @attention
+//   *
+//   * Copyright (c) 2022 STMicroelectronics.
+//   * All rights reserved.
+//   *
+//   * This software is licensed under terms that can be found in the LICENSE file
+//   * in the root directory of this software component.
+//   * If no LICENSE file comes with this software, it is provided AS-IS.
+//   *
+//   ******************************************************************************
+//   */
+//
+// #include "linklayer_plat.h"
+// #include "ll_sys.h"
+// #include "ll_intf_cmn.h"
+//
+// /* Link Layer deep sleep timer */
+static mut RADIO_DP_SLP_TMR_ID: os_timer_id = NULL as *mut _;
+//
+// /* Link Layer deep sleep state */
+static mut LINKLAYER_DP_SLP_STATE: ll_sys_dp_slp_state_t = LL_SYS_DP_SLP_STATE_T_LL_SYS_DP_SLP_DISABLED;
+//
+// /**
+//   * @brief  Initialize resources to handle deep sleep entry/exit
+//   * @param  None
+//   * @retval LL_SYS status
+//   */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_dp_slp_init() -> ll_sys_status_t {
+    let mut return_status: ll_sys_status_t = LL_SYS_STATUS_T_LL_SYS_ERROR;
+
+    /* Create link layer timer for handling IP DEEP SLEEP mode */
+    RADIO_DP_SLP_TMR_ID = os_timer_create(
+        Some(ll_sys_dp_slp_wakeup_evt_clbk),
+        OS_TIMER_TYPE_OS_TIMER_ONCE,
+        NULL as *mut _,
+    );
+
+    /* Set priority of deep sleep timer */
+    os_timer_set_prio(RADIO_DP_SLP_TMR_ID, OS_TIMER_PRIO_HG_PRIO_TMR);
+
+    if RADIO_DP_SLP_TMR_ID != NULL as *mut _ {
+        return_status = LL_SYS_STATUS_T_LL_SYS_OK;
+    }
+
+    return return_status;
+}
+//
+// /**
+//   * @brief  Link Layer deep sleep status getter
+//   * @param  None
+//   * @retval Link Layer deep sleep state
+//   */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_dp_slp_get_state() -> ll_sys_dp_slp_state_t {
+    return LINKLAYER_DP_SLP_STATE;
+}
+//
+// /**
+//   * @brief  The Link Layer IP enters deep sleep mode
+//   * @param  dp_slp_duration    deep sleep duration in us
+//   * @retval LL_SYS status
+//   */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_dp_slp_enter(dp_slp_duration: u32) -> ll_sys_status_t {
+    let cmd_status: ble_stat_t;
+    let os_status: i32;
+    let mut return_status: ll_sys_status_t = LL_SYS_STATUS_T_LL_SYS_ERROR;
+
+    /* Check if deep sleep timer has to be started */
+    if dp_slp_duration < LL_DP_SLP_NO_WAKEUP!() {
+        /* Start deep sleep timer */
+        os_status = os_timer_start(RADIO_DP_SLP_TMR_ID, LL_INTERNAL_TMR_US_TO_STEPS!(dp_slp_duration));
+    } else {
+        /* No timer started */
+        os_status = SUCCESS as i32;
+    }
+
+    if os_status == SUCCESS as i32 {
+        /* Switch Link Layer IP to DEEP SLEEP mode */
+        cmd_status = ll_intf_cmn_le_set_dp_slp_mode(DPSLP_STATE_DEEP_SLEEP_ENABLE as u8);
+        if cmd_status == SUCCESS {
+            LINKLAYER_DP_SLP_STATE = LL_SYS_DP_SLP_STATE_T_LL_SYS_DP_SLP_ENABLED;
+            return_status = LL_SYS_STATUS_T_LL_SYS_OK;
+        }
+    }
+
+    return return_status;
+}
+//
+// /**
+//   * @brief  The Link Layer IP exits deep sleep mode
+//   * @param  None
+//   * @retval LL_SYS status
+//   */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_dp_slp_exit() -> ll_sys_status_t {
+    let cmd_status: ble_stat_t;
+    let mut return_status: ll_sys_status_t = LL_SYS_STATUS_T_LL_SYS_ERROR;
+
+    /* Disable radio interrupt */
+    LINKLAYER_PLAT_DisableRadioIT();
+
+    if LINKLAYER_DP_SLP_STATE == LL_SYS_DP_SLP_STATE_T_LL_SYS_DP_SLP_DISABLED {
+        /* Radio not in sleep mode */
+        return_status = LL_SYS_STATUS_T_LL_SYS_OK;
+    } else {
+        /* Switch Link Layer IP to SLEEP mode (by deactivate DEEP SLEEP mode) */
+        cmd_status = ll_intf_cmn_le_set_dp_slp_mode(DPSLP_STATE_DEEP_SLEEP_DISABLE as u8);
+        if cmd_status == SUCCESS {
+            LINKLAYER_DP_SLP_STATE = LL_SYS_DP_SLP_STATE_T_LL_SYS_DP_SLP_DISABLED;
+            return_status = LL_SYS_STATUS_T_LL_SYS_OK;
+        }
+
+        /* Stop the deep sleep wake-up timer if running */
+        if os_get_tmr_state(RADIO_DP_SLP_TMR_ID) != OS_TIMER_STATE_OSTIMERSTOPPED {
+            os_timer_stop(RADIO_DP_SLP_TMR_ID);
+        }
+    }
+
+    /* Re-enable radio interrupt */
+    LINKLAYER_PLAT_EnableRadioIT();
+
+    return return_status;
+}
+
+/**
+ * @brief  Link Layer deep sleep wake-up timer callback
+ * @param  ptr_arg    pointer passed through the callback
+ * @retval LL_SYS status
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_dp_slp_wakeup_evt_clbk(_ptr_arg: *const ::core::ffi::c_void) {
+    /* Link Layer IP exits from DEEP SLEEP mode */
+    ll_sys_dp_slp_exit();
+}
diff --git a/embassy-stm32-wpan/src/wba/ll_sys/ll_sys_intf.rs b/embassy-stm32-wpan/src/wba/ll_sys/ll_sys_intf.rs
new file mode 100644
index 000000000..0b4b0b37f
--- /dev/null
+++ b/embassy-stm32-wpan/src/wba/ll_sys/ll_sys_intf.rs
@@ -0,0 +1,199 @@
+use crate::bindings::link_layer::{
+    Evnt_timing_t, HostStack_Process, LINKLAYER_PLAT_AclkCtrl, LINKLAYER_PLAT_Assert, LINKLAYER_PLAT_ClockInit,
+    LINKLAYER_PLAT_DelayUs, LINKLAYER_PLAT_GetRNG, LINKLAYER_PLAT_RCOStartClbr, LINKLAYER_PLAT_RCOStopClbr,
+    LINKLAYER_PLAT_RequestTemperature, LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT, LINKLAYER_PLAT_SetupRadioIT,
+    LINKLAYER_PLAT_SetupSwLowIT, LINKLAYER_PLAT_StartRadioEvt, LINKLAYER_PLAT_StopRadioEvt,
+    LINKLAYER_PLAT_TriggerSwLowIT, LINKLAYER_PLAT_WaitHclkRdy, MAX_NUM_CNCRT_STAT_MCHNS, emngr_can_mcu_sleep,
+    emngr_handle_all_events, ll_sys_schedule_bg_process,
+};
+
+// /**
+//   ******************************************************************************
+//   * @file    ll_sys_intf.c
+//   * @author  MCD Application Team
+//   * @brief   Link Layer IP general system interface
+//   ******************************************************************************
+//   * @attention
+//   *
+//   * Copyright (c) 2022 STMicroelectronics.
+//   * All rights reserved.
+//   *
+//   * This software is licensed under terms that can be found in the LICENSE file
+//   * in the root directory of this software component.
+//   * If no LICENSE file comes with this software, it is provided AS-IS.
+//   *
+//   ******************************************************************************
+//   */
+// #include <stdint.h>
+//
+// #include "ll_sys.h"
+// #include "linklayer_plat.h"
+// #include "event_manager.h"
+// #include "ll_intf.h"
+//
+/**
+ * @brief  Initialize the Link Layer SoC dependencies
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_init() {
+    LINKLAYER_PLAT_ClockInit();
+}
+//
+/**
+ * @brief  Blocking delay in us
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_delay_us(delay: u32) {
+    LINKLAYER_PLAT_DelayUs(delay);
+}
+
+/**
+ * @brief  Assert checking
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_assert(condition: u8) {
+    LINKLAYER_PLAT_Assert(condition);
+}
+
+/**
+ * @brief  Radio active clock management
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_radio_ack_ctrl(enable: u8) {
+    LINKLAYER_PLAT_AclkCtrl(enable);
+}
+
+/**
+ * @brief  Link Layer waits for radio bus clock ready
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_radio_wait_for_busclkrdy() {
+    LINKLAYER_PLAT_WaitHclkRdy();
+}
+
+/**
+ * @brief  Get RNG number for the Link Layer IP
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_get_rng(ptr_rnd: *mut u8, len: u32) {
+    LINKLAYER_PLAT_GetRNG(ptr_rnd, len);
+}
+
+/**
+ * @brief  Initialize the main radio interrupt
+ * @param  intr_cb    radio interrupt callback to link with the radio IRQ
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_setup_radio_intr(intr_cb: ::core::option::Option<unsafe extern "C" fn()>) {
+    LINKLAYER_PLAT_SetupRadioIT(intr_cb);
+}
+
+/**
+ * @brief  Initialize the radio SW low interrupt
+ * @param  intr_cb    radio SW low interrupt interrupt callback to link
+ *                    with the defined interrupt vector
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_setup_radio_sw_low_intr(intr_cb: ::core::option::Option<unsafe extern "C" fn()>) {
+    LINKLAYER_PLAT_SetupSwLowIT(intr_cb);
+}
+
+/**
+ * @brief  Trigger the radio SW low interrupt
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_radio_sw_low_intr_trigger(priority: u8) {
+    LINKLAYER_PLAT_TriggerSwLowIT(priority);
+}
+
+/**
+ * @brief  Link Layer radio activity event notification
+ * @param  start      start/end of radio event
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_radio_evt_not(start: u8) {
+    if start != 0 {
+        LINKLAYER_PLAT_StartRadioEvt();
+    } else {
+        LINKLAYER_PLAT_StopRadioEvt();
+    }
+}
+
+/**
+ * @brief  Link Layer RCO calibration notification
+ * @param  start      start/end of RCO calibration
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_rco_clbr_not(start: u8) {
+    if start != 0 {
+        LINKLAYER_PLAT_RCOStartClbr();
+    } else {
+        LINKLAYER_PLAT_RCOStopClbr();
+    }
+}
+
+/**
+ * @brief  Link Layer temperature request
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_request_temperature() {
+    LINKLAYER_PLAT_RequestTemperature();
+}
+
+/**
+ * @brief  Link Layer background task pcoessing procedure
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_bg_process() {
+    if emngr_can_mcu_sleep() == 0 {
+        emngr_handle_all_events();
+
+        HostStack_Process();
+    }
+
+    if emngr_can_mcu_sleep() == 0 {
+        ll_sys_schedule_bg_process();
+    }
+}
+
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_schldr_timing_update_not(p_evnt_timing: *mut Evnt_timing_t) {
+    LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT(p_evnt_timing);
+}
+
+/**
+ * @brief  Get the number of concurrent state machines for the Link Layer
+ * @param  None
+ * @retval Supported number of concurrent state machines
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_get_concurrent_state_machines_num() -> u8 {
+    return MAX_NUM_CNCRT_STAT_MCHNS as u8;
+}
+//
+// __WEAK void HostStack_Process(void)
+// {
+//
+// }
diff --git a/embassy-stm32-wpan/src/wba/ll_sys/ll_sys_startup.rs b/embassy-stm32-wpan/src/wba/ll_sys/ll_sys_startup.rs
new file mode 100644
index 000000000..074aaeafe
--- /dev/null
+++ b/embassy-stm32-wpan/src/wba/ll_sys/ll_sys_startup.rs
@@ -0,0 +1,125 @@
+use crate::bindings::link_layer::{
+    _NULL as NULL, LL_SYS_STATUS_T_LL_SYS_OK, ble_buff_hdr_p, hci_dispatch_tbl, hci_get_dis_tbl, hst_cbk, ll_intf_init,
+    ll_intf_rgstr_hst_cbk, ll_intf_rgstr_hst_cbk_ll_queue_full, ll_sys_assert, ll_sys_bg_process_init,
+    ll_sys_config_params, ll_sys_dp_slp_init, ll_sys_status_t,
+};
+use crate::bindings::mac::ST_MAC_preInit;
+// /**
+//   ******************************************************************************
+//   * @file    ll_sys_startup.c
+//   * @author  MCD Application Team
+//   * @brief   Link Layer IP system interface startup module
+//   ******************************************************************************
+//   * @attention
+//   *
+//   * Copyright (c) 2022 STMicroelectronics.
+//   * All rights reserved.
+//   *
+//   * This software is licensed under terms that can be found in the LICENSE file
+//   * in the root directory of this software component.
+//   * If no LICENSE file comes with this software, it is provided AS-IS.
+//   *
+//   ******************************************************************************
+//   */
+//
+// #include "ll_fw_config.h"
+// #include "ll_sys.h"
+// #include "ll_intf.h"
+// #include "ll_sys_startup.h"
+// #include "common_types.h"
+// #if defined(MAC)
+// #ifndef OPENTHREAD_CONFIG_FILE
+// /* Projects with MAC Layer (i.e. 15.4 except Thread) */
+// #include "st_mac_802_15_4_sap.h"
+// #endif /* OPENTHREAD_CONFIG_FILE */
+// #endif /* MAC */
+//
+
+#[allow(dead_code)]
+/**
+ * @brief  Missed HCI event flag
+ */
+static mut MISSED_HCI_EVENT_FLAG: u8 = 0;
+
+// static void ll_sys_dependencies_init(void);
+// #if SUPPORT_BLE
+
+#[cfg(feature = "wba_ble")]
+#[allow(dead_code)]
+unsafe extern "C" fn ll_sys_event_missed_cb(_ptr_evnt_hdr: ble_buff_hdr_p) {
+    MISSED_HCI_EVENT_FLAG = 1;
+}
+
+#[cfg(feature = "wba_ble")]
+/**
+ * @brief  Initialize the Link Layer IP BLE controller
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_ble_cntrl_init(host_callback: hst_cbk) {
+    let p_hci_dis_tbl: *const hci_dispatch_tbl = NULL as *const _;
+
+    hci_get_dis_tbl(&p_hci_dis_tbl as *const *const _ as *mut *const _);
+
+    ll_intf_init(p_hci_dis_tbl);
+
+    ll_intf_rgstr_hst_cbk(host_callback);
+
+    ll_intf_rgstr_hst_cbk_ll_queue_full(Some(ll_sys_event_missed_cb));
+
+    ll_sys_dependencies_init();
+}
+// #endif /* SUPPORT_BLE */
+// #if defined(MAC)
+// #ifndef OPENTHREAD_CONFIG_FILE
+#[cfg(feature = "wba_mac")]
+/**
+ * @brief  Initialize the Link Layer IP 802.15.4 MAC controller
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_mac_cntrl_init() {
+    ST_MAC_preInit();
+    ll_sys_dependencies_init();
+}
+// #endif /* OPENTHREAD_CONFIG_FILE */
+// #endif /* MAC */
+/**
+ * @brief  Start the Link Layer IP in OpenThread configuration
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_thread_init() {
+    ll_sys_dependencies_init();
+}
+
+/**
+ * @brief  Initialize the Link Layer resources for startup.
+ *         This includes: - Deep Sleep feature resources
+ *                        - Link Layer background task
+ * @param  None
+ * @retval None
+ */
+unsafe fn ll_sys_dependencies_init() {
+    static mut IS_LL_INITIALIZED: u8 = 0;
+    let dp_slp_status: ll_sys_status_t;
+
+    /* Ensure Link Layer resources are created only once */
+    if IS_LL_INITIALIZED == 1 {
+        return;
+    }
+    IS_LL_INITIALIZED = 1;
+
+    /* Deep sleep feature initialization */
+    dp_slp_status = ll_sys_dp_slp_init();
+    ll_sys_assert((dp_slp_status == LL_SYS_STATUS_T_LL_SYS_OK) as u8);
+
+    /* Background task initialization */
+    ll_sys_bg_process_init();
+
+    /* Link Layer user parameters application */
+    ll_sys_config_params();
+}
diff --git a/embassy-stm32-wpan/src/wba/ll_sys/ll_version.rs b/embassy-stm32-wpan/src/wba/ll_sys/ll_version.rs
new file mode 100644
index 000000000..a42e8cc67
--- /dev/null
+++ b/embassy-stm32-wpan/src/wba/ll_sys/ll_version.rs
@@ -0,0 +1,115 @@
+use crate::bindings::link_layer::{
+    LL_SYS_BRIEF_VERSION_MAJOR, LL_SYS_BRIEF_VERSION_MAJOR_MASK, LL_SYS_BRIEF_VERSION_MAJOR_POS,
+    LL_SYS_BRIEF_VERSION_MINOR, LL_SYS_BRIEF_VERSION_MINOR_MASK, LL_SYS_BRIEF_VERSION_MINOR_POS,
+    LL_SYS_BRIEF_VERSION_PATCH, LL_SYS_BRIEF_VERSION_PATCH_MASK, LL_SYS_BRIEF_VERSION_PATCH_POS,
+};
+
+// /**
+//   ******************************************************************************
+//   * @file    ll_version.c
+//   * @author  MCD Application Team
+//   * @brief   Link Layer version interface
+//   ******************************************************************************
+//   * @attention
+//   *
+//   * Copyright (c) 2025 STMicroelectronics.
+//   * All rights reserved.
+//   *
+//   * This software is licensed under terms that can be found in the LICENSE file
+//   * in the root directory of this software component.
+//   * If no LICENSE file comes with this software, it is provided AS-IS.
+//   *
+//   ******************************************************************************
+//   */
+//
+// /* Includes ------------------------------------------------------------------*/
+// /* Integer types */
+// #include <stdint.h>
+//
+// /* Own header file  */
+// #include "ll_version.h"
+//
+// /* Temporary header file for version tracking */
+// #include "ll_tmp_version.h"
+//
+// /* Private defines -----------------------------------------------------------*/
+// /**
+//  * @brief Magic keyword to identify the system version when debugging
+//  */
+//  #define LL_SYS_MAGIC_KEYWORD  0xDEADBEEF
+
+const LL_SYS_MAGIC_KEYWORD: u32 = 0xDEADBEEF;
+
+//
+// /* Private macros ------------------------------------------------------------*/
+// /* Macro to set a specific field value */
+// #define LL_SYS_SET_FIELD_VALUE(value, mask, pos) \
+//   (((value) << (pos)) & (mask))
+
+macro_rules! LL_SYS_SET_FIELD_VALUE {
+    ($value:expr, $mask:expr, $pos:expr) => {
+        ((($value) << ($pos)) & ($mask))
+    };
+}
+
+//
+// /* Private typedef -----------------------------------------------------------*/
+// /**
+//   * @brief Link Layer system version structure definition
+//   */
+#[allow(non_camel_case_types)]
+struct ll_sys_version_t {
+    #[allow(unused)]
+    magic_key_word: u32, /* Magic key word to identify the system version */
+    version: u32, /* System version - i.e.: short hash of latest commit */
+}
+//
+// /* Private variables ---------------------------------------------------------*/
+// /**
+//  * @brief Link Layer brief version definition
+//  */
+const LL_SYS_BRIEF_VERSION: u8 = LL_SYS_SET_FIELD_VALUE!(
+    LL_SYS_BRIEF_VERSION_MAJOR as u8,
+    LL_SYS_BRIEF_VERSION_MAJOR_MASK as u8,
+    LL_SYS_BRIEF_VERSION_MAJOR_POS as u8
+) | LL_SYS_SET_FIELD_VALUE!(
+    LL_SYS_BRIEF_VERSION_MINOR as u8,
+    LL_SYS_BRIEF_VERSION_MINOR_MASK as u8,
+    LL_SYS_BRIEF_VERSION_MINOR_POS as u8
+) | LL_SYS_SET_FIELD_VALUE!(
+    LL_SYS_BRIEF_VERSION_PATCH as u8,
+    LL_SYS_BRIEF_VERSION_PATCH_MASK as u8,
+    LL_SYS_BRIEF_VERSION_PATCH_POS as u8
+);
+//
+// /**
+//  * @brief Link Layer system version structure definition
+//  */
+const LL_SYS_SYSTEM_VERSION: ll_sys_version_t = ll_sys_version_t {
+    magic_key_word: LL_SYS_MAGIC_KEYWORD,
+    version: 0, // LL_SYS_SYSTEM_VERSION,
+};
+//
+// /**
+//  * @brief Link Layer source version structure definition
+//  */
+const LL_SYS_SOURCE_VERSION: ll_sys_version_t = ll_sys_version_t {
+    magic_key_word: LL_SYS_MAGIC_KEYWORD,
+    version: 0, // LL_SYS_SOURCE_VERSION
+};
+//
+// /* Functions Definition ------------------------------------------------------*/
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_get_brief_fw_version() -> u8 {
+    return LL_SYS_BRIEF_VERSION;
+}
+
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_get_system_fw_version() -> u32 {
+    return LL_SYS_SYSTEM_VERSION.version;
+}
+
+#[unsafe(no_mangle)]
+unsafe extern "C" fn ll_sys_get_source_fw_version() -> u32 {
+    return LL_SYS_SOURCE_VERSION.version;
+}
diff --git a/embassy-stm32-wpan/src/wba/ll_sys/mod.rs b/embassy-stm32-wpan/src/wba/ll_sys/mod.rs
new file mode 100644
index 000000000..45e196c96
--- /dev/null
+++ b/embassy-stm32-wpan/src/wba/ll_sys/mod.rs
@@ -0,0 +1,5 @@
+mod ll_sys_cs;
+mod ll_sys_dp_slp;
+mod ll_sys_intf;
+mod ll_sys_startup;
+mod ll_version;
diff --git a/embassy-stm32-wpan/src/wba/ll_sys_if.rs b/embassy-stm32-wpan/src/wba/ll_sys_if.rs
new file mode 100644
index 000000000..7218b69c4
--- /dev/null
+++ b/embassy-stm32-wpan/src/wba/ll_sys_if.rs
@@ -0,0 +1,416 @@
+#![cfg(feature = "wba")]
+// /* USER CODE BEGIN Header */
+// /**
+//   ******************************************************************************
+//   * @file    ll_sys_if.c
+//   * @author  MCD Application Team
+//   * @brief   Source file for initiating system
+//   ******************************************************************************
+//   * @attention
+//   *
+//   * Copyright (c) 2022 STMicroelectronics.
+//   * All rights reserved.
+//   *
+//   * This software is licensed under terms that can be found in the LICENSE file
+//   * in the root directory of this software component.
+//   * If no LICENSE file comes with this software, it is provided AS-IS.
+//   *
+//   ******************************************************************************
+//   */
+// /* USER CODE END Header */
+//
+// #include "main.h"
+// #include "app_common.h"
+// #include "app_conf.h"
+// #include "log_module.h"
+// #include "ll_intf_cmn.h"
+// #include "ll_sys.h"
+// #include "ll_sys_if.h"
+// #include "stm32_rtos.h"
+// #include "utilities_common.h"
+// #if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1)
+// #include "temp_measurement.h"
+// #endif /* (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) */
+// #if (CFG_LPM_STANDBY_SUPPORTED == 0)
+// extern void profile_reset(void);
+// #endif
+// /* Private defines -----------------------------------------------------------*/
+// /* Radio event scheduling method - must be set at 1 */
+// #define USE_RADIO_LOW_ISR                   (1)
+// #define NEXT_EVENT_SCHEDULING_FROM_ISR      (1)
+//
+// /* USER CODE BEGIN PD */
+//
+// /* USER CODE END PD */
+//
+// /* Private macros ------------------------------------------------------------*/
+// /* USER CODE BEGIN PM */
+//
+// /* USER CODE END PM */
+//
+// /* Private constants ---------------------------------------------------------*/
+// /* USER CODE BEGIN PC */
+//
+// /* USER CODE END PC */
+//
+// /* Private variables ---------------------------------------------------------*/
+// /* USER CODE BEGIN PV */
+//
+// /* USER CODE END PV */
+//
+// /* Global variables ----------------------------------------------------------*/
+//
+// /* USER CODE BEGIN GV */
+//
+// /* USER CODE END GV */
+//
+// /* Private functions prototypes-----------------------------------------------*/
+// #if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1)
+// static void ll_sys_bg_temperature_measurement_init(void);
+// #endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */
+// static void ll_sys_sleep_clock_source_selection(void);
+// static uint8_t ll_sys_BLE_sleep_clock_accuracy_selection(void);
+// void ll_sys_reset(void);
+//
+// /* USER CODE BEGIN PFP */
+//
+// /* USER CODE END PFP */
+//
+// /* External variables --------------------------------------------------------*/
+//
+// /* USER CODE BEGIN EV */
+//
+// /* USER CODE END EV */
+//
+// /* Functions Definition ------------------------------------------------------*/
+//
+// /**
+//   * @brief  Link Layer background process initialization
+//   * @param  None
+//   * @retval None
+//   */
+// void ll_sys_bg_process_init(void)
+// {
+//   /* Register Link Layer task */
+//   UTIL_SEQ_RegTask(1U << CFG_TASK_LINK_LAYER, UTIL_SEQ_RFU, ll_sys_bg_process);
+// }
+//
+// /**
+//   * @brief  Link Layer background process next iteration scheduling
+//   * @param  None
+//   * @retval None
+//   */
+// void ll_sys_schedule_bg_process(void)
+// {
+//   UTIL_SEQ_SetTask(1U << CFG_TASK_LINK_LAYER, TASK_PRIO_LINK_LAYER);
+// }
+//
+// /**
+//   * @brief  Link Layer background process next iteration scheduling from ISR
+//   * @param  None
+//   * @retval None
+//   */
+// void ll_sys_schedule_bg_process_isr(void)
+// {
+//   UTIL_SEQ_SetTask(1U << CFG_TASK_LINK_LAYER, TASK_PRIO_LINK_LAYER);
+// }
+//
+// /**
+//   * @brief  Link Layer configuration phase before application startup.
+//   * @param  None
+//   * @retval None
+//   */
+// void ll_sys_config_params(void)
+// {
+// /* USER CODE BEGIN ll_sys_config_params_0 */
+//
+// /* USER CODE END ll_sys_config_params_0 */
+//
+//   /* Configure link layer behavior for low ISR use and next event scheduling method:
+//    * - SW low ISR is used.
+//    * - Next event is scheduled from ISR.
+//    */
+//   ll_intf_cmn_config_ll_ctx_params(USE_RADIO_LOW_ISR, NEXT_EVENT_SCHEDULING_FROM_ISR);
+//   /* Apply the selected link layer sleep timer source */
+//   ll_sys_sleep_clock_source_selection();
+//
+// /* USER CODE BEGIN ll_sys_config_params_1 */
+//
+// /* USER CODE END ll_sys_config_params_1 */
+//
+// #if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1)
+//   /* Initialize link layer temperature measurement background task */
+//   ll_sys_bg_temperature_measurement_init();
+//
+//   /* Link layer IP uses temperature based calibration instead of periodic one */
+//   ll_intf_cmn_set_temperature_sensor_state();
+// #endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */
+//
+//   /* Link Layer power table */
+//   ll_intf_cmn_select_tx_power_table(CFG_RF_TX_POWER_TABLE_ID);
+//
+// #if (USE_CTE_DEGRADATION == 1u)
+//   /* Apply CTE degradation */
+//   ll_sys_apply_cte_settings ();
+// #endif /* (USE_CTE_DEGRADATION == 1u) */
+//
+// /* USER CODE BEGIN ll_sys_config_params_2 */
+//
+// /* USER CODE END ll_sys_config_params_2 */
+// }
+//
+// #if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1)
+//
+// /**
+//   * @brief  Link Layer temperature request background process initialization
+//   * @param  None
+//   * @retval None
+//   */
+// void ll_sys_bg_temperature_measurement_init(void)
+// {
+//   /* Register Temperature Measurement task */
+//   UTIL_SEQ_RegTask(1U << CFG_TASK_TEMP_MEAS, UTIL_SEQ_RFU, TEMPMEAS_RequestTemperatureMeasurement);
+// }
+//
+// /**
+//   * @brief  Request backroud task processing for temperature measurement
+//   * @param  None
+//   * @retval None
+//   */
+// void ll_sys_bg_temperature_measurement(void)
+// {
+//   static uint8_t initial_temperature_acquisition = 0;
+//
+//   if(initial_temperature_acquisition == 0)
+//   {
+//     TEMPMEAS_RequestTemperatureMeasurement();
+//     initial_temperature_acquisition = 1;
+//   }
+//   else
+//   {
+//     UTIL_SEQ_SetTask(1U << CFG_TASK_TEMP_MEAS, CFG_SEQ_PRIO_0);
+//   }
+// }
+//
+// #endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */
+//
+// uint8_t ll_sys_BLE_sleep_clock_accuracy_selection(void)
+// {
+//   uint8_t BLE_sleep_clock_accuracy = 0;
+// #if (CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE == 0)
+//   uint32_t RevID = LL_DBGMCU_GetRevisionID();
+// #endif
+//   uint32_t linklayer_slp_clk_src = LL_RCC_RADIO_GetSleepTimerClockSource();
+//
+//   if(linklayer_slp_clk_src == LL_RCC_RADIOSLEEPSOURCE_LSE)
+//   {
+//     /* LSE selected as Link Layer sleep clock source.
+//        Sleep clock accuracy is different regarding the WBA device ID and revision
+//      */
+// #if (CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE == 0)
+// #if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx)
+//     if(RevID == REV_ID_A)
+//     {
+//       BLE_sleep_clock_accuracy = STM32WBA5x_REV_ID_A_SCA_RANGE;
+//     }
+//     else if(RevID == REV_ID_B)
+//     {
+//       BLE_sleep_clock_accuracy = STM32WBA5x_REV_ID_B_SCA_RANGE;
+//     }
+//     else
+//     {
+//       /* Revision ID not supported, default value of 500ppm applied */
+//       BLE_sleep_clock_accuracy = STM32WBA5x_DEFAULT_SCA_RANGE;
+//     }
+// #elif defined(STM32WBA65xx)
+//     BLE_sleep_clock_accuracy = STM32WBA6x_SCA_RANGE;
+//     UNUSED(RevID);
+// #else
+//     UNUSED(RevID);
+// #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */
+// #else /* CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE */
+//     BLE_sleep_clock_accuracy = CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE;
+// #endif /* CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE */
+//   }
+//   else
+//   {
+//     /* LSE is not the Link Layer sleep clock source, sleep clock accurcay default value is 500 ppm */
+//     BLE_sleep_clock_accuracy = STM32WBA5x_DEFAULT_SCA_RANGE;
+//   }
+//
+//   return BLE_sleep_clock_accuracy;
+// }
+//
+// void ll_sys_sleep_clock_source_selection(void)
+// {
+//   uint16_t freq_value = 0;
+//   uint32_t linklayer_slp_clk_src = LL_RCC_RADIOSLEEPSOURCE_NONE;
+//
+//   linklayer_slp_clk_src = LL_RCC_RADIO_GetSleepTimerClockSource();
+//   switch(linklayer_slp_clk_src)
+//   {
+//     case LL_RCC_RADIOSLEEPSOURCE_LSE:
+//       linklayer_slp_clk_src = RTC_SLPTMR;
+//       break;
+//
+//     case LL_RCC_RADIOSLEEPSOURCE_LSI:
+//       linklayer_slp_clk_src = RCO_SLPTMR;
+//       break;
+//
+//     case LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000:
+//       linklayer_slp_clk_src = CRYSTAL_OSCILLATOR_SLPTMR;
+//       break;
+//
+//     case LL_RCC_RADIOSLEEPSOURCE_NONE:
+//       /* No Link Layer sleep clock source selected */
+//       assert_param(0);
+//       break;
+//   }
+//   ll_intf_cmn_le_select_slp_clk_src((uint8_t)linklayer_slp_clk_src, &freq_value);
+// }
+//
+// void ll_sys_reset(void)
+// {
+//   uint8_t bsca = 0;
+//   /* Link layer timings */
+//   uint8_t drift_time = DRIFT_TIME_DEFAULT;
+//   uint8_t exec_time = EXEC_TIME_DEFAULT;
+//
+// /* USER CODE BEGIN ll_sys_reset_0 */
+//
+// /* USER CODE END ll_sys_reset_0 */
+//
+//   /* Apply the selected link layer sleep timer source */
+//   ll_sys_sleep_clock_source_selection();
+//
+//   /* Configure the link layer sleep clock accuracy */
+//   bsca = ll_sys_BLE_sleep_clock_accuracy_selection();
+//   ll_intf_le_set_sleep_clock_accuracy(bsca);
+//
+//   /* Update link layer timings depending on selected configuration */
+//   if(LL_RCC_RADIO_GetSleepTimerClockSource() == LL_RCC_RADIOSLEEPSOURCE_LSI)
+//   {
+//     drift_time += DRIFT_TIME_EXTRA_LSI2;
+//     exec_time += EXEC_TIME_EXTRA_LSI2;
+//   }
+//   else
+//   {
+// #if defined(__GNUC__) && defined(DEBUG)
+//     drift_time += DRIFT_TIME_EXTRA_GCC_DEBUG;
+//     exec_time += EXEC_TIME_EXTRA_GCC_DEBUG;
+// #endif
+//   }
+//
+//   /* USER CODE BEGIN ll_sys_reset_1 */
+//
+//   /* USER CODE END ll_sys_reset_1 */
+//
+//   if((drift_time != DRIFT_TIME_DEFAULT) || (exec_time != EXEC_TIME_DEFAULT))
+//   {
+//     ll_sys_config_BLE_schldr_timings(drift_time, exec_time);
+//   }
+//   /* USER CODE BEGIN ll_sys_reset_2 */
+//
+//   /* USER CODE END ll_sys_reset_2 */
+// }
+// #if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA65xx)
+// void ll_sys_apply_cte_settings(void)
+// {
+//   ll_intf_apply_cte_degrad_change();
+// }
+// #endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) || defined(STM32WBA65xx) */
+//
+// #if (CFG_LPM_STANDBY_SUPPORTED == 0)
+// void ll_sys_get_ble_profile_statistics(uint32_t* exec_time, uint32_t* drift_time, uint32_t* average_drift_time, uint8_t reset)
+// {
+//   if (reset != 0U)
+//   {
+//     profile_reset();
+//   }
+//   ll_intf_get_profile_statistics(exec_time, drift_time, average_drift_time);
+// }
+// #endif
+//
+use super::bindings::{link_layer, mac};
+use super::util_seq;
+
+const UTIL_SEQ_RFU: u32 = 0;
+const TASK_LINK_LAYER_MASK: u32 = 1 << mac::CFG_TASK_ID_T_CFG_TASK_LINK_LAYER;
+const TASK_PRIO_LINK_LAYER: u32 = mac::CFG_SEQ_PRIO_ID_T_CFG_SEQ_PRIO_0 as u32;
+
+/**
+ * @brief  Link Layer background process initialization
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn ll_sys_bg_process_init() {
+    util_seq::UTIL_SEQ_RegTask(TASK_LINK_LAYER_MASK, UTIL_SEQ_RFU, Some(link_layer::ll_sys_bg_process));
+}
+
+/**
+ * @brief  Link Layer background process next iteration scheduling
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn ll_sys_schedule_bg_process() {
+    util_seq::UTIL_SEQ_SetTask(TASK_LINK_LAYER_MASK, TASK_PRIO_LINK_LAYER);
+}
+
+/**
+ * @brief  Link Layer background process next iteration scheduling from ISR
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn ll_sys_schedule_bg_process_isr() {
+    util_seq::UTIL_SEQ_SetTask(TASK_LINK_LAYER_MASK, TASK_PRIO_LINK_LAYER);
+}
+
+/**
+ * @brief  Link Layer configuration phase before application startup.
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn ll_sys_config_params() {
+    let allow_low_isr = mac::USE_RADIO_LOW_ISR as u8;
+    let run_from_isr = mac::NEXT_EVENT_SCHEDULING_FROM_ISR as u8;
+    let _ = link_layer::ll_intf_cmn_config_ll_ctx_params(allow_low_isr, run_from_isr);
+
+    ll_sys_sleep_clock_source_selection();
+    let _ = link_layer::ll_intf_cmn_select_tx_power_table(mac::CFG_RF_TX_POWER_TABLE_ID as u8);
+}
+
+/**
+ * @brief  Reset Link Layer timing parameters to their default configuration.
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn ll_sys_reset() {
+    ll_sys_sleep_clock_source_selection();
+
+    let sleep_accuracy = ll_sys_BLE_sleep_clock_accuracy_selection();
+    let _ = link_layer::ll_intf_le_set_sleep_clock_accuracy(sleep_accuracy);
+}
+
+/// Select the sleep-clock source used by the Link Layer.
+/// Defaults to the crystal oscillator when no explicit configuration is available.
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn ll_sys_sleep_clock_source_selection() {
+    let mut frequency: u16 = 0;
+    let _ = link_layer::ll_intf_cmn_le_select_slp_clk_src(
+        link_layer::_SLPTMR_SRC_TYPE_E_CRYSTAL_OSCILLATOR_SLPTMR as u8,
+        &mut frequency as *mut u16,
+    );
+}
+
+/// Determine the BLE sleep-clock accuracy used by the stack.
+/// Returns zero when board-specific calibration data is unavailable.
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn ll_sys_BLE_sleep_clock_accuracy_selection() -> u8 {
+    // TODO: derive the board-specific sleep clock accuracy once calibration data is available.
+    0
+}
diff --git a/embassy-stm32-wpan/src/wba/mac_sys_if.rs b/embassy-stm32-wpan/src/wba/mac_sys_if.rs
new file mode 100644
index 000000000..273399a19
--- /dev/null
+++ b/embassy-stm32-wpan/src/wba/mac_sys_if.rs
@@ -0,0 +1,188 @@
+#![cfg(feature = "wba")]
+#![allow(non_snake_case)]
+
+//
+// /* USER CODE BEGIN Header */
+// /**
+//   ******************************************************************************
+//   * @file    mac_sys_if.c
+//   * @author  MCD Application Team
+//   * @brief   Source file for using MAC Layer with a RTOS
+//   ******************************************************************************
+//   * @attention
+//   *
+//   * Copyright (c) 2025 STMicroelectronics.
+//   * All rights reserved.
+//   *
+//   * This software is licensed under terms that can be found in the LICENSE file
+//   * in the root directory of this software component.
+//   * If no LICENSE file comes with this software, it is provided AS-IS.
+//   *
+//   ******************************************************************************
+//   */
+// /* USER CODE END Header */
+//
+// #include "main.h"
+// #include "app_common.h"
+// #include "app_conf.h"
+// #include "log_module.h"
+// #include "stm32_rtos.h"
+// #include "st_mac_802_15_4_sys.h"
+//
+// extern void mac_baremetal_run(void);
+//
+// /* Private defines -----------------------------------------------------------*/
+// /* USER CODE BEGIN PD */
+//
+// /* USER CODE END PD */
+//
+// /* Private macros ------------------------------------------------------------*/
+// /* USER CODE BEGIN PM */
+//
+// /* USER CODE END PM */
+//
+// /* Private variables ---------------------------------------------------------*/
+// /* USER CODE BEGIN PV */
+//
+// /* USER CODE END PV */
+//
+// /* Global variables ----------------------------------------------------------*/
+// /* USER CODE BEGIN GV */
+//
+// /* USER CODE END GV */
+//
+// /* Functions Definition ------------------------------------------------------*/
+//
+// /**
+//   * @brief  Mac Layer Initialisation
+//   * @param  None
+//   * @retval None
+//   */
+// void MacSys_Init(void)
+// {
+//   /* Register tasks */
+//   UTIL_SEQ_RegTask( TASK_MAC_LAYER, UTIL_SEQ_RFU, mac_baremetal_run);
+// }
+//
+// /**
+//   * @brief  Mac Layer Resume
+//   * @param  None
+//   * @retval None
+//   */
+// void MacSys_Resume(void)
+// {
+//   UTIL_SEQ_ResumeTask( TASK_MAC_LAYER );
+// }
+//
+// /**
+//   * @brief  MAC Layer set Task.
+//   * @param  None
+//   * @retval None
+//   */
+// void MacSys_SemaphoreSet(void)
+// {
+//   UTIL_SEQ_SetTask( TASK_MAC_LAYER, TASK_PRIO_MAC_LAYER );
+// }
+//
+// /**
+//   * @brief  MAC Layer Task wait.
+//   * @param  None
+//   * @retval None
+//   */
+// void MacSys_SemaphoreWait( void )
+// {
+//   /* Not used */
+// }
+//
+// /**
+//   * @brief  MAC Layer set Event.
+//   * @param  None
+//   * @retval None
+//   */
+// void MacSys_EventSet( void )
+// {
+//   UTIL_SEQ_SetEvt( EVENT_MAC_LAYER );
+// }
+//
+// /**
+//   * @brief  MAC Layer wait Event.
+//   * @param  None
+//   * @retval None
+//   */
+// void MacSys_EventWait( void )
+// {
+//   UTIL_SEQ_WaitEvt( EVENT_MAC_LAYER );
+// }
+//
+
+use super::util_seq;
+use crate::bindings::mac;
+
+/// Placeholder value used by the original ST middleware when registering tasks.
+const UTIL_SEQ_RFU: u32 = 0;
+
+/// Bit mask identifying the MAC layer task within the sequencer.
+const TASK_MAC_LAYER_MASK: u32 = 1 << mac::CFG_TASK_ID_T_CFG_TASK_MAC_LAYER;
+
+/// Sequencer priority assigned to the MAC layer task.
+const TASK_PRIO_MAC_LAYER: u32 = mac::CFG_SEQ_PRIO_ID_T_CFG_SEQ_PRIO_0 as u32;
+
+/// Event flag consumed by the MAC task while waiting on notifications.
+const EVENT_MAC_LAYER_MASK: u32 = 1 << 0;
+
+/// Registers the MAC bare-metal runner with the lightweight sequencer.
+///
+/// Mirrors the behaviour of the reference implementation:
+/// `UTIL_SEQ_RegTask(TASK_MAC_LAYER, UTIL_SEQ_RFU, mac_baremetal_run);`
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn MacSys_Init() {
+    util_seq::UTIL_SEQ_RegTask(TASK_MAC_LAYER_MASK, UTIL_SEQ_RFU, Some(mac::mac_baremetal_run));
+}
+
+/**
+ * @brief  Mac Layer Resume
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn MacSys_Resume() {
+    util_seq::UTIL_SEQ_ResumeTask(TASK_MAC_LAYER_MASK);
+}
+
+/**
+ * @brief  MAC Layer set Task.
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn MacSys_SemaphoreSet() {
+    util_seq::UTIL_SEQ_SetTask(TASK_MAC_LAYER_MASK, TASK_PRIO_MAC_LAYER);
+}
+
+/**
+ * @brief  MAC Layer Task wait.
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn MacSys_SemaphoreWait() {}
+
+/**
+ * @brief  MAC Layer set Event.
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn MacSys_EventSet() {
+    util_seq::UTIL_SEQ_SetEvt(EVENT_MAC_LAYER_MASK);
+}
+
+/**
+ * @brief  MAC Layer wait Event.
+ * @param  None
+ * @retval None
+ */
+#[unsafe(no_mangle)]
+pub unsafe extern "C" fn MacSys_EventWait() {
+    util_seq::UTIL_SEQ_WaitEvt(EVENT_MAC_LAYER_MASK);
+}
diff --git a/embassy-stm32-wpan/src/wba/mod.rs b/embassy-stm32-wpan/src/wba/mod.rs
new file mode 100644
index 000000000..3161b578e
--- /dev/null
+++ b/embassy-stm32-wpan/src/wba/mod.rs
@@ -0,0 +1,6 @@
+pub mod bindings;
+pub mod linklayer_plat;
+pub mod ll_sys;
+pub mod ll_sys_if;
+pub mod mac_sys_if;
+pub mod util_seq;
diff --git a/embassy-stm32-wpan/src/wba/util_seq.rs b/embassy-stm32-wpan/src/wba/util_seq.rs
new file mode 100644
index 000000000..b596df908
--- /dev/null
+++ b/embassy-stm32-wpan/src/wba/util_seq.rs
@@ -0,0 +1,243 @@
+#![cfg(feature = "wba")]
+
+use core::cell::UnsafeCell;
+use core::sync::atomic::{AtomicBool, AtomicU32, Ordering};
+
+use critical_section::with as critical;
+
+type TaskFn = unsafe extern "C" fn();
+
+const MAX_TASKS: usize = 32;
+const DEFAULT_PRIORITY: u8 = u8::MAX;
+
+struct TaskTable {
+    funcs: UnsafeCell<[Option<TaskFn>; MAX_TASKS]>,
+    priorities: UnsafeCell<[u8; MAX_TASKS]>,
+}
+
+impl TaskTable {
+    const fn new() -> Self {
+        Self {
+            funcs: UnsafeCell::new([None; MAX_TASKS]),
+            priorities: UnsafeCell::new([DEFAULT_PRIORITY; MAX_TASKS]),
+        }
+    }
+
+    unsafe fn set_task(&self, idx: usize, func: Option<TaskFn>, priority: u8) {
+        (*self.funcs.get())[idx] = func;
+        (*self.priorities.get())[idx] = priority;
+    }
+
+    unsafe fn update_priority(&self, idx: usize, priority: u8) {
+        (*self.priorities.get())[idx] = priority;
+    }
+
+    unsafe fn task(&self, idx: usize) -> Option<TaskFn> {
+        (*self.funcs.get())[idx]
+    }
+
+    unsafe fn priority(&self, idx: usize) -> u8 {
+        (*self.priorities.get())[idx]
+    }
+}
+
+unsafe impl Sync for TaskTable {}
+
+#[inline(always)]
+fn wake_event() {
+    #[cfg(target_arch = "arm")]
+    {
+        cortex_m::asm::sev();
+    }
+
+    #[cfg(not(target_arch = "arm"))]
+    {
+        // No-op on architectures without SEV support.
+    }
+}
+
+#[inline(always)]
+fn wait_event() {
+    #[cfg(target_arch = "arm")]
+    {
+        cortex_m::asm::wfe();
+    }
+
+    #[cfg(not(target_arch = "arm"))]
+    {
+        core::hint::spin_loop();
+    }
+}
+
+static TASKS: TaskTable = TaskTable::new();
+static PENDING_TASKS: AtomicU32 = AtomicU32::new(0);
+static EVENTS: AtomicU32 = AtomicU32::new(0);
+static SCHEDULING: AtomicBool = AtomicBool::new(false);
+
+fn mask_to_index(mask: u32) -> Option<usize> {
+    if mask == 0 {
+        return None;
+    }
+    let idx = mask.trailing_zeros() as usize;
+    if idx < MAX_TASKS { Some(idx) } else { None }
+}
+
+fn drain_pending_tasks() {
+    loop {
+        if SCHEDULING
+            .compare_exchange(false, true, Ordering::AcqRel, Ordering::Acquire)
+            .is_err()
+        {
+            return;
+        }
+
+        loop {
+            let next = critical(|_| select_next_task());
+            match next {
+                Some((idx, task)) => unsafe {
+                    task();
+                    // Force a fresh read of the pending bitmask after each task completion.
+                    let _ = idx;
+                },
+                None => break,
+            }
+        }
+
+        SCHEDULING.store(false, Ordering::Release);
+
+        if PENDING_TASKS.load(Ordering::Acquire) == 0 {
+            break;
+        }
+    }
+}
+
+/// Poll and execute any tasks that have been scheduled via the UTIL sequencer API.
+pub fn poll_pending_tasks() {
+    drain_pending_tasks();
+}
+
+fn select_next_task() -> Option<(usize, TaskFn)> {
+    let pending = PENDING_TASKS.load(Ordering::Acquire);
+    if pending == 0 {
+        return None;
+    }
+
+    let mut remaining = pending;
+    let mut best_idx: Option<usize> = None;
+    let mut best_priority = DEFAULT_PRIORITY;
+    let mut best_fn: Option<TaskFn> = None;
+
+    while remaining != 0 {
+        let idx = remaining.trailing_zeros() as usize;
+        remaining &= remaining - 1;
+
+        if idx >= MAX_TASKS {
+            continue;
+        }
+
+        unsafe {
+            if let Some(func) = TASKS.task(idx) {
+                let prio = TASKS.priority(idx);
+                if prio <= best_priority {
+                    if prio < best_priority || best_idx.map_or(true, |current| idx < current) {
+                        best_priority = prio;
+                        best_idx = Some(idx);
+                        best_fn = Some(func);
+                    }
+                }
+            } else {
+                PENDING_TASKS.fetch_and(!(1u32 << idx), Ordering::AcqRel);
+            }
+        }
+    }
+
+    if let (Some(idx), Some(func)) = (best_idx, best_fn) {
+        PENDING_TASKS.fetch_and(!(1u32 << idx), Ordering::AcqRel);
+        Some((idx, func))
+    } else {
+        None
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn UTIL_SEQ_RegTask(task_mask: u32, _flags: u32, task: Option<TaskFn>) {
+    if let Some(idx) = mask_to_index(task_mask) {
+        critical(|_| unsafe {
+            TASKS.set_task(idx, task, DEFAULT_PRIORITY);
+        });
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn UTIL_SEQ_UnregTask(task_mask: u32) {
+    if let Some(idx) = mask_to_index(task_mask) {
+        critical(|_| unsafe {
+            TASKS.set_task(idx, None, DEFAULT_PRIORITY);
+        });
+        PENDING_TASKS.fetch_and(!(task_mask), Ordering::AcqRel);
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn UTIL_SEQ_SetTask(task_mask: u32, priority: u32) {
+    let prio = (priority & 0xFF) as u8;
+
+    if let Some(idx) = mask_to_index(task_mask) {
+        let registered = critical(|_| unsafe {
+            if TASKS.task(idx).is_some() {
+                TASKS.update_priority(idx, prio);
+                true
+            } else {
+                false
+            }
+        });
+
+        if registered {
+            PENDING_TASKS.fetch_or(task_mask, Ordering::Release);
+            wake_event();
+        }
+    }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn UTIL_SEQ_ResumeTask(task_mask: u32) {
+    PENDING_TASKS.fetch_or(task_mask, Ordering::Release);
+    wake_event();
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn UTIL_SEQ_PauseTask(task_mask: u32) {
+    PENDING_TASKS.fetch_and(!task_mask, Ordering::AcqRel);
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn UTIL_SEQ_SetEvt(event_mask: u32) {
+    EVENTS.fetch_or(event_mask, Ordering::Release);
+    wake_event();
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn UTIL_SEQ_ClrEvt(event_mask: u32) {
+    EVENTS.fetch_and(!event_mask, Ordering::AcqRel);
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn UTIL_SEQ_IsEvtSet(event_mask: u32) -> u32 {
+    let state = EVENTS.load(Ordering::Acquire);
+    if (state & event_mask) == event_mask { 1 } else { 0 }
+}
+
+#[unsafe(no_mangle)]
+pub extern "C" fn UTIL_SEQ_WaitEvt(event_mask: u32) {
+    loop {
+        poll_pending_tasks();
+
+        let current = EVENTS.load(Ordering::Acquire);
+        if (current & event_mask) == event_mask {
+            EVENTS.fetch_and(!event_mask, Ordering::AcqRel);
+            break;
+        }
+
+        wait_event();
+    }
+}
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 6c36bc108..38f22b1c3 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## Unreleased - ReleaseDate
 
+- fix: stm32: GPDMA driver reset ignored during channel configuration
+- fix: stm32: SPI driver SSOE and SSM manegment, add `nss_output_disable` to SPI Config
+- change: stm32: use typelevel timer type to allow dma for 32 bit timers
 - fix: fix incorrect handling of split interrupts in timer driver
 - feat: allow granular stop for regular usart
 - feat: Add continuous waveform method to SimplePWM
@@ -85,8 +88,11 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - fix: build script ensures EXTI2_TSC is listed as the IRQ of EXTI2 even if the PAC doesn't
 - feat: stm32/lcd: added implementation
 - change: add error messages to can timing calculations ([#4961](https://github.com/embassy-rs/embassy/pull/4961))
+- feat: stm32/spi bidirectional mode 
 - fix: stm32/i2c v2: add stop flag on stop received
 - stm32: Add blocking_listen for blocking I2C driver
+- fix: stm32l47*/stm32l48* adc analog pin setup
+- fix: keep stm32/sai: make NODIV independent of MCKDIV
 
 ## 0.4.0 - 2025-08-26
 
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index e10409112..7989fc5d7 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -200,11 +200,11 @@ aligned = "0.4.1"
 heapless = "0.9.1"
 
 #stm32-metapac = { version = "18" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-f61ed017ef12ec84ff04c49e3147694bda3b29cb" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-497fb3042b49b765d8974aac87b8ab4fa3566d74" }
 
 [build-dependencies]
 #stm32-metapac = { version = "18", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-f61ed017ef12ec84ff04c49e3147694bda3b29cb", default-features = false, features = ["metadata"] }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-497fb3042b49b765d8974aac87b8ab4fa3566d74", default-features = false, features = ["metadata"] }
 
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
diff --git a/embassy-stm32/src/adc/adc4.rs b/embassy-stm32/src/adc/adc4.rs
index 453513309..43509873f 100644
--- a/embassy-stm32/src/adc/adc4.rs
+++ b/embassy-stm32/src/adc/adc4.rs
@@ -5,7 +5,7 @@ use pac::adc::vals::{Adc4Dmacfg as Dmacfg, Adc4Exten as Exten, Adc4OversamplingR
 use pac::adc::vals::{Chselrmod, Cont, Dmacfg, Exten, OversamplingRatio, Ovss, Smpsel};
 
 use super::blocking_delay_us;
-use crate::adc::ConversionMode;
+use crate::adc::{AdcRegs, ConversionMode, Instance};
 #[cfg(stm32u5)]
 pub use crate::pac::adc::regs::Adc4Chselrmod0 as Chselr;
 #[cfg(stm32wba)]
@@ -90,135 +90,112 @@ fn from_ker_ck(frequency: Hertz) -> Presc {
     }
 }
 
-pub trait SealedInstance {
-    #[allow(unused)]
-    fn regs() -> crate::pac::adc::Adc4;
-}
+impl AdcRegs for crate::pac::adc::Adc4 {
+    fn data(&self) -> *mut u16 {
+        crate::pac::adc::Adc4::dr(*self).as_ptr() as *mut u16
+    }
 
-pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeripheral {
-    type Interrupt: crate::interrupt::typelevel::Interrupt;
-}
+    fn enable(&self) {
+        if !self.cr().read().aden() || !self.isr().read().adrdy() {
+            self.isr().write(|w| w.set_adrdy(true));
+            self.cr().modify(|w| w.set_aden(true));
+            while !self.isr().read().adrdy() {}
+        }
+    }
 
-foreach_adc!(
-    (ADC4, $common_inst:ident, $clock:ident) => {
-        use crate::peripherals::ADC4;
+    fn start(&self) {
+        // Start conversion
+        self.cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+    }
 
-        impl super::BasicAnyInstance for ADC4 {
-            type SampleTime = SampleTime;
+    fn stop(&self) {
+        let cr = self.cr().read();
+        if cr.adstart() {
+            self.cr().modify(|w| w.set_adstp(true));
+            while self.cr().read().adstart() {}
         }
 
-        impl super::SealedAnyInstance for ADC4 {
-            fn dr() -> *mut u16 {
-                ADC4::regs().dr().as_ptr() as *mut u16
-            }
+        if cr.aden() || cr.adstart() {
+            self.cr().modify(|w| w.set_addis(true));
+            while self.cr().read().aden() {}
+        }
 
-            fn enable() {
-                if !ADC4::regs().cr().read().aden()  || !ADC4::regs().isr().read().adrdy() {
-                    ADC4::regs().isr().write(|w| w.set_adrdy(true));
-                    ADC4::regs().cr().modify(|w| w.set_aden(true));
-                    while !ADC4::regs().isr().read().adrdy() {}
-                }
-            }
+        // Reset configuration.
+        self.cfgr1().modify(|reg| {
+            reg.set_dmaen(false);
+        });
+    }
 
-            fn start() {
-                // Start conversion
-                ADC4::regs().cr().modify(|reg| {
-                    reg.set_adstart(true);
+    fn configure_dma(&self, conversion_mode: ConversionMode) {
+        match conversion_mode {
+            ConversionMode::Singular => {
+                self.isr().modify(|reg| {
+                    reg.set_ovr(true);
+                    reg.set_eos(true);
+                    reg.set_eoc(true);
                 });
-            }
 
-            fn stop() {
-                let cr = ADC4::regs().cr().read();
-                if cr.adstart() {
-                    ADC4::regs().cr().modify(|w| w.set_adstp(true));
-                    while ADC4::regs().cr().read().adstart() {}
-                }
-
-                if cr.aden() || cr.adstart() {
-                    ADC4::regs().cr().modify(|w| w.set_addis(true));
-                    while ADC4::regs().cr().read().aden() {}
-                }
-
-                // Reset configuration.
-                ADC4::regs().cfgr1().modify(|reg| {
-                    reg.set_dmaen(false);
+                self.cfgr1().modify(|reg| {
+                    reg.set_dmaen(true);
+                    reg.set_dmacfg(Dmacfg::ONE_SHOT);
+                    #[cfg(stm32u5)]
+                    reg.set_chselrmod(false);
+                    #[cfg(stm32wba)]
+                    reg.set_chselrmod(Chselrmod::ENABLE_INPUT)
                 });
             }
+            #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+            _ => unreachable!(),
+        }
+    }
 
-            fn configure_dma(conversion_mode: ConversionMode) {
-                match conversion_mode {
-                    ConversionMode::Singular => {
-                        ADC4::regs().isr().modify(|reg| {
-                            reg.set_ovr(true);
-                            reg.set_eos(true);
-                            reg.set_eoc(true);
-                        });
-
-                        ADC4::regs().cfgr1().modify(|reg| {
-                            reg.set_dmaen(true);
-                            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-                            #[cfg(stm32u5)]
-                            reg.set_chselrmod(false);
-                            #[cfg(stm32wba)]
-                            reg.set_chselrmod(Chselrmod::ENABLE_INPUT)
-                        });
-                    }
-                    #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
-                    _ => unreachable!(),
-                }
-            }
-
-            fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
-                let mut prev_channel: i16 = -1;
-                #[cfg(stm32wba)]
-                ADC4::regs().chselr().write_value(Chselr(0_u32));
-                #[cfg(stm32u5)]
-                ADC4::regs().chselrmod0().write_value(Chselr(0_u32));
-                for (_i, ((channel, _), sample_time)) in sequence.enumerate() {
-                    ADC4::regs().smpr().modify(|w| {
-                        w.set_smp(_i, sample_time);
-                    });
-
-                    let channel_num = channel;
-                    if channel_num as i16 <= prev_channel {
-                        return;
-                    };
-                    prev_channel = channel_num as i16;
-
-                    #[cfg(stm32wba)]
-                    ADC4::regs().chselr().modify(|w| {
-                        w.set_chsel0(channel as usize, true);
-                    });
-                    #[cfg(stm32u5)]
-                    ADC4::regs().chselrmod0().modify(|w| {
-                        w.set_chsel(channel as usize, true);
-                    });
-                }
-            }
+    fn configure_sequence(&self, sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+        let mut prev_channel: i16 = -1;
+        #[cfg(stm32wba)]
+        self.chselr().write_value(Chselr(0_u32));
+        #[cfg(stm32u5)]
+        self.chselrmod0().write_value(Chselr(0_u32));
+        for (_i, ((channel, _), sample_time)) in sequence.enumerate() {
+            self.smpr().modify(|w| {
+                w.set_smp(_i, sample_time);
+            });
+
+            let channel_num = channel;
+            if channel_num as i16 <= prev_channel {
+                return;
+            };
+            prev_channel = channel_num as i16;
 
-            fn convert() -> u16 {
-                // Reset interrupts
-                ADC4::regs().isr().modify(|reg| {
-                    reg.set_eos(true);
-                    reg.set_eoc(true);
-                });
+            #[cfg(stm32wba)]
+            self.chselr().modify(|w| {
+                w.set_chsel0(channel as usize, true);
+            });
+            #[cfg(stm32u5)]
+            self.chselrmod0().modify(|w| {
+                w.set_chsel(channel as usize, true);
+            });
+        }
+    }
 
-                // Start conversion
-                ADC4::regs().cr().modify(|reg| {
-                    reg.set_adstart(true);
-                });
+    fn convert(&self) {
+        // Reset interrupts
+        self.isr().modify(|reg| {
+            reg.set_eos(true);
+            reg.set_eoc(true);
+        });
 
-                while !ADC4::regs().isr().read().eos() {
-                    // spin
-                }
+        // Start conversion
+        self.cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
 
-                ADC4::regs().dr().read().0 as u16
-            }
+        while !self.isr().read().eos() {
+            // spin
         }
-
-        impl super::AnyInstance for ADC4 {}
-    };
-);
+    }
+}
 
 pub struct Adc4<'d, T: Instance> {
     #[allow(unused)]
@@ -231,7 +208,7 @@ pub enum Adc4Error {
     DMAError,
 }
 
-impl<'d, T: Instance + super::AnyInstance> super::Adc<'d, T> {
+impl<'d, T: Instance<Regs = crate::pac::adc::Adc4>> super::Adc<'d, T> {
     /// Create a new ADC driver.
     pub fn new_adc4(adc: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
@@ -267,7 +244,7 @@ impl<'d, T: Instance + super::AnyInstance> super::Adc<'d, T> {
 
         blocking_delay_us(1);
 
-        T::enable();
+        T::regs().enable();
 
         // single conversion mode, software trigger
         T::regs().cfgr1().modify(|w| {
diff --git a/embassy-stm32/src/adc/c0.rs b/embassy-stm32/src/adc/c0.rs
index 3e109e429..2f0f326af 100644
--- a/embassy-stm32/src/adc/c0.rs
+++ b/embassy-stm32/src/adc/c0.rs
@@ -4,7 +4,7 @@ use pac::adccommon::vals::Presc;
 use stm32_metapac::adc::vals::{SampleTime, Scandir};
 
 use super::{Adc, Instance, Resolution, blocking_delay_us};
-use crate::adc::{AnyInstance, ConversionMode};
+use crate::adc::{AdcRegs, ConversionMode};
 use crate::time::Hertz;
 use crate::{Peri, pac, rcc};
 
@@ -43,52 +43,52 @@ fn from_ker_ck(frequency: Hertz) -> Presc {
     }
 }
 
-impl<T: Instance> super::SealedAnyInstance for T {
-    fn dr() -> *mut u16 {
-        T::regs().dr().as_ptr() as *mut u16
+impl AdcRegs for crate::pac::adc::Adc {
+    fn data(&self) -> *mut u16 {
+        crate::pac::adc::Adc::dr(*self).as_ptr() as *mut u16
     }
 
-    fn enable() {
-        T::regs().isr().modify(|w| w.set_adrdy(true));
-        T::regs().cr().modify(|w| w.set_aden(true));
+    fn enable(&self) {
+        self.isr().modify(|w| w.set_adrdy(true));
+        self.cr().modify(|w| w.set_aden(true));
         // ADRDY is "ADC ready". Wait until it will be True.
-        while !T::regs().isr().read().adrdy() {}
+        while !self.isr().read().adrdy() {}
     }
 
-    fn start() {
+    fn start(&self) {
         // Start conversion
-        T::regs().cr().modify(|reg| {
+        self.cr().modify(|reg| {
             reg.set_adstart(true);
         });
     }
 
-    fn stop() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
+    fn stop(&self) {
+        if self.cr().read().adstart() && !self.cr().read().addis() {
+            self.cr().modify(|reg| {
                 reg.set_adstp(Adstp::STOP);
             });
-            while T::regs().cr().read().adstart() {}
+            while self.cr().read().adstart() {}
         }
 
         // Reset configuration.
-        T::regs().cfgr1().modify(|reg| {
+        self.cfgr1().modify(|reg| {
             reg.set_cont(false);
             reg.set_dmacfg(Dmacfg::from_bits(0));
             reg.set_dmaen(false);
         });
     }
 
-    fn configure_dma(conversion_mode: super::ConversionMode) {
+    fn configure_dma(&self, conversion_mode: super::ConversionMode) {
         match conversion_mode {
             ConversionMode::Singular => {
                 // Enable overrun control, so no new DMA requests will be generated until
                 // previous DR values is read.
-                T::regs().isr().modify(|reg| {
+                self.isr().modify(|reg| {
                     reg.set_ovr(true);
                 });
 
                 // Set continuous mode with oneshot dma.
-                T::regs().cfgr1().modify(|reg| {
+                self.cfgr1().modify(|reg| {
                     reg.set_discen(false);
                     reg.set_cont(true);
                     reg.set_dmacfg(Dmacfg::DMA_ONE_SHOT);
@@ -99,7 +99,7 @@ impl<T: Instance> super::SealedAnyInstance for T {
         }
     }
 
-    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), Self::SampleTime)>) {
+    fn configure_sequence(&self, sequence: impl ExactSizeIterator<Item = ((u8, bool), Self::SampleTime)>) {
         let mut needs_hw = sequence.len() == 1 || sequence.len() > CHSELR_SQ_SIZE;
         let mut is_ordered_up = true;
         let mut is_ordered_down = true;
@@ -109,7 +109,7 @@ impl<T: Instance> super::SealedAnyInstance for T {
         let mut last_channel: u8 = 0;
         let mut sample_time: Self::SampleTime = SampleTime::CYCLES2_5;
 
-        T::regs().chselr_sq().write(|w| {
+        self.chselr_sq().write(|w| {
             for (i, ((channel, _), _sample_time)) in sequence.enumerate() {
                 assert!(
                     sample_time == _sample_time || i == 0,
@@ -146,42 +146,40 @@ impl<T: Instance> super::SealedAnyInstance for T {
             );
 
             // Set required channels for multi-convert.
-            unsafe { (T::regs().chselr().as_ptr() as *mut u32).write_volatile(hw_channel_selection) }
+            unsafe { (self.chselr().as_ptr() as *mut u32).write_volatile(hw_channel_selection) }
         }
 
-        T::regs().smpr().modify(|w| {
+        self.smpr().modify(|w| {
             w.smpsel(0);
             w.set_smp1(sample_time);
         });
 
-        T::regs().cfgr1().modify(|reg| {
+        self.cfgr1().modify(|reg| {
             reg.set_chselrmod(!needs_hw);
             reg.set_align(Align::RIGHT);
             reg.set_scandir(if is_ordered_up { Scandir::UP } else { Scandir::BACK });
         });
 
         // Trigger and wait for the channel selection procedure to complete.
-        T::regs().isr().modify(|w| w.set_ccrdy(false));
-        while !T::regs().isr().read().ccrdy() {}
+        self.isr().modify(|w| w.set_ccrdy(false));
+        while !self.isr().read().ccrdy() {}
     }
 
-    fn convert() -> u16 {
+    fn convert(&self) {
         // Set single conversion mode.
-        T::regs().cfgr1().modify(|w| w.set_cont(false));
+        self.cfgr1().modify(|w| w.set_cont(false));
 
         // Start conversion
-        T::regs().cr().modify(|reg| {
+        self.cr().modify(|reg| {
             reg.set_adstart(true);
         });
 
         // Waiting for End Of Conversion (EOC).
-        while !T::regs().isr().read().eoc() {}
-
-        T::regs().dr().read().data() as u16
+        while !self.isr().read().eoc() {}
     }
 }
 
-impl<'d, T: AnyInstance> Adc<'d, T> {
+impl<'d, T: Instance<Regs = crate::pac::adc::Adc>> Adc<'d, T> {
     /// Create a new ADC driver.
     pub fn new(adc: Peri<'d, T>, resolution: Resolution) -> Self {
         rcc::enable_and_reset::<T>();
@@ -225,7 +223,7 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
 
         T::regs().cfgr1().modify(|w| w.set_autoff(autoff_value));
 
-        T::enable();
+        T::regs().enable();
 
         // single conversion mode, software trigger
         T::regs().cfgr1().modify(|w| {
diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index 1767a3bb3..e93ed945f 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -12,7 +12,8 @@ use super::{
     Adc, AnyAdcChannel, ConversionMode, Instance, RegularConversionMode, Resolution, RxDma, SampleTime,
     blocking_delay_us,
 };
-use crate::adc::{AnyInstance, SealedAdcChannel};
+use crate::adc::{AdcRegs, BasicAdcRegs, SealedAdcChannel};
+use crate::pac::adc::regs::{Smpr, Smpr2, Sqr1, Sqr2, Sqr3, Sqr4};
 use crate::time::Hertz;
 use crate::{Peri, pac, rcc};
 
@@ -68,79 +69,77 @@ pub struct ConversionTrigger {
     pub edge: Exten,
 }
 
-impl<T: Instance> super::SealedAnyInstance for T {
-    fn dr() -> *mut u16 {
-        T::regs().dr().as_ptr() as *mut u16
+impl super::AdcRegs for crate::pac::adc::Adc {
+    fn data(&self) -> *mut u16 {
+        crate::pac::adc::Adc::dr(*self).as_ptr() as *mut u16
     }
 
-    fn enable() {
+    fn enable(&self) {
         // Make sure bits are off
-        while T::regs().cr().read().addis() {
+        while self.cr().read().addis() {
             // spin
         }
 
-        if !T::regs().cr().read().aden() {
+        if !self.cr().read().aden() {
             // Enable ADC
-            T::regs().isr().modify(|reg| {
+            self.isr().modify(|reg| {
                 reg.set_adrdy(true);
             });
-            T::regs().cr().modify(|reg| {
+            self.cr().modify(|reg| {
                 reg.set_aden(true);
             });
 
-            while !T::regs().isr().read().adrdy() {
+            while !self.isr().read().adrdy() {
                 // spin
             }
         }
     }
 
-    fn start() {
-        T::regs().cr().modify(|reg| {
+    fn start(&self) {
+        self.cr().modify(|reg| {
             reg.set_adstart(true);
         });
     }
 
-    fn stop() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
+    fn stop(&self) {
+        if self.cr().read().adstart() && !self.cr().read().addis() {
+            self.cr().modify(|reg| {
                 reg.set_adstp(Adstp::STOP);
             });
             // The software must poll ADSTART until the bit is reset before assuming the
             // ADC is completely stopped
-            while T::regs().cr().read().adstart() {}
+            while self.cr().read().adstart() {}
         }
 
         // Disable dma control and continuous conversion, if enabled
-        T::regs().cfgr().modify(|reg| {
+        self.cfgr().modify(|reg| {
             reg.set_cont(false);
             reg.set_dmaen(Dmaen::DISABLE);
         });
     }
 
-    fn convert() -> u16 {
-        T::regs().isr().modify(|reg| {
+    fn convert(&self) {
+        self.isr().modify(|reg| {
             reg.set_eos(true);
             reg.set_eoc(true);
         });
 
         // Start conversion
-        T::regs().cr().modify(|reg| {
+        self.cr().modify(|reg| {
             reg.set_adstart(true);
         });
 
-        while !T::regs().isr().read().eos() {
+        while !self.isr().read().eos() {
             // spin
         }
-
-        T::regs().dr().read().0 as u16
     }
 
-    fn configure_dma(conversion_mode: ConversionMode) {
-        T::regs().isr().modify(|reg| {
+    fn configure_dma(&self, conversion_mode: ConversionMode) {
+        self.isr().modify(|reg| {
             reg.set_ovr(true);
         });
 
-        T::regs().cfgr().modify(|reg| {
+        self.cfgr().modify(|reg| {
             reg.set_discen(false); // Convert all channels for each trigger
             reg.set_dmacfg(match conversion_mode {
                 ConversionMode::Singular => Dmacfg::ONE_SHOT,
@@ -152,43 +151,41 @@ impl<T: Instance> super::SealedAnyInstance for T {
         if let ConversionMode::Repeated(mode) = conversion_mode {
             match mode {
                 RegularConversionMode::Continuous => {
-                    T::regs().cfgr().modify(|reg| {
+                    self.cfgr().modify(|reg| {
                         reg.set_cont(true);
                     });
                 }
                 RegularConversionMode::Triggered(trigger) => {
-                    T::regs().cfgr().modify(|r| {
+                    self.cfgr().modify(|r| {
                         r.set_cont(false); // New trigger is neede for each sample to be read
                     });
 
-                    T::regs().cfgr().modify(|r| {
+                    self.cfgr().modify(|r| {
                         r.set_extsel(trigger.channel);
                         r.set_exten(trigger.edge);
                     });
 
                     // Regular conversions uses DMA so no need to generate interrupt
-                    T::regs().ier().modify(|r| r.set_eosie(false));
+                    self.ier().modify(|r| r.set_eosie(false));
                 }
             }
         }
     }
 
-    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
-        T::regs().cr().modify(|w| w.set_aden(false));
-
-        // Set sequence length
-        T::regs().sqr1().modify(|w| {
-            w.set_l(sequence.len() as u8 - 1);
-        });
+    fn configure_sequence(&self, sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+        self.cr().modify(|w| w.set_aden(false));
 
         #[cfg(stm32g4)]
         let mut difsel = DifselReg::default();
-        let mut smpr = T::regs().smpr().read();
-        let mut smpr2 = T::regs().smpr2().read();
-        let mut sqr1 = T::regs().sqr1().read();
-        let mut sqr2 = T::regs().sqr2().read();
-        let mut sqr3 = T::regs().sqr3().read();
-        let mut sqr4 = T::regs().sqr4().read();
+        let mut smpr = Smpr::default();
+        let mut smpr2 = Smpr2::default();
+        let mut sqr1 = Sqr1::default();
+        let mut sqr2 = Sqr2::default();
+        let mut sqr3 = Sqr3::default();
+        let mut sqr4 = Sqr4::default();
+
+        // Set sequence length
+        sqr1.set_l(sequence.len() as u8 - 1);
 
         // Configure channels and ranks
         for (_i, ((ch, is_differential), sample_time)) in sequence.enumerate() {
@@ -230,18 +227,18 @@ impl<T: Instance> super::SealedAnyInstance for T {
             }
         }
 
-        T::regs().smpr().write_value(smpr);
-        T::regs().smpr2().write_value(smpr2);
-        T::regs().sqr1().write_value(sqr1);
-        T::regs().sqr2().write_value(sqr2);
-        T::regs().sqr3().write_value(sqr3);
-        T::regs().sqr4().write_value(sqr4);
+        self.smpr().write_value(smpr);
+        self.smpr2().write_value(smpr2);
+        self.sqr1().write_value(sqr1);
+        self.sqr2().write_value(sqr2);
+        self.sqr3().write_value(sqr3);
+        self.sqr4().write_value(sqr4);
         #[cfg(stm32g4)]
-        T::regs().difsel().write_value(difsel);
+        self.difsel().write_value(difsel);
     }
 }
 
-impl<'d, T: Instance + AnyInstance> Adc<'d, T> {
+impl<'d, T: Instance<Regs = crate::pac::adc::Adc>> Adc<'d, T> {
     /// Create a new ADC driver.
     pub fn new(adc: Peri<'d, T>, config: AdcConfig) -> Self {
         rcc::enable_and_reset::<T>();
@@ -293,7 +290,7 @@ impl<'d, T: Instance + AnyInstance> Adc<'d, T> {
 
         blocking_delay_us(20);
 
-        T::enable();
+        T::regs().enable();
 
         // single conversion mode, software trigger
         T::regs().cfgr().modify(|w| {
@@ -409,10 +406,10 @@ impl<'d, T: Instance + AnyInstance> Adc<'d, T> {
     ///   `InjectedAdc<T, N>` to enforce bounds at compile time.
     pub fn setup_injected_conversions<'a, const N: usize>(
         self,
-        sequence: [(AnyAdcChannel<T>, SampleTime); N],
+        sequence: [(AnyAdcChannel<'a, T>, SampleTime); N],
         trigger: ConversionTrigger,
         interrupt: bool,
-    ) -> InjectedAdc<T, N> {
+    ) -> InjectedAdc<'a, T, N> {
         assert!(N != 0, "Read sequence cannot be empty");
         assert!(
             N <= NR_INJECTED_RANKS,
@@ -420,12 +417,12 @@ impl<'d, T: Instance + AnyInstance> Adc<'d, T> {
             NR_INJECTED_RANKS
         );
 
-        T::enable();
+        T::regs().enable();
 
         T::regs().jsqr().modify(|w| w.set_jl(N as u8 - 1));
 
-        for (n, (channel, sample_time)) in sequence.into_iter().enumerate() {
-            let sample_time = sample_time.into();
+        for (n, (channel, sample_time)) in sequence.iter().enumerate() {
+            let sample_time = sample_time.clone().into();
             if channel.channel() <= 9 {
                 T::regs()
                     .smpr()
@@ -487,16 +484,16 @@ impl<'d, T: Instance + AnyInstance> Adc<'d, T> {
     /// This function is `unsafe` because it clones the ADC peripheral handle unchecked. Both the
     /// `RingBufferedAdc` and `InjectedAdc` take ownership of the handle and drop it independently.
     /// Ensure no other code concurrently accesses the same ADC instance in a conflicting way.
-    pub fn into_ring_buffered_and_injected<'a, const N: usize>(
+    pub fn into_ring_buffered_and_injected<'a, 'b, const N: usize>(
         self,
         dma: Peri<'a, impl RxDma<T>>,
         dma_buf: &'a mut [u16],
-        regular_sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, T::SampleTime)>,
+        regular_sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<'b, T>, <T::Regs as BasicAdcRegs>::SampleTime)>,
         regular_conversion_mode: RegularConversionMode,
-        injected_sequence: [(AnyAdcChannel<T>, SampleTime); N],
+        injected_sequence: [(AnyAdcChannel<'b, T>, SampleTime); N],
         injected_trigger: ConversionTrigger,
         injected_interrupt: bool,
-    ) -> (super::RingBufferedAdc<'a, T>, InjectedAdc<T, N>) {
+    ) -> (super::RingBufferedAdc<'a, T>, InjectedAdc<'b, T, N>) {
         unsafe {
             (
                 Self {
@@ -531,7 +528,7 @@ impl<'d, T: Instance + AnyInstance> Adc<'d, T> {
     }
 }
 
-impl<T: Instance, const N: usize> InjectedAdc<T, N> {
+impl<'a, T: Instance<Regs = crate::pac::adc::Adc>, const N: usize> InjectedAdc<'a, T, N> {
     /// Read sampled data from all injected ADC injected ranks
     /// Clear the JEOS flag to allow a new injected sequence
     pub(super) fn read_injected_data() -> [u16; N] {
diff --git a/embassy-stm32/src/adc/injected.rs b/embassy-stm32/src/adc/injected.rs
index ccaa5d1b2..029722b84 100644
--- a/embassy-stm32/src/adc/injected.rs
+++ b/embassy-stm32/src/adc/injected.rs
@@ -4,19 +4,19 @@ use core::sync::atomic::{Ordering, compiler_fence};
 #[allow(unused_imports)]
 use embassy_hal_internal::Peri;
 
-use super::{AnyAdcChannel, SampleTime};
+use super::{AdcRegs, AnyAdcChannel, SampleTime};
+use crate::adc::Adc;
 #[allow(unused_imports)]
 use crate::adc::Instance;
-use crate::adc::{Adc, AnyInstance};
 
 /// Injected ADC sequence with owned channels.
-pub struct InjectedAdc<T: Instance, const N: usize> {
-    _channels: [(AnyAdcChannel<T>, SampleTime); N],
+pub struct InjectedAdc<'a, T: Instance<Regs = crate::pac::adc::Adc>, const N: usize> {
+    _channels: [(AnyAdcChannel<'a, T>, SampleTime); N],
     _phantom: PhantomData<T>,
 }
 
-impl<T: Instance, const N: usize> InjectedAdc<T, N> {
-    pub(crate) fn new(channels: [(AnyAdcChannel<T>, SampleTime); N]) -> Self {
+impl<'a, T: Instance<Regs = crate::pac::adc::Adc>, const N: usize> InjectedAdc<'a, T, N> {
+    pub(crate) fn new(channels: [(AnyAdcChannel<'a, T>, SampleTime); N]) -> Self {
         Self {
             _channels: channels,
             _phantom: PhantomData,
@@ -36,9 +36,9 @@ impl<T: Instance, const N: usize> InjectedAdc<T, N> {
     }
 }
 
-impl<T: Instance + AnyInstance, const N: usize> Drop for InjectedAdc<T, N> {
+impl<'a, T: Instance<Regs = crate::pac::adc::Adc>, const N: usize> Drop for InjectedAdc<'a, T, N> {
     fn drop(&mut self) {
-        T::stop();
+        T::regs().stop();
         compiler_fence(Ordering::SeqCst);
     }
 }
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 6d53d9b91..a6af1175a 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -25,12 +25,18 @@ use core::marker::PhantomData;
 #[allow(unused)]
 #[cfg(not(any(adc_f3v3, adc_wba)))]
 pub use _version::*;
-use embassy_hal_internal::{PeripheralType, impl_peripheral};
+#[allow(unused)]
+use embassy_hal_internal::PeripheralType;
 #[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
 use embassy_sync::waitqueue::AtomicWaker;
 #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
 pub use ringbuffered::RingBufferedAdc;
 
+#[cfg(adc_u5)]
+use crate::pac::adc::vals::Adc4SampleTime;
+#[cfg(adc_wba)]
+use crate::pac::adc::vals::SampleTime as Adc4SampleTime;
+
 #[cfg(any(adc_u5, adc_wba))]
 #[path = "adc4.rs"]
 pub mod adc4;
@@ -43,10 +49,10 @@ pub use crate::pac::adc::vals::Res as Resolution;
 pub use crate::pac::adc::vals::SampleTime;
 use crate::peripherals;
 
-dma_trait!(RxDma, AnyInstance);
+dma_trait!(RxDma, Instance);
 
 /// Analog to Digital driver.
-pub struct Adc<'d, T: AnyInstance> {
+pub struct Adc<'d, T: Instance> {
     #[allow(unused)]
     adc: crate::Peri<'d, T>,
 }
@@ -65,79 +71,72 @@ impl State {
     }
 }
 
-trait SealedInstance {
-    #[cfg(not(adc_wba))]
-    #[allow(unused)]
-    fn regs() -> crate::pac::adc::Adc;
-    #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3v3, adc_f3v2, adc_g0)))]
-    #[allow(unused)]
-    fn common_regs() -> crate::pac::adccommon::AdcCommon;
-    #[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
-    fn state() -> &'static State;
+#[cfg(any(adc_f1, adc_f3v1, adc_f3v2, adc_v1, adc_l0))]
+trait_set::trait_set! {
+    pub trait DefaultInstance = Instance;
 }
 
-pub(crate) trait SealedAdcChannel<T> {
-    #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
-    fn setup(&mut self) {}
-
-    #[allow(unused)]
-    fn channel(&self) -> u8;
-
-    #[allow(unused)]
-    fn is_differential(&self) -> bool {
-        false
-    }
+#[cfg(any(adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_g4, adc_c0))]
+trait_set::trait_set! {
+    pub trait DefaultInstance = Instance<Regs = crate::pac::adc::Adc>;
 }
 
-// Temporary patch for ADCs that have not implemented the standard iface yet
-#[cfg(any(adc_v1, adc_l0, adc_f1, adc_f3v1, adc_f3v2, adc_f3v3, adc_v1))]
+#[cfg(adc_wba)]
 trait_set::trait_set! {
-    pub trait AnyInstance = Instance;
+    pub trait DefaultInstance = Instance<Regs = crate::pac::adc::Adc4>;
 }
 
-#[cfg(any(
-    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
-))]
-pub trait BasicAnyInstance {
+pub trait BasicAdcRegs {
     type SampleTime;
 }
 
 #[cfg(any(
     adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
 ))]
-pub(self) trait SealedAnyInstance: BasicAnyInstance {
-    fn enable();
-    fn start();
-    fn stop();
-    fn convert() -> u16;
-    fn configure_dma(conversion_mode: ConversionMode);
-    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), Self::SampleTime)>);
-    #[allow(dead_code)]
-    fn dr() -> *mut u16;
+trait AdcRegs: BasicAdcRegs {
+    fn enable(&self);
+    fn start(&self);
+    fn stop(&self);
+    fn convert(&self);
+    fn configure_dma(&self, conversion_mode: ConversionMode);
+    fn configure_sequence(&self, sequence: impl ExactSizeIterator<Item = ((u8, bool), Self::SampleTime)>);
+    fn data(&self) -> *mut u16;
 }
 
-// On chips without ADC4, AnyInstance is an Instance
-#[cfg(any(adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_g4, adc_c0))]
 #[allow(private_bounds)]
-pub trait AnyInstance: SealedAnyInstance + Instance {}
-
-// On chips with ADC4, AnyInstance is an Instance or adc4::Instance
-#[cfg(any(adc_v4, adc_u5, adc_wba))]
-#[allow(private_bounds)]
-pub trait AnyInstance: SealedAnyInstance + crate::PeripheralType + crate::rcc::RccPeripheral {}
+pub trait BasicInstance {
+    #[cfg(any(
+        adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+    ))]
+    type Regs: AdcRegs;
+}
 
-// Implement AnyInstance automatically for SealedAnyInstance
-#[cfg(any(
-    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
-))]
-impl<T: SealedAnyInstance + Instance> BasicAnyInstance for T {
-    type SampleTime = SampleTime;
+trait SealedInstance: BasicInstance {
+    #[cfg(any(adc_f1, adc_f3v1, adc_f3v2, adc_v1, adc_l0))]
+    fn regs() -> crate::pac::adc::Adc;
+    #[cfg(any(
+        adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+    ))]
+    fn regs() -> Self::Regs;
+    #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3v3, adc_f3v2, adc_g0)))]
+    #[allow(unused)]
+    fn common_regs() -> crate::pac::adccommon::AdcCommon;
+    #[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
+    fn state() -> &'static State;
 }
 
-#[cfg(any(
-    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
-))]
-impl<T: SealedAnyInstance + Instance> AnyInstance for T {}
+pub(crate) trait SealedAdcChannel<T> {
+    #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v3, adc_v4, adc_u5, adc_wba))]
+    fn setup(&mut self) {}
+
+    #[allow(unused)]
+    fn channel(&self) -> u8;
+
+    #[allow(unused)]
+    fn is_differential(&self) -> bool {
+        false
+    }
+}
 
 #[cfg(any(adc_c0, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5))]
 /// Number of samples used for averaging.
@@ -183,28 +182,33 @@ pub enum RegularConversionMode {
     Triggered(ConversionTrigger),
 }
 
-impl<'d, T: AnyInstance> Adc<'d, T> {
+impl<'d, T: Instance> Adc<'d, T> {
     #[cfg(any(
-        adc_v2, adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_u5, adc_v4, adc_wba, adc_c0
+        adc_v2, adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_u5, adc_v3, adc_v4, adc_wba, adc_c0
     ))]
     /// Read an ADC pin.
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: T::SampleTime) -> u16 {
-        #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
+    pub fn blocking_read(
+        &mut self,
+        channel: &mut impl AdcChannel<T>,
+        sample_time: <T::Regs as BasicAdcRegs>::SampleTime,
+    ) -> u16 {
+        #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v3, adc_v4, adc_u5, adc_wba))]
         channel.setup();
 
         // Ensure no conversions are ongoing
-        T::stop();
+        T::regs().stop();
         #[cfg(any(adc_v2, adc_v3, adc_g0, adc_h7rs, adc_u0, adc_u5, adc_wba, adc_c0))]
-        T::enable();
-        T::configure_sequence([((channel.channel(), channel.is_differential()), sample_time)].into_iter());
+        T::regs().enable();
+        T::regs().configure_sequence([((channel.channel(), channel.is_differential()), sample_time)].into_iter());
 
         // On chips with differential channels, enable after configure_sequence to allow setting differential channels
         //
         // TODO: If hardware allows, enable after configure_sequence on all chips
         #[cfg(any(adc_g4, adc_h5))]
-        T::enable();
+        T::regs().enable();
+        T::regs().convert();
 
-        T::convert()
+        unsafe { *T::regs().data() }
     }
 
     #[cfg(any(adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
@@ -241,10 +245,10 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
     /// in order or require the sequence to have the same sample time for all channnels, depending
     /// on the number and properties of the channels in the sequence. This method will panic if
     /// the hardware cannot deliver the requested configuration.
-    pub async fn read(
+    pub async fn read<'a, 'b: 'a>(
         &mut self,
         rx_dma: embassy_hal_internal::Peri<'_, impl RxDma<T>>,
-        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, T::SampleTime)>,
+        sequence: impl ExactSizeIterator<Item = (&'a mut AnyAdcChannel<'b, T>, <T::Regs as BasicAdcRegs>::SampleTime)>,
         readings: &mut [u16],
     ) {
         assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
@@ -258,11 +262,11 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
         );
 
         // Ensure no conversions are ongoing
-        T::stop();
+        T::regs().stop();
         #[cfg(any(adc_g0, adc_v3, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
-        T::enable();
+        T::regs().enable();
 
-        T::configure_sequence(
+        T::regs().configure_sequence(
             sequence.map(|(channel, sample_time)| ((channel.channel, channel.is_differential), sample_time)),
         );
 
@@ -270,20 +274,20 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
         //
         // TODO: If hardware allows, enable after configure_sequence on all chips
         #[cfg(any(adc_g4, adc_h5))]
-        T::enable();
-        T::configure_dma(ConversionMode::Singular);
+        T::regs().enable();
+        T::regs().configure_dma(ConversionMode::Singular);
 
         let request = rx_dma.request();
         let transfer =
-            unsafe { crate::dma::Transfer::new_read(rx_dma, request, T::dr(), readings, Default::default()) };
+            unsafe { crate::dma::Transfer::new_read(rx_dma, request, T::regs().data(), readings, Default::default()) };
 
-        T::start();
+        T::regs().start();
 
         // Wait for conversion sequence to finish.
         transfer.await;
 
         // Ensure conversions are finished.
-        T::stop();
+        T::regs().stop();
     }
 
     #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
@@ -313,11 +317,11 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
     /// in order or require the sequence to have the same sample time for all channnels, depending
     /// on the number and properties of the channels in the sequence. This method will panic if
     /// the hardware cannot deliver the requested configuration.
-    pub fn into_ring_buffered<'a>(
+    pub fn into_ring_buffered<'a, 'b>(
         self,
         dma: embassy_hal_internal::Peri<'a, impl RxDma<T>>,
         dma_buf: &'a mut [u16],
-        sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, T::SampleTime)>,
+        sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<'b, T>, <T::Regs as BasicAdcRegs>::SampleTime)>,
         mode: RegularConversionMode,
     ) -> RingBufferedAdc<'a, T> {
         assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
@@ -327,11 +331,11 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
             "Asynchronous read sequence cannot be more than 16 in length"
         );
         // Ensure no conversions are ongoing
-        T::stop();
+        T::regs().stop();
         #[cfg(any(adc_g0, adc_v3, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
-        T::enable();
+        T::regs().enable();
 
-        T::configure_sequence(
+        T::regs().configure_sequence(
             sequence.map(|(channel, sample_time)| ((channel.channel, channel.is_differential), sample_time)),
         );
 
@@ -339,8 +343,8 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
         //
         // TODO: If hardware allows, enable after configure_sequence on all chips
         #[cfg(any(adc_g4, adc_h5))]
-        T::enable();
-        T::configure_dma(ConversionMode::Repeated(mode));
+        T::regs().enable();
+        T::regs().configure_dma(ConversionMode::Repeated(mode));
 
         core::mem::forget(self);
 
@@ -417,8 +421,11 @@ pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeri
 #[allow(private_bounds)]
 pub trait AdcChannel<T>: SealedAdcChannel<T> + Sized {
     #[allow(unused_mut)]
-    fn degrade_adc(mut self) -> AnyAdcChannel<T> {
-        #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
+    fn degrade_adc<'a>(mut self) -> AnyAdcChannel<'a, T>
+    where
+        Self: 'a,
+    {
+        #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v3, adc_v4, adc_u5, adc_wba))]
         self.setup();
 
         AnyAdcChannel {
@@ -433,14 +440,13 @@ pub trait AdcChannel<T>: SealedAdcChannel<T> + Sized {
 ///
 /// This is useful in scenarios where you need the ADC channels to have the same type, such as
 /// storing them in an array.
-pub struct AnyAdcChannel<T> {
+pub struct AnyAdcChannel<'a, T> {
     channel: u8,
     is_differential: bool,
-    _phantom: PhantomData<T>,
+    _phantom: PhantomData<&'a mut T>,
 }
-impl_peripheral!(AnyAdcChannel<T: AnyInstance>);
-impl<T: AnyInstance> AdcChannel<T> for AnyAdcChannel<T> {}
-impl<T: AnyInstance> SealedAdcChannel<T> for AnyAdcChannel<T> {
+impl<T: Instance> AdcChannel<T> for AnyAdcChannel<'_, T> {}
+impl<T: Instance> SealedAdcChannel<T> for AnyAdcChannel<'_, T> {
     fn channel(&self) -> u8 {
         self.channel
     }
@@ -450,22 +456,41 @@ impl<T: AnyInstance> SealedAdcChannel<T> for AnyAdcChannel<T> {
     }
 }
 
-impl<T> AnyAdcChannel<T> {
+impl<T> AnyAdcChannel<'_, T> {
     #[allow(unused)]
     pub fn get_hw_channel(&self) -> u8 {
         self.channel
     }
 }
+
+#[cfg(not(adc_wba))]
+impl BasicAdcRegs for crate::pac::adc::Adc {
+    type SampleTime = SampleTime;
+}
+
+#[cfg(any(adc_wba, adc_u5))]
+impl BasicAdcRegs for crate::pac::adc::Adc4 {
+    type SampleTime = Adc4SampleTime;
+}
+
 #[cfg(adc_wba)]
 foreach_adc!(
     (ADC4, $common_inst:ident, $clock:ident) => {
-        impl crate::adc::adc4::SealedInstance for peripherals::ADC4 {
-            fn regs() -> crate::pac::adc::Adc4 {
+        impl crate::adc::BasicInstance for peripherals::ADC4 {
+            type Regs = crate::pac::adc::Adc4;
+        }
+
+        impl crate::adc::SealedInstance for peripherals::ADC4 {
+            fn regs() -> Self::Regs {
                 crate::pac::ADC4
             }
+
+            fn common_regs() -> crate::pac::adccommon::AdcCommon {
+                return crate::pac::$common_inst
+            }
         }
 
-        impl crate::adc::adc4::Instance for peripherals::ADC4 {
+        impl crate::adc::Instance for peripherals::ADC4 {
             type Interrupt = crate::_generated::peripheral_interrupts::ADC4::GLOBAL;
         }
     };
@@ -490,20 +515,32 @@ foreach_adc!(
 #[cfg(adc_u5)]
 foreach_adc!(
     (ADC4, $common_inst:ident, $clock:ident) => {
-        impl crate::adc::adc4::SealedInstance for peripherals::ADC4 {
-            fn regs() -> crate::pac::adc::Adc4 {
+        impl crate::adc::BasicInstance for peripherals::ADC4 {
+            type Regs = crate::pac::adc::Adc4;
+        }
+
+        impl crate::adc::SealedInstance for peripherals::ADC4 {
+            fn regs() -> Self::Regs {
                 crate::pac::ADC4
             }
+
+            fn common_regs() -> crate::pac::adccommon::AdcCommon {
+                return crate::pac::$common_inst
+            }
         }
 
-        impl crate::adc::adc4::Instance for peripherals::ADC4 {
+        impl crate::adc::Instance for peripherals::ADC4 {
             type Interrupt = crate::_generated::peripheral_interrupts::ADC4::GLOBAL;
         }
     };
 
     ($inst:ident, $common_inst:ident, $clock:ident) => {
+        impl crate::adc::BasicInstance for peripherals::$inst {
+            type Regs = crate::pac::adc::Adc;
+        }
+
         impl crate::adc::SealedInstance for peripherals::$inst {
-            fn regs() -> crate::pac::adc::Adc {
+            fn regs() -> Self::Regs {
                 crate::pac::$inst
             }
 
@@ -521,14 +558,23 @@ foreach_adc!(
 #[cfg(not(any(adc_u5, adc_wba)))]
 foreach_adc!(
     ($inst:ident, $common_inst:ident, $clock:ident) => {
+        impl crate::adc::BasicInstance for peripherals::$inst {
+            #[cfg(any(
+                adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+            ))]
+            type Regs = crate::pac::adc::Adc;
+        }
+
         impl crate::adc::SealedInstance for peripherals::$inst {
-            #[cfg(not(adc_wba))]
-            fn regs() -> crate::pac::adc::Adc {
+            #[cfg(any(
+                adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+            ))]
+            fn regs() -> Self::Regs {
                 crate::pac::$inst
             }
 
-            #[cfg(adc_wba)]
-            fn regs() -> crate::pac::adc::Adc4 {
+            #[cfg(any(adc_f1, adc_f3v1, adc_f3v2, adc_v1, adc_l0))]
+            fn regs() -> crate::pac::adc::Adc {
                 crate::pac::$inst
             }
 
@@ -554,7 +600,7 @@ macro_rules! impl_adc_pin {
     ($inst:ident, $pin:ident, $ch:expr) => {
         impl crate::adc::AdcChannel<peripherals::$inst> for crate::Peri<'_, crate::peripherals::$pin> {}
         impl crate::adc::SealedAdcChannel<peripherals::$inst> for crate::Peri<'_, crate::peripherals::$pin> {
-            #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
+            #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v3, adc_v4, adc_u5, adc_wba))]
             fn setup(&mut self) {
                 <crate::peripherals::$pin as crate::gpio::SealedPin>::set_as_analog(self);
             }
@@ -582,7 +628,7 @@ macro_rules! impl_adc_pair {
                 crate::Peri<'_, crate::peripherals::$npin>,
             )
         {
-            #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
+            #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v3, adc_v4, adc_u5, adc_wba))]
             fn setup(&mut self) {
                 <crate::peripherals::$pin as crate::gpio::SealedPin>::set_as_analog(&mut self.0);
                 <crate::peripherals::$npin as crate::gpio::SealedPin>::set_as_analog(&mut self.1);
diff --git a/embassy-stm32/src/adc/ringbuffered.rs b/embassy-stm32/src/adc/ringbuffered.rs
index 5437866d3..242a1a89c 100644
--- a/embassy-stm32/src/adc/ringbuffered.rs
+++ b/embassy-stm32/src/adc/ringbuffered.rs
@@ -4,7 +4,7 @@ use core::sync::atomic::{Ordering, compiler_fence};
 #[allow(unused_imports)]
 use embassy_hal_internal::Peri;
 
-use crate::adc::AnyInstance;
+use super::AdcRegs;
 #[allow(unused_imports)]
 use crate::adc::{Instance, RxDma};
 #[allow(unused_imports)]
@@ -19,7 +19,7 @@ pub struct RingBufferedAdc<'d, T: Instance> {
     ring_buf: ReadableRingBuffer<'d, u16>,
 }
 
-impl<'d, T: Instance + AnyInstance> RingBufferedAdc<'d, T> {
+impl<'d, T: Instance> RingBufferedAdc<'d, T> {
     pub(crate) fn new(dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> Self {
         //dma side setup
         let opts = TransferOptions {
@@ -31,8 +31,7 @@ impl<'d, T: Instance + AnyInstance> RingBufferedAdc<'d, T> {
         // Safety: we forget the struct before this function returns.
         let request = dma.request();
 
-        let ring_buf =
-            unsafe { ReadableRingBuffer::new(dma, request, T::regs().dr().as_ptr() as *mut u16, dma_buf, opts) };
+        let ring_buf = unsafe { ReadableRingBuffer::new(dma, request, T::regs().data(), dma_buf, opts) };
 
         Self {
             _phantom: PhantomData,
@@ -45,7 +44,7 @@ impl<'d, T: Instance + AnyInstance> RingBufferedAdc<'d, T> {
         compiler_fence(Ordering::SeqCst);
         self.ring_buf.start();
 
-        T::start();
+        T::regs().start();
     }
 
     pub fn stop(&mut self) {
@@ -117,15 +116,15 @@ impl<'d, T: Instance + AnyInstance> RingBufferedAdc<'d, T> {
             self.start();
         }
 
-        #[cfg(adc_v2)]
-        {
-            // Clear overrun flag if set.
-            if T::regs().sr().read().ovr() {
-                self.stop();
-
-                return Err(OverrunError);
-            }
-        }
+        //        #[cfg(adc_v2)]
+        //        {
+        //            // Clear overrun flag if set.
+        //            if T::regs().sr().read().ovr() {
+        //                self.stop();
+        //
+        //                return Err(OverrunError);
+        //            }
+        //        }
 
         self.ring_buf.read_exact(measurements).await.map_err(|_| OverrunError)
     }
@@ -143,15 +142,16 @@ impl<'d, T: Instance + AnyInstance> RingBufferedAdc<'d, T> {
             self.start();
         }
 
-        #[cfg(adc_v2)]
-        {
-            // Clear overrun flag if set.
-            if T::regs().sr().read().ovr() {
-                self.stop();
+        //        #[cfg(adc_v2)]
+        //        {
+        //            // Clear overrun flag if set.
+        //            if T::regs().sr().read().ovr() {
+        //                self.stop();
+        //
+        //                return Err(OverrunError);
+        //            }
+        //        }
 
-                return Err(OverrunError);
-            }
-        }
         loop {
             match self.ring_buf.read(buf) {
                 Ok((0, _)) => {}
@@ -168,9 +168,9 @@ impl<'d, T: Instance + AnyInstance> RingBufferedAdc<'d, T> {
     }
 }
 
-impl<T: Instance + AnyInstance> Drop for RingBufferedAdc<'_, T> {
+impl<T: Instance> Drop for RingBufferedAdc<'_, T> {
     fn drop(&mut self) {
-        T::stop();
+        T::regs().stop();
 
         compiler_fence(Ordering::SeqCst);
 
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index 3c4431ae0..b026383d5 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -1,7 +1,7 @@
 use core::sync::atomic::{Ordering, compiler_fence};
 
 use super::{ConversionMode, Temperature, Vbat, VrefInt, blocking_delay_us};
-use crate::adc::{Adc, Instance, Resolution, SampleTime};
+use crate::adc::{Adc, AdcRegs, Instance, Resolution, SampleTime};
 use crate::pac::adc::vals;
 pub use crate::pac::adccommon::vals::Adcpre;
 use crate::time::Hertz;
@@ -71,31 +71,31 @@ fn from_pclk2(freq: Hertz) -> Adcpre {
 /// ADC configuration
 #[derive(Default)]
 pub struct AdcConfig {
-    resolution: Option<Resolution>,
+    pub resolution: Option<Resolution>,
 }
 
-impl<T: Instance> super::SealedAnyInstance for T {
-    fn dr() -> *mut u16 {
-        T::regs().dr().as_ptr() as *mut u16
+impl super::AdcRegs for crate::pac::adc::Adc {
+    fn data(&self) -> *mut u16 {
+        crate::pac::adc::Adc::dr(*self).as_ptr() as *mut u16
     }
 
-    fn enable() {
-        T::regs().cr2().modify(|reg| {
+    fn enable(&self) {
+        self.cr2().modify(|reg| {
             reg.set_adon(true);
         });
 
         blocking_delay_us(3);
     }
 
-    fn start() {
+    fn start(&self) {
         // Begin ADC conversions
-        T::regs().cr2().modify(|reg| {
+        self.cr2().modify(|reg| {
             reg.set_swstart(true);
         });
     }
 
-    fn stop() {
-        let r = T::regs();
+    fn stop(&self) {
+        let r = self;
 
         // Stop ADC
         r.cr2().modify(|reg| {
@@ -114,36 +114,34 @@ impl<T: Instance> super::SealedAnyInstance for T {
             w.set_ovrie(false);
         });
 
-        clear_interrupt_flags(r);
+        clear_interrupt_flags(*r);
 
         compiler_fence(Ordering::SeqCst);
     }
 
-    fn convert() -> u16 {
+    fn convert(&self) {
         // clear end of conversion flag
-        T::regs().sr().modify(|reg| {
+        self.sr().modify(|reg| {
             reg.set_eoc(false);
         });
 
         // Start conversion
-        T::regs().cr2().modify(|reg| {
+        self.cr2().modify(|reg| {
             reg.set_swstart(true);
         });
 
-        while T::regs().sr().read().strt() == false {
+        while self.sr().read().strt() == false {
             // spin //wait for actual start
         }
-        while T::regs().sr().read().eoc() == false {
+        while self.sr().read().eoc() == false {
             // spin //wait for finish
         }
-
-        T::regs().dr().read().0 as u16
     }
 
-    fn configure_dma(conversion_mode: ConversionMode) {
+    fn configure_dma(&self, conversion_mode: ConversionMode) {
         match conversion_mode {
             ConversionMode::Repeated(_) => {
-                let r = T::regs();
+                let r = self;
 
                 // Clear all interrupts
                 r.sr().modify(|regs| {
@@ -177,25 +175,25 @@ impl<T: Instance> super::SealedAnyInstance for T {
         }
     }
 
-    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
-        T::regs().cr2().modify(|reg| {
+    fn configure_sequence(&self, sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+        self.cr2().modify(|reg| {
             reg.set_adon(true);
         });
 
         // Check the sequence is long enough
-        T::regs().sqr1().modify(|r| {
+        self.sqr1().modify(|r| {
             r.set_l((sequence.len() - 1).try_into().unwrap());
         });
 
         for (i, ((ch, _), sample_time)) in sequence.enumerate() {
             // Set the channel in the right sequence field.
-            T::regs().sqr3().modify(|w| w.set_sq(i, ch));
+            self.sqr3().modify(|w| w.set_sq(i, ch));
 
             let sample_time = sample_time.into();
             if ch <= 9 {
-                T::regs().smpr2().modify(|reg| reg.set_smp(ch as _, sample_time));
+                self.smpr2().modify(|reg| reg.set_smp(ch as _, sample_time));
             } else {
-                T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
+                self.smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
             }
         }
     }
@@ -203,7 +201,7 @@ impl<T: Instance> super::SealedAnyInstance for T {
 
 impl<'d, T> Adc<'d, T>
 where
-    T: Instance + super::AnyInstance,
+    T: Instance<Regs = crate::pac::adc::Adc>,
 {
     pub fn new(adc: Peri<'d, T>) -> Self {
         Self::new_with_config(adc, Default::default())
@@ -214,7 +212,7 @@ where
 
         let presc = from_pclk2(T::frequency());
         T::common_regs().ccr().modify(|w| w.set_adcpre(presc));
-        T::enable();
+        T::regs().enable();
 
         if let Some(resolution) = config.resolution {
             T::regs().cr1().modify(|reg| reg.set_res(resolution.into()));
@@ -259,9 +257,7 @@ where
 
 impl<'d, T: Instance> Drop for Adc<'d, T> {
     fn drop(&mut self) {
-        T::regs().cr2().modify(|reg| {
-            reg.set_adon(false);
-        });
+        T::regs().stop();
 
         rcc::disable::<T>();
     }
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index b270588c4..9cc44aa9a 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -146,63 +146,63 @@ pub struct AdcConfig {
     pub averaging: Option<Averaging>,
 }
 
-impl<T: Instance> super::SealedAnyInstance for T {
-    fn dr() -> *mut u16 {
-        T::regs().dr().as_ptr() as *mut u16
+impl super::AdcRegs for crate::pac::adc::Adc {
+    fn data(&self) -> *mut u16 {
+        crate::pac::adc::Adc::dr(*self).as_ptr() as *mut u16
     }
 
     // Enable ADC only when it is not already running.
-    fn enable() {
+    fn enable(&self) {
         // Make sure bits are off
-        while T::regs().cr().read().addis() {
+        while self.cr().read().addis() {
             // spin
         }
 
-        if !T::regs().cr().read().aden() {
+        if !self.cr().read().aden() {
             // Enable ADC
-            T::regs().isr().modify(|reg| {
+            self.isr().modify(|reg| {
                 reg.set_adrdy(true);
             });
-            T::regs().cr().modify(|reg| {
+            self.cr().modify(|reg| {
                 reg.set_aden(true);
             });
 
-            while !T::regs().isr().read().adrdy() {
+            while !self.isr().read().adrdy() {
                 // spin
             }
         }
     }
 
-    fn start() {
-        T::regs().cr().modify(|reg| {
+    fn start(&self) {
+        self.cr().modify(|reg| {
             reg.set_adstart(true);
         });
     }
 
-    fn stop() {
+    fn stop(&self) {
         // Ensure conversions are finished.
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
+        if self.cr().read().adstart() && !self.cr().read().addis() {
+            self.cr().modify(|reg| {
                 reg.set_adstp(true);
             });
-            while T::regs().cr().read().adstart() {}
+            while self.cr().read().adstart() {}
         }
 
         // Reset configuration.
         #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| {
+        self.cfgr().modify(|reg| {
             reg.set_cont(false);
             reg.set_dmaen(false);
         });
         #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| {
+        self.cfgr1().modify(|reg| {
             reg.set_cont(false);
             reg.set_dmaen(false);
         });
     }
 
     /// Perform a single conversion.
-    fn convert() -> u16 {
+    fn convert(&self) {
         // Some models are affected by an erratum:
         // If we perform conversions slower than 1 kHz, the first read ADC value can be
         // corrupted, so we discard it and measure again.
@@ -216,36 +216,34 @@ impl<T: Instance> super::SealedAnyInstance for T {
         let len = 1;
 
         for _ in 0..len {
-            T::regs().isr().modify(|reg| {
+            self.isr().modify(|reg| {
                 reg.set_eos(true);
                 reg.set_eoc(true);
             });
 
             // Start conversion
-            T::regs().cr().modify(|reg| {
+            self.cr().modify(|reg| {
                 reg.set_adstart(true);
             });
 
-            while !T::regs().isr().read().eos() {
+            while !self.isr().read().eos() {
                 // spin
             }
         }
-
-        T::regs().dr().read().0 as u16
     }
 
-    fn configure_dma(conversion_mode: ConversionMode) {
+    fn configure_dma(&self, conversion_mode: ConversionMode) {
         // Set continuous mode with oneshot dma.
         // Clear overrun flag before starting transfer.
-        T::regs().isr().modify(|reg| {
+        self.isr().modify(|reg| {
             reg.set_ovr(true);
         });
 
         #[cfg(not(any(adc_g0, adc_u0)))]
-        let regs = T::regs().cfgr();
+        let regs = self.cfgr();
 
         #[cfg(any(adc_g0, adc_u0))]
-        let regs = T::regs().cfgr1();
+        let regs = self.cfgr1();
 
         regs.modify(|reg| {
             reg.set_discen(false);
@@ -259,13 +257,13 @@ impl<T: Instance> super::SealedAnyInstance for T {
         });
     }
 
-    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+    fn configure_sequence(&self, sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
         #[cfg(adc_h5)]
-        T::regs().cr().modify(|w| w.set_aden(false));
+        self.cr().modify(|w| w.set_aden(false));
 
         // Set sequence length
         #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().sqr1().modify(|w| {
+        self.sqr1().modify(|w| {
             w.set_l(sequence.len() as u8 - 1);
         });
 
@@ -273,8 +271,8 @@ impl<T: Instance> super::SealedAnyInstance for T {
         {
             let mut sample_times = Vec::<SampleTime, SAMPLE_TIMES_CAPACITY>::new();
 
-            T::regs().chselr().write(|chselr| {
-                T::regs().smpr().write(|smpr| {
+            self.chselr().write(|chselr| {
+                self.smpr().write(|smpr| {
                     for ((channel, _), sample_time) in sequence {
                         chselr.set_chsel(channel.into(), true);
                         if let Some(i) = sample_times.iter().position(|&t| t == sample_time) {
@@ -306,22 +304,22 @@ impl<T: Instance> super::SealedAnyInstance for T {
                 // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
                 #[cfg(any(adc_h5, adc_h7rs))]
                 if channel == 0 {
-                    T::regs().or().modify(|reg| reg.set_op0(true));
+                    self.or().modify(|reg| reg.set_op0(true));
                 }
 
                 // Configure channel
                 cfg_if! {
                     if #[cfg(adc_u0)] {
                         // On G0 and U6 all channels use the same sampling time.
-                        T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
+                        self.smpr().modify(|reg| reg.set_smp1(sample_time.into()));
                     } else if #[cfg(any(adc_h5, adc_h7rs))] {
                         match channel {
-                            0..=9 => T::regs().smpr1().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
-                            _ => T::regs().smpr2().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
+                            0..=9 => self.smpr1().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
+                            _ => self.smpr2().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
                         }
                     } else {
                         let sample_time = sample_time.into();
-                        T::regs()
+                        self
                             .smpr(channel as usize / 10)
                             .modify(|reg| reg.set_smp(channel as usize % 10, sample_time));
                     }
@@ -331,9 +329,8 @@ impl<T: Instance> super::SealedAnyInstance for T {
                 {
                     use crate::pac::adc::vals::Pcsel;
 
-                    T::regs().cfgr2().modify(|w| w.set_lshift(0));
-                    T::regs()
-                        .pcsel()
+                    self.cfgr2().modify(|w| w.set_lshift(0));
+                    self.pcsel()
                         .write(|w| w.set_pcsel(channel.channel() as _, Pcsel::PRESELECTED));
                 }
 
@@ -341,22 +338,22 @@ impl<T: Instance> super::SealedAnyInstance for T {
                 #[cfg(not(any(adc_g0, adc_u0)))]
                 match _i {
                     0..=3 => {
-                        T::regs().sqr1().modify(|w| {
+                        self.sqr1().modify(|w| {
                             w.set_sq(_i, channel);
                         });
                     }
                     4..=8 => {
-                        T::regs().sqr2().modify(|w| {
+                        self.sqr2().modify(|w| {
                             w.set_sq(_i - 4, channel);
                         });
                     }
                     9..=13 => {
-                        T::regs().sqr3().modify(|w| {
+                        self.sqr3().modify(|w| {
                             w.set_sq(_i - 9, channel);
                         });
                     }
                     14..=15 => {
-                        T::regs().sqr4().modify(|w| {
+                        self.sqr4().modify(|w| {
                             w.set_sq(_i - 14, channel);
                         });
                     }
@@ -375,20 +372,20 @@ impl<T: Instance> super::SealedAnyInstance for T {
             }
 
             #[cfg(adc_h5)]
-            T::regs().difsel().write(|w| w.set_difsel(difsel));
+            self.difsel().write(|w| w.set_difsel(difsel));
 
             // On G0 and U0 enabled channels are sampled from 0 to last channel.
             // It is possible to add up to 8 sequences if CHSELRMOD = 1.
             // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
             #[cfg(adc_u0)]
-            T::regs().chselr().modify(|reg| {
+            self.chselr().modify(|reg| {
                 reg.set_chsel(channel_mask);
             });
         }
     }
 }
 
-impl<'d, T: Instance> Adc<'d, T> {
+impl<'d, T: Instance<Regs = crate::pac::adc::Adc>> Adc<'d, T> {
     /// Enable the voltage regulator
     fn init_regulator() {
         rcc::enable_and_reset::<T>();
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index a3d9e6176..09fc2ab22 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -5,7 +5,7 @@ use pac::adc::vals::{Adstp, Difsel, Dmngt, Exten, Pcsel};
 use pac::adccommon::vals::Presc;
 
 use super::{Adc, Averaging, Instance, Resolution, SampleTime, Temperature, Vbat, VrefInt, blocking_delay_us};
-use crate::adc::ConversionMode;
+use crate::adc::{AdcRegs, ConversionMode};
 use crate::time::Hertz;
 use crate::{Peri, pac, rcc};
 
@@ -80,65 +80,63 @@ pub struct AdcConfig {
     pub averaging: Option<Averaging>,
 }
 
-impl<T: Instance> super::SealedAnyInstance for T {
-    fn dr() -> *mut u16 {
-        T::regs().dr().as_ptr() as *mut u16
+impl AdcRegs for crate::pac::adc::Adc {
+    fn data(&self) -> *mut u16 {
+        crate::pac::adc::Adc::dr(*self).as_ptr() as *mut u16
     }
 
-    fn enable() {
-        T::regs().isr().write(|w| w.set_adrdy(true));
-        T::regs().cr().modify(|w| w.set_aden(true));
-        while !T::regs().isr().read().adrdy() {}
-        T::regs().isr().write(|w| w.set_adrdy(true));
+    fn enable(&self) {
+        self.isr().write(|w| w.set_adrdy(true));
+        self.cr().modify(|w| w.set_aden(true));
+        while !self.isr().read().adrdy() {}
+        self.isr().write(|w| w.set_adrdy(true));
     }
 
-    fn start() {
+    fn start(&self) {
         // Start conversion
-        T::regs().cr().modify(|reg| {
+        self.cr().modify(|reg| {
             reg.set_adstart(true);
         });
     }
 
-    fn stop() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
+    fn stop(&self) {
+        if self.cr().read().adstart() && !self.cr().read().addis() {
+            self.cr().modify(|reg| {
                 reg.set_adstp(Adstp::STOP);
             });
-            while T::regs().cr().read().adstart() {}
+            while self.cr().read().adstart() {}
         }
 
         // Reset configuration.
-        T::regs().cfgr().modify(|reg| {
+        self.cfgr().modify(|reg| {
             reg.set_cont(false);
             reg.set_dmngt(Dmngt::from_bits(0));
         });
     }
 
-    fn convert() -> u16 {
-        T::regs().isr().modify(|reg| {
+    fn convert(&self) {
+        self.isr().modify(|reg| {
             reg.set_eos(true);
             reg.set_eoc(true);
         });
 
         // Start conversion
-        T::regs().cr().modify(|reg| {
+        self.cr().modify(|reg| {
             reg.set_adstart(true);
         });
 
-        while !T::regs().isr().read().eos() {
+        while !self.isr().read().eos() {
             // spin
         }
-
-        T::regs().dr().read().0 as u16
     }
 
-    fn configure_dma(conversion_mode: ConversionMode) {
+    fn configure_dma(&self, conversion_mode: ConversionMode) {
         match conversion_mode {
             ConversionMode::Singular => {
-                T::regs().isr().modify(|reg| {
+                self.isr().modify(|reg| {
                     reg.set_ovr(true);
                 });
-                T::regs().cfgr().modify(|reg| {
+                self.cfgr().modify(|reg| {
                     reg.set_cont(true);
                     reg.set_dmngt(Dmngt::DMA_ONE_SHOT);
                 });
@@ -148,9 +146,9 @@ impl<T: Instance> super::SealedAnyInstance for T {
         }
     }
 
-    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+    fn configure_sequence(&self, sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
         // Set sequence length
-        T::regs().sqr1().modify(|w| {
+        self.sqr1().modify(|w| {
             w.set_l(sequence.len() as u8 - 1);
         });
 
@@ -158,39 +156,35 @@ impl<T: Instance> super::SealedAnyInstance for T {
         for (i, ((channel, _), sample_time)) in sequence.enumerate() {
             let sample_time = sample_time.into();
             if channel <= 9 {
-                T::regs().smpr(0).modify(|reg| reg.set_smp(channel as _, sample_time));
+                self.smpr(0).modify(|reg| reg.set_smp(channel as _, sample_time));
             } else {
-                T::regs()
-                    .smpr(1)
-                    .modify(|reg| reg.set_smp((channel - 10) as _, sample_time));
+                self.smpr(1).modify(|reg| reg.set_smp((channel - 10) as _, sample_time));
             }
 
             #[cfg(any(stm32h7, stm32u5))]
             {
-                T::regs().cfgr2().modify(|w| w.set_lshift(0));
-                T::regs()
-                    .pcsel()
-                    .modify(|w| w.set_pcsel(channel as _, Pcsel::PRESELECTED));
+                self.cfgr2().modify(|w| w.set_lshift(0));
+                self.pcsel().modify(|w| w.set_pcsel(channel as _, Pcsel::PRESELECTED));
             }
 
             match i {
                 0..=3 => {
-                    T::regs().sqr1().modify(|w| {
+                    self.sqr1().modify(|w| {
                         w.set_sq(i, channel);
                     });
                 }
                 4..=8 => {
-                    T::regs().sqr2().modify(|w| {
+                    self.sqr2().modify(|w| {
                         w.set_sq(i - 4, channel);
                     });
                 }
                 9..=13 => {
-                    T::regs().sqr3().modify(|w| {
+                    self.sqr3().modify(|w| {
                         w.set_sq(i - 9, channel);
                     });
                 }
                 14..=15 => {
-                    T::regs().sqr4().modify(|w| {
+                    self.sqr4().modify(|w| {
                         w.set_sq(i - 14, channel);
                     });
                 }
@@ -200,7 +194,7 @@ impl<T: Instance> super::SealedAnyInstance for T {
     }
 }
 
-impl<'d, T: Instance + super::AnyInstance> Adc<'d, T> {
+impl<'d, T: Instance<Regs = crate::pac::adc::Adc>> Adc<'d, T> {
     pub fn new_with_config(adc: Peri<'d, T>, config: AdcConfig) -> Self {
         let s = Self::new(adc);
 
@@ -292,7 +286,7 @@ impl<'d, T: Instance + super::AnyInstance> Adc<'d, T> {
 
         blocking_delay_us(1);
 
-        T::enable();
+        T::regs().enable();
 
         // single conversion mode, software trigger
         T::regs().cfgr().modify(|w| {
diff --git a/embassy-stm32/src/dma/gpdma/mod.rs b/embassy-stm32/src/dma/gpdma/mod.rs
index bfd0570f8..afb18ec1a 100644
--- a/embassy-stm32/src/dma/gpdma/mod.rs
+++ b/embassy-stm32/src/dma/gpdma/mod.rs
@@ -137,7 +137,6 @@ pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: c
 
 impl AnyChannel {
     /// Safety: Must be called with a matching set of parameters for a valid dma channel
-    #[cfg(not(stm32n6))]
     pub(crate) unsafe fn on_irq(&self) {
         let info = self.info();
         #[cfg(feature = "_dual-core")]
@@ -238,6 +237,11 @@ impl AnyChannel {
         // "Preceding reads and writes cannot be moved past subsequent writes."
         fence(Ordering::SeqCst);
 
+        if ch.cr().read().en() {
+            ch.cr().modify(|w| w.set_susp(true));
+            while !ch.sr().read().suspf() {}
+        }
+
         ch.cr().write(|w| w.set_reset(true));
         ch.fcr().write(|w| {
             // Clear all irqs
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index efb324fa6..05d9c2e51 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -25,7 +25,7 @@ pub(crate) use util::*;
 pub(crate) mod ringbuffer;
 pub mod word;
 
-use embassy_hal_internal::{Peri, PeripheralType, impl_peripheral};
+use embassy_hal_internal::{PeripheralType, impl_peripheral};
 
 use crate::interrupt;
 use crate::rcc::StoppablePeripheral;
@@ -47,21 +47,10 @@ pub type Request = u8;
 #[cfg(not(any(dma_v2, bdma_v2, gpdma, dmamux)))]
 pub type Request = ();
 
-impl<'a> StoppablePeripheral for Peri<'a, AnyChannel> {
-    #[cfg(feature = "low-power")]
-    fn stop_mode(&self) -> crate::rcc::StopMode {
-        self.stop_mode
-    }
-}
-
-pub(crate) trait SealedChannel {
-    #[cfg(not(stm32n6))]
+pub(crate) trait SealedChannel: StoppablePeripheral {
     fn id(&self) -> u8;
-    #[cfg(feature = "low-power")]
-    fn stop_mode(&self) -> crate::rcc::StopMode;
 }
 
-#[cfg(not(stm32n6))]
 pub(crate) trait ChannelInterrupt {
     #[cfg_attr(not(feature = "rt"), allow(unused))]
     unsafe fn on_irq();
@@ -71,19 +60,21 @@ pub(crate) trait ChannelInterrupt {
 #[allow(private_bounds)]
 pub trait Channel: SealedChannel + PeripheralType + Into<AnyChannel> + 'static {}
 
-#[cfg(not(stm32n6))]
 macro_rules! dma_channel_impl {
     ($channel_peri:ident, $index:expr, $stop_mode:ident) => {
-        impl crate::dma::SealedChannel for crate::peripherals::$channel_peri {
-            fn id(&self) -> u8 {
-                $index
-            }
-
+        impl crate::rcc::StoppablePeripheral for crate::peripherals::$channel_peri {
             #[cfg(feature = "low-power")]
             fn stop_mode(&self) -> crate::rcc::StopMode {
                 crate::rcc::StopMode::$stop_mode
             }
         }
+
+        impl crate::dma::SealedChannel for crate::peripherals::$channel_peri {
+            fn id(&self) -> u8 {
+                $index
+            }
+        }
+
         impl crate::dma::ChannelInterrupt for crate::peripherals::$channel_peri {
             unsafe fn on_irq() {
                 crate::dma::AnyChannel {
@@ -102,7 +93,7 @@ macro_rules! dma_channel_impl {
                 Self {
                     id: crate::dma::SealedChannel::id(&val),
                     #[cfg(feature = "low-power")]
-                    stop_mode: crate::dma::SealedChannel::stop_mode(&val),
+                    stop_mode: crate::rcc::StoppablePeripheral::stop_mode(&val),
                 }
             }
         }
@@ -123,17 +114,18 @@ impl AnyChannel {
     }
 }
 
-impl SealedChannel for AnyChannel {
-    #[cfg(not(stm32n6))]
-    fn id(&self) -> u8 {
-        self.id
-    }
-
+impl StoppablePeripheral for AnyChannel {
     #[cfg(feature = "low-power")]
     fn stop_mode(&self) -> crate::rcc::StopMode {
         self.stop_mode
     }
 }
+
+impl SealedChannel for AnyChannel {
+    fn id(&self) -> u8 {
+        self.id
+    }
+}
 impl Channel for AnyChannel {}
 
 const CHANNEL_COUNT: usize = crate::_generated::DMA_CHANNELS.len();
diff --git a/embassy-stm32/src/dma/util.rs b/embassy-stm32/src/dma/util.rs
index 3245887c1..304268963 100644
--- a/embassy-stm32/src/dma/util.rs
+++ b/embassy-stm32/src/dma/util.rs
@@ -20,6 +20,16 @@ impl<'d> ChannelAndRequest<'d> {
         Transfer::new_read(self.channel.reborrow(), self.request, peri_addr, buf, options)
     }
 
+    #[allow(dead_code)]
+    pub unsafe fn read_unchecked<'a, W: Word>(
+        &'a self,
+        peri_addr: *mut W,
+        buf: &'a mut [W],
+        options: TransferOptions,
+    ) -> Transfer<'a> {
+        Transfer::new_read(self.channel.clone_unchecked(), self.request, peri_addr, buf, options)
+    }
+
     pub unsafe fn read_raw<'a, MW: Word, PW: Word>(
         &'a mut self,
         peri_addr: *mut PW,
@@ -29,6 +39,16 @@ impl<'d> ChannelAndRequest<'d> {
         Transfer::new_read_raw(self.channel.reborrow(), self.request, peri_addr, buf, options)
     }
 
+    #[allow(dead_code)]
+    pub unsafe fn read_raw_unchecked<'a, MW: Word, PW: Word>(
+        &'a self,
+        peri_addr: *mut PW,
+        buf: *mut [MW],
+        options: TransferOptions,
+    ) -> Transfer<'a> {
+        Transfer::new_read_raw(self.channel.clone_unchecked(), self.request, peri_addr, buf, options)
+    }
+
     pub unsafe fn write<'a, W: Word>(
         &'a mut self,
         buf: &'a [W],
@@ -38,6 +58,16 @@ impl<'d> ChannelAndRequest<'d> {
         Transfer::new_write(self.channel.reborrow(), self.request, buf, peri_addr, options)
     }
 
+    #[allow(dead_code)]
+    pub unsafe fn write_unchecked<'a, W: Word>(
+        &'a self,
+        buf: &'a [W],
+        peri_addr: *mut W,
+        options: TransferOptions,
+    ) -> Transfer<'a> {
+        Transfer::new_write(self.channel.clone_unchecked(), self.request, buf, peri_addr, options)
+    }
+
     pub unsafe fn write_raw<'a, MW: Word, PW: Word>(
         &'a mut self,
         buf: *const [MW],
@@ -48,6 +78,16 @@ impl<'d> ChannelAndRequest<'d> {
     }
 
     #[allow(dead_code)]
+    pub unsafe fn write_raw_unchecked<'a, MW: Word, PW: Word>(
+        &'a self,
+        buf: *const [MW],
+        peri_addr: *mut PW,
+        options: TransferOptions,
+    ) -> Transfer<'a> {
+        Transfer::new_write_raw(self.channel.clone_unchecked(), self.request, buf, peri_addr, options)
+    }
+
+    #[allow(dead_code)]
     pub unsafe fn write_repeated<'a, W: Word>(
         &'a mut self,
         repeated: &'a W,
@@ -64,4 +104,22 @@ impl<'d> ChannelAndRequest<'d> {
             options,
         )
     }
+
+    #[allow(dead_code)]
+    pub unsafe fn write_repeated_unchecked<'a, W: Word>(
+        &'a self,
+        repeated: &'a W,
+        count: usize,
+        peri_addr: *mut W,
+        options: TransferOptions,
+    ) -> Transfer<'a> {
+        Transfer::new_write_repeated(
+            self.channel.clone_unchecked(),
+            self.request,
+            repeated,
+            count,
+            peri_addr,
+            options,
+        )
+    }
 }
diff --git a/embassy-stm32/src/dma/word.rs b/embassy-stm32/src/dma/word.rs
index fb1bde860..5c3bb8f7f 100644
--- a/embassy-stm32/src/dma/word.rs
+++ b/embassy-stm32/src/dma/word.rs
@@ -31,6 +31,10 @@ pub trait Word: SealedWord + Default + Copy + 'static {
     fn size() -> WordSize;
     /// Amount of bits of this word size.
     fn bits() -> usize;
+    /// Maximum value of this type.
+    fn max() -> usize {
+        (1 << Self::bits()) - 1
+    }
 }
 
 macro_rules! impl_word {
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index 7b7896d46..458174b5d 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -74,7 +74,7 @@ unsafe fn on_irq() {
     }
 
     #[cfg(feature = "low-power")]
-    crate::low_power::Executor::on_wakeup_irq();
+    crate::low_power::Executor::on_wakeup_irq_or_event();
 }
 
 struct BitIter(u32);
diff --git a/embassy-stm32/src/fmt.rs b/embassy-stm32/src/fmt.rs
index b6ae24ee8..b731796f0 100644
--- a/embassy-stm32/src/fmt.rs
+++ b/embassy-stm32/src/fmt.rs
@@ -207,6 +207,16 @@ macro_rules! error {
 }
 
 #[cfg(feature = "defmt")]
+trait_set::trait_set! {
+    pub trait Debuggable = Debug + defmt::Format;
+}
+
+#[cfg(not(feature = "defmt"))]
+trait_set::trait_set! {
+    pub trait Debuggable = Debug;
+}
+
+#[cfg(feature = "defmt")]
 #[collapse_debuginfo(yes)]
 macro_rules! unwrap {
     ($($x:tt)*) => {
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index e7d4e9ad3..5de8bad2c 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -684,7 +684,11 @@ fn set_as_analog(pin_port: PinNumber) {
     });
 
     #[cfg(gpio_v2)]
-    r.moder().modify(|w| w.set_moder(n, vals::Moder::ANALOG));
+    {
+        #[cfg(any(stm32l47x, stm32l48x))]
+        r.ascr().modify(|w| w.set_asc(n, true));
+        r.moder().modify(|w| w.set_moder(n, vals::Moder::ANALOG));
+    }
 }
 
 #[inline(never)]
diff --git a/embassy-stm32/src/i2c/mod.rs b/embassy-stm32/src/i2c/mod.rs
index ee60c3f44..0bf430ffc 100644
--- a/embassy-stm32/src/i2c/mod.rs
+++ b/embassy-stm32/src/i2c/mod.rs
@@ -226,7 +226,7 @@ impl<'d, M: Mode> I2c<'d, M, Master> {
     }
 
     fn enable_and_init(&mut self, config: Config) {
-        self.info.rcc.enable_and_reset();
+        self.info.rcc.enable_and_reset_without_stop();
         self.init(config);
     }
 }
diff --git a/embassy-stm32/src/i2c/v1.rs b/embassy-stm32/src/i2c/v1.rs
index 128a58db7..81a6d74c1 100644
--- a/embassy-stm32/src/i2c/v1.rs
+++ b/embassy-stm32/src/i2c/v1.rs
@@ -529,6 +529,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Write.
     pub async fn write(&mut self, address: u8, write_buffer: &[u8]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         self.write_frame(address, write_buffer, FrameOptions::FirstAndLastFrame)
             .await?;
 
@@ -537,6 +538,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Read.
     pub async fn read(&mut self, address: u8, read_buffer: &mut [u8]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         self.read_frame(address, read_buffer, FrameOptions::FirstAndLastFrame)
             .await?;
 
@@ -701,6 +703,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Write, restart, read.
     pub async fn write_read(&mut self, address: u8, write_buffer: &[u8], read_buffer: &mut [u8]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         // Check empty read buffer before starting transaction. Otherwise, we would not generate the
         // stop condition below.
         if read_buffer.is_empty() {
@@ -719,6 +722,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     ///
     /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
     pub async fn transaction(&mut self, address: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         for (op, frame) in operation_frames(operations)? {
             match op {
                 Operation::Read(read_buffer) => self.read_frame(address, read_buffer, frame).await?,
@@ -1357,6 +1361,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
     /// (Read/Write) and the matched address. This method will suspend until
     /// an address match occurs.
     pub async fn listen(&mut self) -> Result<SlaveCommand, Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         trace!("I2C slave: starting async listen for address match");
         let state = self.state;
         let info = self.info;
@@ -1421,6 +1426,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
     ///
     /// Returns the number of bytes stored in the buffer (not total received).
     pub async fn respond_to_write(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         trace!("I2C slave: starting respond_to_write, buffer_len={}", buffer.len());
 
         if buffer.is_empty() {
@@ -1454,6 +1460,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
     ///
     /// Returns the total number of bytes transmitted (data + padding).
     pub async fn respond_to_read(&mut self, data: &[u8]) -> Result<usize, Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         trace!("I2C slave: starting respond_to_read, data_len={}", data.len());
 
         if data.is_empty() {
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 933cca9cb..fe7782a7c 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -73,7 +73,7 @@ pub(crate) unsafe fn on_interrupt<T: Instance>() {
     // restore the clocks to their last configured state as
     // much is lost in STOP modes
     #[cfg(all(feature = "low-power", stm32wlex))]
-    crate::low_power::Executor::on_wakeup_irq();
+    crate::low_power::Executor::on_wakeup_irq_or_event();
 
     let regs = T::info().regs;
     let isr = regs.isr().read();
@@ -1075,6 +1075,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Write.
     pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         let timeout = self.timeout();
         if write.is_empty() {
             self.write_internal(address.into(), write, true, timeout)
@@ -1089,6 +1090,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     ///
     /// The buffers are concatenated in a single write transaction.
     pub async fn write_vectored(&mut self, address: Address, write: &[&[u8]]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         let timeout = self.timeout();
 
         if write.is_empty() {
@@ -1120,6 +1122,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Read.
     pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         let timeout = self.timeout();
 
         if buffer.is_empty() {
@@ -1132,6 +1135,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Write, restart, read.
     pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         let timeout = self.timeout();
 
         if write.is_empty() {
@@ -1157,6 +1161,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     ///
     /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
     pub async fn transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         if operations.is_empty() {
             return Err(Error::ZeroLengthTransfer);
         }
@@ -1741,6 +1746,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
     ///
     /// The listen method is an asynchronous method but it does not require DMA to be asynchronous.
     pub async fn listen(&mut self) -> Result<SlaveCommand, Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         let state = self.state;
         self.info.regs.cr1().modify(|reg| {
             reg.set_addrie(true);
@@ -1766,12 +1772,14 @@ impl<'d> I2c<'d, Async, MultiMaster> {
     ///
     /// Returns the total number of bytes received.
     pub async fn respond_to_write(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         let timeout = self.timeout();
         timeout.with(self.read_dma_internal_slave(buffer, timeout)).await
     }
 
     /// Respond to a read request from an I2C master.
     pub async fn respond_to_read(&mut self, write: &[u8]) -> Result<SendStatus, Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         let timeout = self.timeout();
         timeout.with(self.write_dma_internal_slave(write, timeout)).await
     }
diff --git a/embassy-stm32/src/low_power.rs b/embassy-stm32/src/low_power.rs
index cdf3323fb..2388abe3c 100644
--- a/embassy-stm32/src/low_power.rs
+++ b/embassy-stm32/src/low_power.rs
@@ -88,7 +88,7 @@ foreach_interrupt! {
         #[interrupt]
         #[allow(non_snake_case)]
         unsafe fn $irq() {
-            Executor::on_wakeup_irq();
+            Executor::on_wakeup_irq_or_event();
         }
     };
 }
@@ -99,7 +99,7 @@ foreach_interrupt! {
         #[interrupt]
         #[allow(non_snake_case)]
         unsafe fn $irq() {
-            Executor::on_wakeup_irq();
+            Executor::on_wakeup_irq_or_event();
         }
     };
 }
@@ -164,22 +164,30 @@ impl Executor {
         }
     }
 
-    pub(crate) unsafe fn on_wakeup_irq() {
+    pub(crate) unsafe fn on_wakeup_irq_or_event() {
+        if !get_driver().is_stopped() {
+            return;
+        }
+
         critical_section::with(|cs| {
             #[cfg(stm32wlex)]
             {
-                use crate::pac::rcc::vals::Sw;
-                use crate::pac::{PWR, RCC};
-                use crate::rcc::init as init_rcc;
-
-                let extscr = PWR.extscr().read();
-                if extscr.c1stop2f() || extscr.c1stopf() {
+                let es = crate::pac::PWR.extscr().read();
+                match (es.c1stopf(), es.c1stop2f()) {
+                    (true, false) => debug!("low power: wake from STOP1"),
+                    (false, true) => debug!("low power: wake from STOP2"),
+                    (true, true) => debug!("low power: wake from STOP1 and STOP2 ???"),
+                    (false, false) => trace!("low power: stop mode not entered"),
+                };
+                crate::pac::PWR.extscr().modify(|w| {
+                    w.set_c1cssf(false);
+                });
+
+                if es.c1stop2f() || es.c1stopf() {
                     // when we wake from any stop mode we need to re-initialize the rcc
-                    while RCC.cfgr().read().sws() != Sw::MSI {}
-
-                    init_rcc(RCC_CONFIG.unwrap());
+                    crate::rcc::init(RCC_CONFIG.unwrap());
 
-                    if extscr.c1stop2f() {
+                    if es.c1stop2f() {
                         // when we wake from STOP2, we need to re-initialize the time driver
                         get_driver().init_timer(cs);
                         // reset the refcounts for STOP2 and STOP1 (initializing the time driver will increment one of them for the timer)
@@ -190,7 +198,8 @@ impl Executor {
                 }
             }
             get_driver().resume_time(cs);
-            trace!("low power: resume");
+
+            trace!("low power: resume time");
         });
     }
 
@@ -201,10 +210,8 @@ impl Executor {
     fn stop_mode(_cs: CriticalSection) -> Option<StopMode> {
         // We cannot enter standby because we will lose program state.
         if unsafe { REFCOUNT_STOP2 == 0 && REFCOUNT_STOP1 == 0 } {
-            trace!("low power: stop 2");
             Some(StopMode::Stop2)
         } else if unsafe { REFCOUNT_STOP1 == 0 } {
-            trace!("low power: stop 1");
             Some(StopMode::Stop1)
         } else {
             trace!("low power: not ready to stop (refcount_stop1: {})", unsafe {
@@ -305,9 +312,11 @@ impl Executor {
             get_driver().pause_time(cs).ok()?;
             self.configure_stop(cs, stop_mode).ok()?;
 
-            Some(())
+            Some(stop_mode)
         })
-        .map(|_| {
+        .map(|stop_mode| {
+            trace!("low power: enter stop: {}", stop_mode);
+
             #[cfg(not(feature = "low-power-debug-with-sleep"))]
             Self::get_scb().set_sleepdeep();
         });
@@ -338,20 +347,10 @@ impl Executor {
             unsafe {
                 self.inner.poll();
                 self.configure_pwr();
+                #[cfg(feature = "defmt")]
+                defmt::flush();
                 asm!("wfe");
-                #[cfg(stm32wlex)]
-                {
-                    let es = crate::pac::PWR.extscr().read();
-                    match (es.c1stopf(), es.c1stop2f()) {
-                        (true, false) => debug!("low power: wake from STOP1"),
-                        (false, true) => debug!("low power: wake from STOP2"),
-                        (true, true) => debug!("low power: wake from STOP1 and STOP2 ???"),
-                        (false, false) => trace!("low power: stop mode not entered"),
-                    };
-                    crate::pac::PWR.extscr().modify(|w| {
-                        w.set_c1cssf(false);
-                    });
-                }
+                Self::on_wakeup_irq_or_event();
             };
         }
     }
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index bb4f4f1d0..1f47f4845 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -111,7 +111,7 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
         config: Config,
         fsel: FlashSelection,
     ) -> Self {
-        rcc::enable_and_reset::<T>();
+        rcc::enable_and_reset_without_stop::<T>();
 
         while T::REGS.sr().read().busy() {}
 
@@ -403,6 +403,7 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
 
     /// Async read data, using DMA.
     pub async fn read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig) {
+        let _scoped_block_stop = T::RCC_INFO.block_stop();
         let transfer = self.start_read_transfer(transaction, buf);
         transfer.await;
     }
@@ -443,6 +444,7 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
 
     /// Async write data, using DMA.
     pub async fn write_dma(&mut self, buf: &[u8], transaction: TransferConfig) {
+        let _scoped_block_stop = T::RCC_INFO.block_stop();
         let transfer = self.start_write_transfer(transaction, buf);
         transfer.await;
     }
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 1dd634cfe..2a9a1595a 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -12,6 +12,7 @@ pub use bd::*;
 #[cfg(any(mco, mco1, mco2))]
 mod mco;
 use critical_section::CriticalSection;
+use embassy_hal_internal::{Peri, PeripheralType};
 #[cfg(any(mco, mco1, mco2))]
 pub use mco::*;
 
@@ -172,7 +173,7 @@ pub(crate) struct RccInfo {
 /// E.g. if `StopMode::Stop1` is selected, the peripheral prevents the chip from entering Stop1 mode.
 #[cfg(feature = "low-power")]
 #[allow(dead_code)]
-#[derive(Debug, Clone, Copy, PartialEq, Default)]
+#[derive(Debug, Clone, Copy, PartialEq, Default, defmt::Format)]
 pub enum StopMode {
     #[default]
     /// Peripheral prevents chip from entering Stop1 or executor will enter Stop1
@@ -381,12 +382,19 @@ pub(crate) trait StoppablePeripheral {
 }
 
 #[cfg(feature = "low-power")]
-impl<'a> StoppablePeripheral for StopMode {
+impl StoppablePeripheral for StopMode {
     fn stop_mode(&self) -> StopMode {
         *self
     }
 }
 
+impl<'a, T: StoppablePeripheral + PeripheralType> StoppablePeripheral for Peri<'a, T> {
+    #[cfg(feature = "low-power")]
+    fn stop_mode(&self) -> StopMode {
+        T::stop_mode(&self)
+    }
+}
+
 pub(crate) struct BusyPeripheral<T: StoppablePeripheral> {
     peripheral: T,
 }
@@ -490,6 +498,16 @@ pub fn enable_and_reset<T: RccPeripheral>() {
     T::RCC_INFO.enable_and_reset();
 }
 
+/// Enables and resets peripheral `T` without incrementing the stop refcount.
+///
+/// # Safety
+///
+/// Peripheral must not be in use.
+// TODO: should this be `unsafe`?
+pub fn enable_and_reset_without_stop<T: RccPeripheral>() {
+    T::RCC_INFO.enable_and_reset_without_stop();
+}
+
 /// Disables peripheral `T`.
 ///
 /// # Safety
diff --git a/embassy-stm32/src/rcc/n6.rs b/embassy-stm32/src/rcc/n6.rs
index 866851bbd..178ec57d4 100644
--- a/embassy-stm32/src/rcc/n6.rs
+++ b/embassy-stm32/src/rcc/n6.rs
@@ -1003,6 +1003,24 @@ pub(crate) unsafe fn init(config: Config) {
         p.SCB.cpacr.modify(|w| w | (3 << 20) | (3 << 22));
     }
 
+    // TODO: ugly workaround for DMA accesses until RIF is properly implemented
+    debug!("deactivating RIF");
+    const RISAF3_BASE_NS: *mut u32 = stm32_metapac::RNG.wrapping_byte_offset(0x8000) as _; // AHB3PERIPH_BASE_NS + 0x8000UL
+    const RISAF3_REG0_CFGR: *mut u32 = RISAF3_BASE_NS.wrapping_byte_offset(0x40);
+    const RISAF3_REG0_ENDR: *mut u32 = RISAF3_BASE_NS.wrapping_byte_offset(0x48);
+    const RISAF3_REG0_CIDCFGR: *mut u32 = RISAF3_BASE_NS.wrapping_byte_offset(0x4C);
+    const RISAF3_REG1_CFGR: *mut u32 = RISAF3_BASE_NS.wrapping_byte_offset(0x80);
+    const RISAF3_REG1_ENDR: *mut u32 = RISAF3_BASE_NS.wrapping_byte_offset(0x88);
+    const RISAF3_REG1_CIDCFGR: *mut u32 = RISAF3_BASE_NS.wrapping_byte_offset(0x8C);
+    unsafe {
+        *RISAF3_REG0_CIDCFGR = 0x000F000F; /* RW for everyone */
+        *RISAF3_REG0_ENDR = 0xFFFFFFFF; /* all-encompassing */
+        *RISAF3_REG0_CFGR = 0x00000101; /* enabled, secure, unprivileged for everyone */
+        *RISAF3_REG1_CIDCFGR = 0x00FF00FF; /* RW for everyone */
+        *RISAF3_REG1_ENDR = 0xFFFFFFFF; /* all-encompassing */
+        *RISAF3_REG1_CFGR = 0x00000001; /* enabled, non-secure, unprivileged*/
+    }
+
     debug!("setting power supply config");
 
     power_supply_config(config.supply_config);
@@ -1039,7 +1057,9 @@ pub(crate) unsafe fn init(config: Config) {
         i2s_ckin: None,
         ic8: None,
         ic9: None,
+        ic10: None,
         ic14: None,
+        ic15: None,
         ic17: None,
         ic20: None,
     );
diff --git a/embassy-stm32/src/sai/mod.rs b/embassy-stm32/src/sai/mod.rs
index ce4bc43c3..579c34c13 100644
--- a/embassy-stm32/src/sai/mod.rs
+++ b/embassy-stm32/src/sai/mod.rs
@@ -394,7 +394,8 @@ pub struct Config {
     pub frame_length: u16,
     pub clock_strobe: ClockStrobe,
     pub output_drive: OutputDrive,
-    pub master_clock_divider: Option<MasterClockDivider>,
+    pub master_clock_divider: MasterClockDivider,
+    pub nodiv: bool,
     pub is_high_impedance_on_inactive_slot: bool,
     pub fifo_threshold: FifoThreshold,
     pub companding: Companding,
@@ -423,7 +424,8 @@ impl Default for Config {
             frame_sync_active_level_length: word::U7(16),
             frame_sync_definition: FrameSyncDefinition::ChannelIdentification,
             frame_length: 32,
-            master_clock_divider: None,
+            master_clock_divider: MasterClockDivider::DIV1,
+            nodiv: false,
             clock_strobe: ClockStrobe::Rising,
             output_drive: OutputDrive::Immediately,
             is_high_impedance_on_inactive_slot: false,
@@ -677,8 +679,8 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
             w.set_syncen(config.sync_input.syncen());
             w.set_mono(config.stereo_mono.mono());
             w.set_outdriv(config.output_drive.outdriv());
-            w.set_mckdiv(config.master_clock_divider.unwrap_or(MasterClockDivider::DIV1));
-            w.set_nodiv(config.master_clock_divider.is_none());
+            w.set_mckdiv(config.master_clock_divider);
+            w.set_nodiv(config.nodiv);
             w.set_dmaen(true);
         });
 
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index e05131040..12086cd3a 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -4,16 +4,15 @@
 use core::default::Default;
 use core::future::poll_fn;
 use core::marker::PhantomData;
-use core::ops::{Deref, DerefMut};
+use core::slice;
 use core::task::Poll;
 
-use embassy_hal_internal::drop::OnDrop;
 use embassy_hal_internal::{Peri, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
-use sdio_host::common_cmd::{self, Resp, ResponseLen};
-use sdio_host::emmc::{EMMC, ExtCSD};
-use sdio_host::sd::{BusWidth, CIC, CID, CSD, CardCapacity, CardStatus, CurrentState, OCR, RCA, SCR, SD, SDStatus};
-use sdio_host::{Cmd, emmc_cmd, sd_cmd};
+use sdio_host::Cmd;
+use sdio_host::common_cmd::{self, R1, R2, R3, Resp, ResponseLen, Rz};
+use sdio_host::sd::{BusWidth, CardStatus};
+use sdio_host::sd_cmd::{R6, R7};
 
 #[cfg(sdmmc_v1)]
 use crate::dma::ChannelAndRequest;
@@ -22,37 +21,27 @@ use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::sdmmc::Sdmmc as RegBlock;
-use crate::rcc::{self, RccPeripheral};
+use crate::rcc::{self, RccInfo, RccPeripheral, SealedRccPeripheral};
+use crate::sdmmc::sd::Addressable;
 use crate::time::Hertz;
 use crate::{interrupt, peripherals};
 
+/// Module for SD and EMMC cards
+pub mod sd;
+
+/// Module for SDIO interface
+pub mod sdio;
+
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
     _phantom: PhantomData<T>,
 }
 
-impl<T: Instance> InterruptHandler<T> {
-    fn enable_interrupts() {
-        let regs = T::regs();
-        regs.maskr().write(|w| {
-            w.set_dcrcfailie(true);
-            w.set_dtimeoutie(true);
-            w.set_dataendie(true);
-            w.set_dbckendie(true);
-
-            #[cfg(sdmmc_v1)]
-            w.set_stbiterre(true);
-            #[cfg(sdmmc_v2)]
-            w.set_dabortie(true);
-        });
-    }
-}
-
 impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
     unsafe fn on_interrupt() {
-        T::state().wake();
-        let status = T::regs().star().read();
-        T::regs().maskr().modify(|w| {
+        T::state().waker.wake();
+        let status = T::info().regs.star().read();
+        T::info().regs.maskr().modify(|w| {
             if status.dcrcfail() {
                 w.set_dcrcfailie(false)
             }
@@ -77,6 +66,57 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
     }
 }
 
+struct U128(pub u128);
+
+trait TypedResp: Resp {
+    type Word: From<U128>;
+}
+
+impl From<U128> for () {
+    fn from(value: U128) -> Self {
+        match value.0 {
+            0 => (),
+            _ => unreachable!(),
+        }
+    }
+}
+
+impl From<U128> for u32 {
+    fn from(value: U128) -> Self {
+        unwrap!(value.0.try_into())
+    }
+}
+
+impl From<U128> for u128 {
+    fn from(value: U128) -> Self {
+        value.0
+    }
+}
+
+impl TypedResp for Rz {
+    type Word = ();
+}
+
+impl TypedResp for R1 {
+    type Word = u32;
+}
+
+impl TypedResp for R2 {
+    type Word = u128;
+}
+
+impl TypedResp for R3 {
+    type Word = u32;
+}
+
+impl TypedResp for R6 {
+    type Word = u32;
+}
+
+impl TypedResp for R7 {
+    type Word = u32;
+}
+
 /// Frequency used for SD Card initialization. Must be no higher than 400 kHz.
 const SD_INIT_FREQ: Hertz = Hertz(400_000);
 
@@ -99,54 +139,14 @@ impl Default for Signalling {
     }
 }
 
-/// Aligned data block for SDMMC transfers.
-///
-/// This is a 512-byte array, aligned to 4 bytes to satisfy DMA requirements.
-#[repr(align(4))]
-#[derive(Debug, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct DataBlock(pub [u8; 512]);
-
-impl Deref for DataBlock {
-    type Target = [u8; 512];
-
-    fn deref(&self) -> &Self::Target {
-        &self.0
-    }
+const fn slice8_mut(x: &mut [u32]) -> &mut [u8] {
+    let len = x.len() * 4;
+    unsafe { slice::from_raw_parts_mut(x.as_mut_ptr() as _, len) }
 }
 
-impl DerefMut for DataBlock {
-    fn deref_mut(&mut self) -> &mut Self::Target {
-        &mut self.0
-    }
-}
-
-/// Command Block buffer for SDMMC command transfers.
-///
-/// This is a 16-word array, exposed so that DMA commpatible memory can be used if required.
-#[derive(Debug, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct CmdBlock(pub [u32; 16]);
-
-impl CmdBlock {
-    /// Creates a new instance of CmdBlock
-    pub const fn new() -> Self {
-        Self([0u32; 16])
-    }
-}
-
-impl Deref for CmdBlock {
-    type Target = [u32; 16];
-
-    fn deref(&self) -> &Self::Target {
-        &self.0
-    }
-}
-
-impl DerefMut for CmdBlock {
-    fn deref_mut(&mut self) -> &mut Self::Target {
-        &mut self.0
-    }
+const fn slice8_ref(x: &[u32]) -> &[u8] {
+    let len = x.len() * 4;
+    unsafe { slice::from_raw_parts(x.as_ptr() as _, len) }
 }
 
 /// Errors
@@ -181,42 +181,6 @@ pub enum Error {
     StBitErr,
 }
 
-#[derive(Clone, Copy, Debug, Default)]
-/// SD Card
-pub struct Card {
-    /// The type of this card
-    pub card_type: CardCapacity,
-    /// Operation Conditions Register
-    pub ocr: OCR<SD>,
-    /// Relative Card Address
-    pub rca: u16,
-    /// Card ID
-    pub cid: CID<SD>,
-    /// Card Specific Data
-    pub csd: CSD<SD>,
-    /// SD CARD Configuration Register
-    pub scr: SCR,
-    /// SD Status
-    pub status: SDStatus,
-}
-
-#[derive(Clone, Copy, Debug, Default)]
-/// eMMC storage
-pub struct Emmc {
-    /// The capacity of this card
-    pub capacity: CardCapacity,
-    /// Operation Conditions Register
-    pub ocr: OCR<EMMC>,
-    /// Relative Card Address
-    pub rca: u16,
-    /// Card ID
-    pub cid: CID<EMMC>,
-    /// Card Specific Data
-    pub csd: CSD<EMMC>,
-    /// Extended Card Specific Data
-    pub ext_csd: ExtCSD,
-}
-
 #[repr(u8)]
 enum PowerCtrl {
     Off = 0b00,
@@ -259,6 +223,55 @@ fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(bool, u8, Hertz), Error> {
     Ok((false, clk_div, clk_f))
 }
 
+fn bus_width_vals(bus_width: BusWidth) -> (u8, u32) {
+    match bus_width {
+        BusWidth::One => (0, 1u32),
+        BusWidth::Four => (1, 4u32),
+        BusWidth::Eight => (2, 8u32),
+        _ => panic!("Invalid Bus Width"),
+    }
+}
+
+#[repr(u8)]
+enum BlockSize {
+    Size1 = 0b0000,
+    Size2 = 0b0001,
+    Size4 = 0b0010,
+    Size8 = 0b0011,
+    Size16 = 0b0100,
+    Size32 = 0b0101,
+    Size64 = 0b0110,
+    Size128 = 0b0111,
+    Size256 = 0b1000,
+    Size512 = 0b1001,
+    Size1024 = 0b1010,
+    Size2048 = 0b1011,
+    Size4096 = 0b1100,
+    Size8192 = 0b1101,
+    Size16384 = 0b1110,
+}
+
+const fn block_size(bytes: usize) -> BlockSize {
+    match bytes {
+        1 => BlockSize::Size1,
+        2 => BlockSize::Size2,
+        4 => BlockSize::Size4,
+        8 => BlockSize::Size8,
+        16 => BlockSize::Size16,
+        32 => BlockSize::Size32,
+        64 => BlockSize::Size64,
+        128 => BlockSize::Size128,
+        256 => BlockSize::Size256,
+        512 => BlockSize::Size512,
+        1024 => BlockSize::Size1024,
+        2048 => BlockSize::Size2048,
+        4096 => BlockSize::Size4096,
+        8192 => BlockSize::Size8192,
+        16384 => BlockSize::Size16384,
+        _ => core::unreachable!(),
+    }
+}
+
 /// Calculate clock divisor. Returns a SDMMC_CK less than or equal to
 /// `sdmmc_ck` in Hertz.
 ///
@@ -286,6 +299,34 @@ struct Transfer<'a> {
     _dummy: PhantomData<&'a ()>,
 }
 
+struct WrappedTransfer<'a> {
+    _transfer: Transfer<'a>,
+    sdmmc: &'a Sdmmc<'a>,
+    defused: bool,
+}
+
+impl<'a> WrappedTransfer<'a> {
+    pub const fn new(_transfer: Transfer<'a>, sdmmc: &'a Sdmmc) -> Self {
+        Self {
+            _transfer,
+            sdmmc,
+            defused: false,
+        }
+    }
+
+    pub fn defuse(&mut self) {
+        self.defused = true;
+    }
+}
+
+impl<'a> Drop for WrappedTransfer<'a> {
+    fn drop(&mut self) {
+        if !self.defused {
+            self.sdmmc.on_drop();
+        }
+    }
+}
+
 #[cfg(all(sdmmc_v1, dma))]
 const DMA_TRANSFER_OPTIONS: crate::dma::TransferOptions = crate::dma::TransferOptions {
     pburst: crate::dma::Burst::Incr4,
@@ -323,64 +364,11 @@ impl Default for Config {
     }
 }
 
-/// Peripheral that can be operated over SDMMC
-#[derive(Clone, Copy, Debug)]
-pub enum SdmmcPeripheral {
-    /// SD Card
-    SdCard(Card),
-    /// eMMC memory
-    Emmc(Emmc),
-}
-
-impl SdmmcPeripheral {
-    /// Get this peripheral's address on the SDMMC bus
-    fn get_address(&self) -> u16 {
-        match self {
-            Self::SdCard(c) => c.rca,
-            Self::Emmc(e) => e.rca,
-        }
-    }
-    /// Is this a standard or high capacity peripheral?
-    fn get_capacity(&self) -> CardCapacity {
-        match self {
-            Self::SdCard(c) => c.card_type,
-            Self::Emmc(e) => e.capacity,
-        }
-    }
-    /// Size in bytes
-    fn size(&self) -> u64 {
-        match self {
-            // SDHC / SDXC / SDUC
-            Self::SdCard(c) => u64::from(c.csd.block_count()) * 512,
-            // capacity > 2GB
-            Self::Emmc(e) => u64::from(e.ext_csd.sector_count()) * 512,
-        }
-    }
-
-    /// Get a mutable reference to the SD Card.
-    ///
-    /// Panics if there is another peripheral instead.
-    fn get_sd_card(&mut self) -> &mut Card {
-        match *self {
-            Self::SdCard(ref mut c) => c,
-            _ => unreachable!("SD only"),
-        }
-    }
-
-    /// Get a mutable reference to the eMMC.
-    ///
-    /// Panics if there is another peripheral instead.
-    fn get_emmc(&mut self) -> &mut Emmc {
-        match *self {
-            Self::Emmc(ref mut e) => e,
-            _ => unreachable!("eMMC only"),
-        }
-    }
-}
-
 /// Sdmmc device
-pub struct Sdmmc<'d, T: Instance> {
-    _peri: Peri<'d, T>,
+pub struct Sdmmc<'d> {
+    info: &'static Info,
+    state: &'static State,
+    ker_clk: Hertz,
     #[cfg(sdmmc_v1)]
     dma: ChannelAndRequest<'d>,
 
@@ -400,12 +388,6 @@ pub struct Sdmmc<'d, T: Instance> {
     clock: Hertz,
     /// Current signalling scheme to card
     signalling: Signalling,
-    /// Card
-    card: Option<SdmmcPeripheral>,
-
-    /// An optional buffer to be used for commands
-    /// This should be used if there are special memory location requirements for dma
-    cmd_block: Option<&'d mut CmdBlock>,
 }
 
 const CLK_AF: AfType = AfType::output(OutputType::PushPull, Speed::VeryHigh);
@@ -416,9 +398,9 @@ const CMD_AF: AfType = AfType::output_pull(OutputType::PushPull, Speed::VeryHigh
 const DATA_AF: AfType = CMD_AF;
 
 #[cfg(sdmmc_v1)]
-impl<'d, T: Instance> Sdmmc<'d, T> {
+impl<'d> Sdmmc<'d> {
     /// Create a new SDMMC driver, with 1 data lane.
-    pub fn new_1bit(
+    pub fn new_1bit<T: Instance>(
         sdmmc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         dma: Peri<'d, impl SdmmcDma<T>>,
@@ -451,7 +433,7 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
     }
 
     /// Create a new SDMMC driver, with 4 data lanes.
-    pub fn new_4bit(
+    pub fn new_4bit<T: Instance>(
         sdmmc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         dma: Peri<'d, impl SdmmcDma<T>>,
@@ -491,9 +473,9 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 }
 
 #[cfg(sdmmc_v1)]
-impl<'d, T: Instance> Sdmmc<'d, T> {
+impl<'d> Sdmmc<'d> {
     /// Create a new SDMMC driver, with 8 data lanes.
-    pub fn new_8bit(
+    pub fn new_8bit<T: Instance>(
         sdmmc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         dma: Peri<'d, impl SdmmcDma<T>>,
@@ -541,9 +523,9 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 }
 
 #[cfg(sdmmc_v2)]
-impl<'d, T: Instance> Sdmmc<'d, T> {
+impl<'d> Sdmmc<'d> {
     /// Create a new SDMMC driver, with 1 data lane.
-    pub fn new_1bit(
+    pub fn new_1bit<T: Instance>(
         sdmmc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         clk: Peri<'d, impl CkPin<T>>,
@@ -574,7 +556,7 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
     }
 
     /// Create a new SDMMC driver, with 4 data lanes.
-    pub fn new_4bit(
+    pub fn new_4bit<T: Instance>(
         sdmmc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         clk: Peri<'d, impl CkPin<T>>,
@@ -612,9 +594,9 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 }
 
 #[cfg(sdmmc_v2)]
-impl<'d, T: Instance> Sdmmc<'d, T> {
+impl<'d> Sdmmc<'d> {
     /// Create a new SDMMC driver, with 8 data lanes.
-    pub fn new_8bit(
+    pub fn new_8bit<T: Instance>(
         sdmmc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         clk: Peri<'d, impl CkPin<T>>,
@@ -659,9 +641,24 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
     }
 }
 
-impl<'d, T: Instance> Sdmmc<'d, T> {
-    fn new_inner(
-        sdmmc: Peri<'d, T>,
+impl<'d> Sdmmc<'d> {
+    fn enable_interrupts(&self) {
+        let regs = self.info.regs;
+        regs.maskr().write(|w| {
+            w.set_dcrcfailie(true);
+            w.set_dtimeoutie(true);
+            w.set_dataendie(true);
+            w.set_dbckendie(true);
+
+            #[cfg(sdmmc_v1)]
+            w.set_stbiterre(true);
+            #[cfg(sdmmc_v2)]
+            w.set_dabortie(true);
+        });
+    }
+
+    fn new_inner<T: Instance>(
+        _sdmmc: Peri<'d, T>,
         #[cfg(sdmmc_v1)] dma: ChannelAndRequest<'d>,
         clk: Peri<'d, AnyPin>,
         cmd: Peri<'d, AnyPin>,
@@ -675,13 +672,16 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         d7: Option<Peri<'d, AnyPin>>,
         config: Config,
     ) -> Self {
-        rcc::enable_and_reset::<T>();
+        rcc::enable_and_reset_without_stop::<T>();
 
         T::Interrupt::unpend();
         unsafe { T::Interrupt::enable() };
 
-        let regs = T::regs();
-        regs.clkcr().write(|w| {
+        let info = T::info();
+        let state = T::state();
+        let ker_clk = T::frequency();
+
+        info.regs.clkcr().write(|w| {
             w.set_pwrsav(false);
             w.set_negedge(false);
 
@@ -698,10 +698,12 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
         // Power off, writen 00: Clock to the card is stopped;
         // D[7:0], CMD, and CK are driven high.
-        regs.power().modify(|w| w.set_pwrctrl(PowerCtrl::Off as u8));
+        info.regs.power().modify(|w| w.set_pwrctrl(PowerCtrl::Off as u8));
 
         Self {
-            _peri: sdmmc,
+            info,
+            state,
+            ker_clk,
             #[cfg(sdmmc_v1)]
             dma,
 
@@ -719,15 +721,13 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             config,
             clock: SD_INIT_FREQ,
             signalling: Default::default(),
-            card: None,
-            cmd_block: None,
         }
     }
 
     /// Data transfer is in progress
     #[inline]
-    fn data_active() -> bool {
-        let regs = T::regs();
+    fn data_active(&self) -> bool {
+        let regs = self.info.regs;
 
         let status = regs.star().read();
         #[cfg(sdmmc_v1)]
@@ -738,8 +738,8 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
     /// Coammand transfer is in progress
     #[inline]
-    fn cmd_active() -> bool {
-        let regs = T::regs();
+    fn cmd_active(&self) -> bool {
+        let regs = self.info.regs;
 
         let status = regs.star().read();
         #[cfg(sdmmc_v1)]
@@ -750,8 +750,16 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
     /// Wait idle on CMDACT, RXACT and TXACT (v1) or DOSNACT and CPSMACT (v2)
     #[inline]
-    fn wait_idle() {
-        while Self::data_active() || Self::cmd_active() {}
+    fn wait_idle(&self) {
+        while self.data_active() || self.cmd_active() {}
+    }
+
+    fn bus_width(&self) -> BusWidth {
+        match (self.d3.is_some(), self.d7.is_some()) {
+            (true, true) => BusWidth::Eight,
+            (true, false) => BusWidth::Four,
+            _ => BusWidth::One,
+        }
     }
 
     /// # Safety
@@ -759,23 +767,25 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
     /// `buffer` must be valid for the whole transfer and word aligned
     #[allow(unused_variables)]
     fn prepare_datapath_read<'a>(
-        config: &Config,
-        #[cfg(sdmmc_v1)] dma: &'a mut ChannelAndRequest<'d>,
+        &'a self,
         buffer: &'a mut [u32],
-        length_bytes: u32,
-        block_size: u8,
-    ) -> Transfer<'a> {
-        assert!(block_size <= 14, "Block size up to 2^14 bytes");
-        let regs = T::regs();
+        block_size: BlockSize,
+        byte_mode: bool,
+    ) -> WrappedTransfer<'a> {
+        let regs = self.info.regs;
 
         // Command AND Data state machines must be idle
-        Self::wait_idle();
-        Self::clear_interrupt_flags();
+        self.wait_idle();
+        self.clear_interrupt_flags();
 
-        regs.dlenr().write(|w| w.set_datalength(length_bytes));
+        regs.dlenr().write(|w| w.set_datalength(size_of_val(buffer) as u32));
 
+        // SAFETY: No other functions use the dma
         #[cfg(sdmmc_v1)]
-        let transfer = unsafe { dma.read(regs.fifor().as_ptr() as *mut u32, buffer, DMA_TRANSFER_OPTIONS) };
+        let transfer = unsafe {
+            self.dma
+                .read_unchecked(regs.fifor().as_ptr() as *mut u32, buffer, DMA_TRANSFER_OPTIONS)
+        };
         #[cfg(sdmmc_v2)]
         let transfer = {
             regs.idmabase0r().write(|w| w.set_idmabase0(buffer.as_mut_ptr() as u32));
@@ -785,8 +795,12 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             }
         };
 
+        #[cfg(sdmmc_v2)]
+        let byte_mode = byte_mode as u8;
+
         regs.dctrl().modify(|w| {
-            w.set_dblocksize(block_size);
+            w.set_dtmode(byte_mode);
+            w.set_dblocksize(block_size as u8);
             w.set_dtdir(true);
             #[cfg(sdmmc_v1)]
             {
@@ -795,26 +809,33 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             }
         });
 
-        transfer
+        self.enable_interrupts();
+
+        WrappedTransfer::new(transfer, &self)
     }
 
     /// # Safety
     ///
     /// `buffer` must be valid for the whole transfer and word aligned
-    fn prepare_datapath_write<'a>(&'a mut self, buffer: &'a [u32], length_bytes: u32, block_size: u8) -> Transfer<'a> {
-        assert!(block_size <= 14, "Block size up to 2^14 bytes");
-        let regs = T::regs();
+    fn prepare_datapath_write<'a>(
+        &'a self,
+        buffer: &'a [u32],
+        block_size: BlockSize,
+        byte_mode: bool,
+    ) -> WrappedTransfer<'a> {
+        let regs = self.info.regs;
 
         // Command AND Data state machines must be idle
-        Self::wait_idle();
-        Self::clear_interrupt_flags();
+        self.wait_idle();
+        self.clear_interrupt_flags();
 
-        regs.dlenr().write(|w| w.set_datalength(length_bytes));
+        regs.dlenr().write(|w| w.set_datalength(size_of_val(buffer) as u32));
 
+        // SAFETY: No other functions use the dma
         #[cfg(sdmmc_v1)]
         let transfer = unsafe {
             self.dma
-                .write(buffer, regs.fifor().as_ptr() as *mut u32, DMA_TRANSFER_OPTIONS)
+                .write_unchecked(buffer, regs.fifor().as_ptr() as *mut u32, DMA_TRANSFER_OPTIONS)
         };
         #[cfg(sdmmc_v2)]
         let transfer = {
@@ -825,8 +846,12 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             }
         };
 
+        #[cfg(sdmmc_v2)]
+        let byte_mode = byte_mode as u8;
+
         regs.dctrl().modify(|w| {
-            w.set_dblocksize(block_size);
+            w.set_dtmode(byte_mode);
+            w.set_dblocksize(block_size as u8);
             w.set_dtdir(false);
             #[cfg(sdmmc_v1)]
             {
@@ -835,12 +860,14 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             }
         });
 
-        transfer
+        self.enable_interrupts();
+
+        WrappedTransfer::new(transfer, &self)
     }
 
     /// Stops the DMA datapath
-    fn stop_datapath() {
-        let regs = T::regs();
+    fn stop_datapath(&self) {
+        let regs = self.info.regs;
 
         #[cfg(sdmmc_v1)]
         regs.dctrl().modify(|w| {
@@ -851,49 +878,58 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         regs.idmactrlr().modify(|w| w.set_idmaen(false));
     }
 
+    fn init_idle(&mut self) -> Result<(), Error> {
+        let regs = self.info.regs;
+
+        self.clkcr_set_clkdiv(SD_INIT_FREQ, BusWidth::One)?;
+        regs.dtimer()
+            .write(|w| w.set_datatime(self.config.data_transfer_timeout));
+
+        regs.power().modify(|w| w.set_pwrctrl(PowerCtrl::On as u8));
+        self.cmd(common_cmd::idle(), false)
+    }
+
     /// Sets the CLKDIV field in CLKCR. Updates clock field in self
-    fn clkcr_set_clkdiv(&mut self, freq: u32, width: BusWidth) -> Result<(), Error> {
-        let regs = T::regs();
-
-        let width_u32 = match width {
-            BusWidth::One => 1u32,
-            BusWidth::Four => 4u32,
-            BusWidth::Eight => 8u32,
-            _ => panic!("Invalid Bus Width"),
-        };
+    fn clkcr_set_clkdiv(&mut self, freq: Hertz, width: BusWidth) -> Result<(), Error> {
+        let regs = self.info.regs;
 
-        let ker_ck = T::frequency();
-        let (_bypass, clkdiv, new_clock) = clk_div(ker_ck, freq)?;
+        let (widbus, width_u32) = bus_width_vals(width);
+        let (_bypass, clkdiv, new_clock) = clk_div(self.ker_clk, freq.0)?;
 
         // Enforce AHB and SDMMC_CK clock relation. See RM0433 Rev 7
         // Section 55.5.8
         let sdmmc_bus_bandwidth = new_clock.0 * width_u32;
-        assert!(ker_ck.0 > 3 * sdmmc_bus_bandwidth / 32);
+        assert!(self.ker_clk.0 > 3 * sdmmc_bus_bandwidth / 32);
         self.clock = new_clock;
 
-        // CPSMACT and DPSMACT must be 0 to set CLKDIV
-        Self::wait_idle();
+        // CPSMACT and DPSMACT must be 0 to set CLKDIV or WIDBUS
+        self.wait_idle();
         regs.clkcr().modify(|w| {
             w.set_clkdiv(clkdiv);
             #[cfg(sdmmc_v1)]
             w.set_bypass(_bypass);
+            w.set_widbus(widbus);
         });
 
         Ok(())
     }
 
+    fn get_cid(&self) -> Result<u128, Error> {
+        self.cmd(common_cmd::all_send_cid(), false) // CMD2
+    }
+
+    fn get_csd(&self, address: u16) -> Result<u128, Error> {
+        self.cmd(common_cmd::send_csd(address), false)
+    }
+
     /// Query the card status (CMD13, returns R1)
-    fn read_status<Ext>(&self, card: &SdmmcPeripheral) -> Result<CardStatus<Ext>, Error>
+    fn read_status<A: Addressable>(&self, card: &A) -> Result<CardStatus<A::Ext>, Error>
     where
-        CardStatus<Ext>: From<u32>,
+        CardStatus<A::Ext>: From<u32>,
     {
-        let regs = T::regs();
         let rca = card.get_address();
 
-        Self::cmd(common_cmd::card_status(rca, false), false)?; // CMD13
-
-        let r1 = regs.respr(0).read().cardstatus();
-        Ok(r1.into())
+        Ok(self.cmd(common_cmd::card_status(rca, false), false)?.into()) // CMD13
     }
 
     /// Select one card and place it into the _Tranfer State_
@@ -904,17 +940,23 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         // Determine Relative Card Address (RCA) of given card
         let rca = rca.unwrap_or(0);
 
-        let r = Self::cmd(common_cmd::select_card(rca), false);
-        match (r, rca) {
-            (Err(Error::Timeout), 0) => Ok(()),
-            _ => r,
+        let resp = self.cmd(common_cmd::select_card(rca), false);
+
+        if let Err(Error::Timeout) = resp
+            && rca == 0
+        {
+            return Ok(());
         }
+
+        resp?;
+
+        Ok(())
     }
 
     /// Clear flags in interrupt clear register
     #[inline]
-    fn clear_interrupt_flags() {
-        let regs = T::regs();
+    fn clear_interrupt_flags(&self) {
+        let regs = self.info.regs;
         regs.icr().write(|w| {
             w.set_ccrcfailc(true);
             w.set_dcrcfailc(true);
@@ -947,12 +989,12 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
     /// Send command to card
     #[allow(unused_variables)]
-    fn cmd<R: Resp>(cmd: Cmd<R>, data: bool) -> Result<(), Error> {
-        let regs = T::regs();
+    fn cmd<R: TypedResp>(&self, cmd: Cmd<R>, data: bool) -> Result<R::Word, Error> {
+        let regs = self.info.regs;
 
-        Self::clear_interrupt_flags();
+        self.clear_interrupt_flags();
         // CP state machine must be idle
-        while Self::cmd_active() {}
+        while self.cmd_active() {}
 
         // Command arg
         regs.argr().write(|w| w.set_cmdarg(cmd.arg));
@@ -994,16 +1036,29 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         } else if status.ccrcfail() {
             return Err(Error::Crc);
         }
-        Ok(())
+
+        Ok(match R::LENGTH {
+            ResponseLen::Zero => U128(0u128),
+            ResponseLen::R48 => U128(self.info.regs.respr(0).read().cardstatus() as u128),
+            ResponseLen::R136 => {
+                let cid0 = self.info.regs.respr(0).read().cardstatus() as u128;
+                let cid1 = self.info.regs.respr(1).read().cardstatus() as u128;
+                let cid2 = self.info.regs.respr(2).read().cardstatus() as u128;
+                let cid3 = self.info.regs.respr(3).read().cardstatus() as u128;
+
+                U128((cid0 << 96) | (cid1 << 64) | (cid2 << 32) | (cid3))
+            }
+        }
+        .into())
     }
 
-    fn on_drop() {
-        let regs = T::regs();
-        if Self::data_active() {
-            Self::clear_interrupt_flags();
+    fn on_drop(&self) {
+        let regs = self.info.regs;
+        if self.data_active() {
+            self.clear_interrupt_flags();
             // Send abort
             // CP state machine must be idle
-            while Self::cmd_active() {}
+            while self.cmd_active() {}
 
             // Command arg
             regs.argr().write(|w| w.set_cmdarg(0));
@@ -1023,22 +1078,22 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             });
 
             // Wait for the abort
-            while Self::data_active() {}
+            while self.data_active() {}
         }
         regs.maskr().write(|_| ()); // disable irqs
-        Self::clear_interrupt_flags();
-        Self::stop_datapath();
+        self.clear_interrupt_flags();
+        self.stop_datapath();
     }
 
     /// Wait for a previously started datapath transfer to complete from an interrupt.
     #[inline]
     #[allow(unused)]
-    async fn complete_datapath_transfer(block: bool) -> Result<(), Error> {
+    async fn complete_datapath_transfer(&self, mut transfer: WrappedTransfer<'_>, block: bool) -> Result<(), Error> {
         let res = poll_fn(|cx| {
             // Compiler might not be sufficiently constrained here
             // https://github.com/embassy-rs/embassy/issues/4723
-            T::state().register(cx.waker());
-            let status = T::regs().star().read();
+            self.state.waker.register(cx.waker());
+            let status = self.info.regs.star().read();
 
             if status.dcrcfail() {
                 return Poll::Ready(Err(Error::Crc));
@@ -1067,698 +1122,25 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         })
         .await;
 
-        Self::clear_interrupt_flags();
-
-        res
-    }
-
-    /// Read a data block.
-    #[inline]
-    pub async fn read_block(&mut self, block_idx: u32, buffer: &mut DataBlock) -> Result<(), Error> {
-        let card_capacity = self.card()?.get_capacity();
-
-        // NOTE(unsafe) DataBlock uses align 4
-        let buffer = unsafe { &mut *((&mut buffer.0) as *mut [u8; 512] as *mut [u32; 128]) };
+        self.clear_interrupt_flags();
+        self.stop_datapath();
 
-        // Always read 1 block of 512 bytes
-        // SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
-        let address = match card_capacity {
-            CardCapacity::StandardCapacity => block_idx * 512,
-            _ => block_idx,
-        };
-        Self::cmd(common_cmd::set_block_length(512), false)?; // CMD16
+        transfer.defuse();
+        drop(transfer);
 
-        let on_drop = OnDrop::new(|| Self::on_drop());
-
-        let transfer = Self::prepare_datapath_read(
-            &self.config,
-            #[cfg(sdmmc_v1)]
-            &mut self.dma,
-            buffer,
-            512,
-            9,
-        );
-        InterruptHandler::<T>::enable_interrupts();
-        Self::cmd(common_cmd::read_single_block(address), true)?;
-
-        let res = Self::complete_datapath_transfer(true).await;
-
-        if res.is_ok() {
-            on_drop.defuse();
-            Self::stop_datapath();
-            drop(transfer);
-        }
         res
     }
 
-    /// Read multiple data blocks.
-    #[inline]
-    pub async fn read_blocks(&mut self, block_idx: u32, blocks: &mut [DataBlock]) -> Result<(), Error> {
-        let card_capacity = self.card()?.get_capacity();
-
-        // NOTE(unsafe) reinterpret buffer as &mut [u32]
-        let buffer = unsafe {
-            let ptr = blocks.as_mut_ptr() as *mut u32;
-            let len = blocks.len() * 128;
-            core::slice::from_raw_parts_mut(ptr, len)
-        };
-
-        // Always read 1 block of 512 bytes
-        // SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
-        let address = match card_capacity {
-            CardCapacity::StandardCapacity => block_idx * 512,
-            _ => block_idx,
-        };
-        Self::cmd(common_cmd::set_block_length(512), false)?; // CMD16
-
-        let on_drop = OnDrop::new(|| Self::on_drop());
-
-        let transfer = Self::prepare_datapath_read(
-            &self.config,
-            #[cfg(sdmmc_v1)]
-            &mut self.dma,
-            buffer,
-            512 * blocks.len() as u32,
-            9,
-        );
-        InterruptHandler::<T>::enable_interrupts();
-
-        Self::cmd(common_cmd::read_multiple_blocks(address), true)?;
-
-        let res = Self::complete_datapath_transfer(false).await;
-
-        Self::cmd(common_cmd::stop_transmission(), false)?; // CMD12
-        Self::clear_interrupt_flags();
-
-        if res.is_ok() {
-            on_drop.defuse();
-            Self::stop_datapath();
-            drop(transfer);
-        }
-        res
-    }
-
-    /// Write a data block.
-    pub async fn write_block(&mut self, block_idx: u32, buffer: &DataBlock) -> Result<(), Error> {
-        let card = self.card.as_mut().ok_or(Error::NoCard)?;
-
-        // NOTE(unsafe) DataBlock uses align 4
-        let buffer = unsafe { &*((&buffer.0) as *const [u8; 512] as *const [u32; 128]) };
-
-        // Always read 1 block of 512 bytes
-        //  cards are byte addressed hence the blockaddress is in multiples of 512 bytes
-        let address = match card.get_capacity() {
-            CardCapacity::StandardCapacity => block_idx * 512,
-            _ => block_idx,
-        };
-        Self::cmd(common_cmd::set_block_length(512), false)?; // CMD16
-
-        let on_drop = OnDrop::new(|| Self::on_drop());
-
-        // sdmmc_v1 uses different cmd/dma order than v2, but only for writes
-        #[cfg(sdmmc_v1)]
-        Self::cmd(common_cmd::write_single_block(address), true)?;
-
-        let transfer = self.prepare_datapath_write(buffer, 512, 9);
-        InterruptHandler::<T>::enable_interrupts();
-
-        #[cfg(sdmmc_v2)]
-        Self::cmd(common_cmd::write_single_block(address), true)?;
-
-        let res = Self::complete_datapath_transfer(true).await;
-
-        match res {
-            Ok(_) => {
-                on_drop.defuse();
-                Self::stop_datapath();
-                drop(transfer);
-
-                // TODO: Make this configurable
-                let mut timeout: u32 = 0x00FF_FFFF;
-
-                let card = self.card.as_ref().unwrap();
-                while timeout > 0 {
-                    let ready_for_data = match card {
-                        SdmmcPeripheral::Emmc(_) => self.read_status::<EMMC>(card)?.ready_for_data(),
-                        SdmmcPeripheral::SdCard(_) => self.read_status::<SD>(card)?.ready_for_data(),
-                    };
-
-                    if ready_for_data {
-                        return Ok(());
-                    }
-                    timeout -= 1;
-                }
-                Err(Error::SoftwareTimeout)
-            }
-            Err(e) => Err(e),
-        }
-    }
-
-    /// Write multiple data blocks.
-    pub async fn write_blocks(&mut self, block_idx: u32, blocks: &[DataBlock]) -> Result<(), Error> {
-        let card = self.card.as_mut().ok_or(Error::NoCard)?;
-
-        // NOTE(unsafe) reinterpret buffer as &[u32]
-        let buffer = unsafe {
-            let ptr = blocks.as_ptr() as *const u32;
-            let len = blocks.len() * 128;
-            core::slice::from_raw_parts(ptr, len)
-        };
-
-        // Always read 1 block of 512 bytes
-        // SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
-        let address = match card.get_capacity() {
-            CardCapacity::StandardCapacity => block_idx * 512,
-            _ => block_idx,
-        };
-
-        Self::cmd(common_cmd::set_block_length(512), false)?; // CMD16
-
-        let block_count = blocks.len();
-
-        let on_drop = OnDrop::new(|| Self::on_drop());
-
-        #[cfg(sdmmc_v1)]
-        Self::cmd(common_cmd::write_multiple_blocks(address), true)?; // CMD25
-
-        // Setup write command
-        let transfer = self.prepare_datapath_write(buffer, 512 * block_count as u32, 9);
-        InterruptHandler::<T>::enable_interrupts();
-
-        #[cfg(sdmmc_v2)]
-        Self::cmd(common_cmd::write_multiple_blocks(address), true)?; // CMD25
-
-        let res = Self::complete_datapath_transfer(false).await;
-
-        Self::cmd(common_cmd::stop_transmission(), false)?; // CMD12
-        Self::clear_interrupt_flags();
-
-        match res {
-            Ok(_) => {
-                on_drop.defuse();
-                Self::stop_datapath();
-                drop(transfer);
-
-                // TODO: Make this configurable
-                let mut timeout: u32 = 0x00FF_FFFF;
-
-                // Try to read card status (ACMD13)
-                while timeout > 0 {
-                    match self.read_sd_status().await {
-                        Ok(_) => return Ok(()),
-                        Err(Error::Timeout) => (), // Try again
-                        Err(e) => return Err(e),
-                    }
-                    timeout -= 1;
-                }
-                Err(Error::SoftwareTimeout)
-            }
-            Err(e) => Err(e),
-        }
-    }
-
-    /// Get a reference to the initialized card
-    ///
-    /// # Errors
-    ///
-    /// Returns Error::NoCard if [`init_sd_card`](#method.init_sd_card) or
-    /// [`init_emmc`](#method.init_emmc) has not previously succeeded
-    #[inline]
-    pub fn card(&self) -> Result<&SdmmcPeripheral, Error> {
-        self.card.as_ref().ok_or(Error::NoCard)
-    }
-
     /// Get the current SDMMC bus clock
     pub fn clock(&self) -> Hertz {
         self.clock
     }
-
-    /// Set a specific cmd buffer rather than using the default stack allocated one.
-    /// This is required if stack RAM cannot be used with DMA and usually manifests
-    /// itself as an indefinite wait on a dma transfer because the dma peripheral
-    /// cannot access the memory.
-    pub fn set_cmd_block(&mut self, cmd_block: &'d mut CmdBlock) {
-        self.cmd_block = Some(cmd_block)
-    }
-
-    async fn init_internal(&mut self, freq: Hertz, mut card: SdmmcPeripheral) -> Result<(), Error> {
-        let regs = T::regs();
-        let ker_ck = T::frequency();
-
-        let bus_width = match (self.d3.is_some(), self.d7.is_some()) {
-            (true, true) => {
-                if matches!(card, SdmmcPeripheral::SdCard(_)) {
-                    return Err(Error::BusWidth);
-                }
-                BusWidth::Eight
-            }
-            (true, false) => BusWidth::Four,
-            _ => BusWidth::One,
-        };
-
-        // While the SD/SDIO card or eMMC is in identification mode,
-        // the SDMMC_CK frequency must be no more than 400 kHz.
-        let (_bypass, clkdiv, init_clock) = unwrap!(clk_div(ker_ck, SD_INIT_FREQ.0));
-        self.clock = init_clock;
-
-        // CPSMACT and DPSMACT must be 0 to set WIDBUS
-        Self::wait_idle();
-
-        regs.clkcr().modify(|w| {
-            w.set_widbus(0);
-            w.set_clkdiv(clkdiv);
-            #[cfg(sdmmc_v1)]
-            w.set_bypass(_bypass);
-        });
-        regs.dtimer()
-            .write(|w| w.set_datatime(self.config.data_transfer_timeout));
-
-        regs.power().modify(|w| w.set_pwrctrl(PowerCtrl::On as u8));
-        Self::cmd(common_cmd::idle(), false)?;
-
-        match card {
-            SdmmcPeripheral::SdCard(ref mut card) => {
-                // Check if cards supports CMD8 (with pattern)
-                Self::cmd(sd_cmd::send_if_cond(1, 0xAA), false)?;
-                let cic = CIC::from(regs.respr(0).read().cardstatus());
-
-                if cic.pattern() != 0xAA {
-                    return Err(Error::UnsupportedCardVersion);
-                }
-
-                if cic.voltage_accepted() & 1 == 0 {
-                    return Err(Error::UnsupportedVoltage);
-                }
-
-                let ocr = loop {
-                    // Signal that next command is a app command
-                    Self::cmd(common_cmd::app_cmd(0), false)?; // CMD55
-
-                    // 3.2-3.3V
-                    let voltage_window = 1 << 5;
-                    // Initialize card
-                    match Self::cmd(sd_cmd::sd_send_op_cond(true, false, true, voltage_window), false) {
-                        // ACMD41
-                        Ok(_) => (),
-                        Err(Error::Crc) => (),
-                        Err(err) => return Err(err),
-                    }
-                    let ocr: OCR<SD> = regs.respr(0).read().cardstatus().into();
-                    if !ocr.is_busy() {
-                        // Power up done
-                        break ocr;
-                    }
-                };
-
-                if ocr.high_capacity() {
-                    // Card is SDHC or SDXC or SDUC
-                    card.card_type = CardCapacity::HighCapacity;
-                } else {
-                    card.card_type = CardCapacity::StandardCapacity;
-                }
-                card.ocr = ocr;
-            }
-            SdmmcPeripheral::Emmc(ref mut emmc) => {
-                let ocr = loop {
-                    let high_voltage = 0b0 << 7;
-                    let access_mode = 0b10 << 29;
-                    let op_cond = high_voltage | access_mode | 0b1_1111_1111 << 15;
-                    // Initialize card
-                    match Self::cmd(emmc_cmd::send_op_cond(op_cond), false) {
-                        Ok(_) => (),
-                        Err(Error::Crc) => (),
-                        Err(err) => return Err(err),
-                    }
-                    let ocr: OCR<EMMC> = regs.respr(0).read().cardstatus().into();
-                    if !ocr.is_busy() {
-                        // Power up done
-                        break ocr;
-                    }
-                };
-
-                emmc.capacity = if ocr.access_mode() == 0b10 {
-                    // Card is SDHC or SDXC or SDUC
-                    CardCapacity::HighCapacity
-                } else {
-                    CardCapacity::StandardCapacity
-                };
-                emmc.ocr = ocr;
-            }
-        }
-
-        Self::cmd(common_cmd::all_send_cid(), false)?; // CMD2
-        let cid0 = regs.respr(0).read().cardstatus() as u128;
-        let cid1 = regs.respr(1).read().cardstatus() as u128;
-        let cid2 = regs.respr(2).read().cardstatus() as u128;
-        let cid3 = regs.respr(3).read().cardstatus() as u128;
-        let cid = (cid0 << 96) | (cid1 << 64) | (cid2 << 32) | (cid3);
-
-        match card {
-            SdmmcPeripheral::SdCard(ref mut card) => {
-                card.cid = cid.into();
-
-                Self::cmd(sd_cmd::send_relative_address(), false)?;
-                let rca = RCA::<SD>::from(regs.respr(0).read().cardstatus());
-                card.rca = rca.address();
-            }
-            SdmmcPeripheral::Emmc(ref mut emmc) => {
-                emmc.cid = cid.into();
-
-                emmc.rca = 1u16.into();
-                Self::cmd(emmc_cmd::assign_relative_address(emmc.rca), false)?;
-            }
-        }
-
-        Self::cmd(common_cmd::send_csd(card.get_address()), false)?;
-        let csd0 = regs.respr(0).read().cardstatus() as u128;
-        let csd1 = regs.respr(1).read().cardstatus() as u128;
-        let csd2 = regs.respr(2).read().cardstatus() as u128;
-        let csd3 = regs.respr(3).read().cardstatus() as u128;
-        let csd = (csd0 << 96) | (csd1 << 64) | (csd2 << 32) | (csd3);
-
-        self.select_card(Some(card.get_address()))?;
-
-        let bus_width = match card {
-            SdmmcPeripheral::SdCard(ref mut card) => {
-                card.csd = csd.into();
-
-                self.get_scr(card).await?;
-
-                if !card.scr.bus_width_four() {
-                    BusWidth::One
-                } else {
-                    BusWidth::Four
-                }
-            }
-            SdmmcPeripheral::Emmc(ref mut emmc) => {
-                emmc.csd = csd.into();
-
-                bus_width
-            }
-        };
-
-        // Set bus width
-        let widbus = match bus_width {
-            BusWidth::Eight => 2,
-            BusWidth::Four => 1,
-            BusWidth::One => 0,
-            _ => unreachable!(),
-        };
-
-        match card {
-            SdmmcPeripheral::SdCard(ref mut card) => {
-                let acmd_arg = match bus_width {
-                    BusWidth::Four if card.scr.bus_width_four() => 2,
-                    _ => 0,
-                };
-                Self::cmd(common_cmd::app_cmd(card.rca), false)?;
-                Self::cmd(sd_cmd::cmd6(acmd_arg), false)?;
-            }
-            SdmmcPeripheral::Emmc(_) => {
-                // Write bus width to ExtCSD byte 183
-                Self::cmd(
-                    emmc_cmd::modify_ext_csd(emmc_cmd::AccessMode::WriteByte, 183, widbus),
-                    false,
-                )?;
-
-                // Wait for ready after R1b response
-                loop {
-                    let status = self.read_status::<EMMC>(&card)?;
-
-                    if status.ready_for_data() {
-                        break;
-                    }
-                }
-            }
-        }
-
-        // CPSMACT and DPSMACT must be 0 to set WIDBUS
-        Self::wait_idle();
-
-        regs.clkcr().modify(|w| w.set_widbus(widbus));
-
-        // Set Clock
-        if freq.0 <= 25_000_000 {
-            // Final clock frequency
-            self.clkcr_set_clkdiv(freq.0, bus_width)?;
-        } else {
-            // Switch to max clock for SDR12
-            self.clkcr_set_clkdiv(25_000_000, bus_width)?;
-        }
-
-        self.card = Some(card);
-
-        match card {
-            SdmmcPeripheral::SdCard(_) => {
-                // Read status
-                self.read_sd_status().await?;
-
-                if freq.0 > 25_000_000 {
-                    // Switch to SDR25
-                    self.signalling = self.switch_signalling_mode(Signalling::SDR25).await?;
-
-                    if self.signalling == Signalling::SDR25 {
-                        // Set final clock frequency
-                        self.clkcr_set_clkdiv(freq.0, bus_width)?;
-
-                        if self.read_status::<SD>(self.card.as_ref().unwrap())?.state() != CurrentState::Transfer {
-                            return Err(Error::SignalingSwitchFailed);
-                        }
-                    }
-                }
-
-                // Read status after signalling change
-                self.read_sd_status().await?;
-            }
-            SdmmcPeripheral::Emmc(_) => {
-                self.read_ext_csd().await?;
-            }
-        }
-
-        Ok(())
-    }
-
-    /// Initializes card (if present) and sets the bus at the specified frequency.
-    ///
-    /// SD only.
-    pub async fn init_sd_card(&mut self, freq: Hertz) -> Result<(), Error> {
-        self.init_internal(freq, SdmmcPeripheral::SdCard(Card::default())).await
-    }
-
-    /// Switch mode using CMD6.
-    ///
-    /// Attempt to set a new signalling mode. The selected
-    /// signalling mode is returned. Expects the current clock
-    /// frequency to be > 12.5MHz.
-    ///
-    /// SD only.
-    async fn switch_signalling_mode(&mut self, signalling: Signalling) -> Result<Signalling, Error> {
-        let _ = self.card.as_mut().ok_or(Error::NoCard)?.get_sd_card();
-        // NB PLSS v7_10 4.3.10.4: "the use of SET_BLK_LEN command is not
-        // necessary"
-
-        let set_function = 0x8000_0000
-            | match signalling {
-                // See PLSS v7_10 Table 4-11
-                Signalling::DDR50 => 0xFF_FF04,
-                Signalling::SDR104 => 0xFF_1F03,
-                Signalling::SDR50 => 0xFF_1F02,
-                Signalling::SDR25 => 0xFF_FF01,
-                Signalling::SDR12 => 0xFF_FF00,
-            };
-
-        let status = match self.cmd_block.as_deref_mut() {
-            Some(x) => x,
-            None => &mut CmdBlock::new(),
-        };
-
-        // Arm `OnDrop` after the buffer, so it will be dropped first
-        let on_drop = OnDrop::new(|| Self::on_drop());
-
-        let transfer = Self::prepare_datapath_read(
-            &self.config,
-            #[cfg(sdmmc_v1)]
-            &mut self.dma,
-            status.as_mut(),
-            64,
-            6,
-        );
-        InterruptHandler::<T>::enable_interrupts();
-        Self::cmd(sd_cmd::cmd6(set_function), true)?; // CMD6
-
-        let res = Self::complete_datapath_transfer(true).await;
-
-        // Host is allowed to use the new functions at least 8
-        // clocks after the end of the switch command
-        // transaction. We know the current clock period is < 80ns,
-        // so a total delay of 640ns is required here
-        for _ in 0..300 {
-            cortex_m::asm::nop();
-        }
-
-        match res {
-            Ok(_) => {
-                on_drop.defuse();
-                Self::stop_datapath();
-                drop(transfer);
-
-                // Function Selection of Function Group 1
-                let selection = (u32::from_be(status[4]) >> 24) & 0xF;
-
-                match selection {
-                    0 => Ok(Signalling::SDR12),
-                    1 => Ok(Signalling::SDR25),
-                    2 => Ok(Signalling::SDR50),
-                    3 => Ok(Signalling::SDR104),
-                    4 => Ok(Signalling::DDR50),
-                    _ => Err(Error::UnsupportedCardType),
-                }
-            }
-            Err(e) => Err(e),
-        }
-    }
-
-    /// Reads the SCR register.
-    ///
-    /// SD only.
-    async fn get_scr(&mut self, card: &mut Card) -> Result<(), Error> {
-        // Read the 64-bit SCR register
-        Self::cmd(common_cmd::set_block_length(8), false)?; // CMD16
-        Self::cmd(common_cmd::app_cmd(card.rca), false)?;
-
-        let cmd_block = match self.cmd_block.as_deref_mut() {
-            Some(x) => x,
-            None => &mut CmdBlock::new(),
-        };
-        let scr = &mut cmd_block.0[..2];
-
-        // Arm `OnDrop` after the buffer, so it will be dropped first
-        let on_drop = OnDrop::new(|| Self::on_drop());
-
-        let transfer = Self::prepare_datapath_read(
-            &self.config,
-            #[cfg(sdmmc_v1)]
-            &mut self.dma,
-            scr,
-            8,
-            3,
-        );
-        InterruptHandler::<T>::enable_interrupts();
-        Self::cmd(sd_cmd::send_scr(), true)?;
-
-        let res = Self::complete_datapath_transfer(true).await;
-
-        if res.is_ok() {
-            on_drop.defuse();
-            Self::stop_datapath();
-            drop(transfer);
-
-            unsafe {
-                let scr_bytes = &*(&scr as *const _ as *const [u8; 8]);
-                card.scr = SCR(u64::from_be_bytes(*scr_bytes));
-            }
-        }
-        res
-    }
-
-    /// Reads the SD Status (ACMD13)
-    ///
-    /// SD only.
-    async fn read_sd_status(&mut self) -> Result<(), Error> {
-        let card = self.card.as_mut().ok_or(Error::NoCard)?.get_sd_card();
-        let rca = card.rca;
-
-        let cmd_block = match self.cmd_block.as_deref_mut() {
-            Some(x) => x,
-            None => &mut CmdBlock::new(),
-        };
-
-        Self::cmd(common_cmd::set_block_length(64), false)?; // CMD16
-        Self::cmd(common_cmd::app_cmd(rca), false)?; // APP
-
-        let status = cmd_block;
-
-        // Arm `OnDrop` after the buffer, so it will be dropped first
-        let on_drop = OnDrop::new(|| Self::on_drop());
-
-        let transfer = Self::prepare_datapath_read(
-            &self.config,
-            #[cfg(sdmmc_v1)]
-            &mut self.dma,
-            status.as_mut(),
-            64,
-            6,
-        );
-        InterruptHandler::<T>::enable_interrupts();
-        Self::cmd(sd_cmd::sd_status(), true)?;
-
-        let res = Self::complete_datapath_transfer(true).await;
-
-        if res.is_ok() {
-            on_drop.defuse();
-            Self::stop_datapath();
-            drop(transfer);
-
-            for byte in status.iter_mut() {
-                *byte = u32::from_be(*byte);
-            }
-            card.status = status.0.into();
-        }
-        res
-    }
-
-    /// Initializes eMMC and sets the bus at the specified frequency.
-    ///
-    /// eMMC only.
-    pub async fn init_emmc(&mut self, freq: Hertz) -> Result<(), Error> {
-        self.init_internal(freq, SdmmcPeripheral::Emmc(Emmc::default())).await
-    }
-
-    /// Gets the EXT_CSD register.
-    ///
-    /// eMMC only.
-    async fn read_ext_csd(&mut self) -> Result<(), Error> {
-        let card = self.card.as_mut().ok_or(Error::NoCard)?.get_emmc();
-
-        // Note: cmd_block can't be used because ExtCSD is too long to fit.
-        let mut data_block = DataBlock([0u8; 512]);
-
-        // NOTE(unsafe) DataBlock uses align 4
-        let buffer = unsafe { &mut *((&mut data_block.0) as *mut [u8; 512] as *mut [u32; 128]) };
-
-        Self::cmd(common_cmd::set_block_length(512), false).unwrap(); // CMD16
-
-        // Arm `OnDrop` after the buffer, so it will be dropped first
-        let on_drop = OnDrop::new(|| Self::on_drop());
-
-        let transfer = Self::prepare_datapath_read(
-            &self.config,
-            #[cfg(sdmmc_v1)]
-            &mut self.dma,
-            buffer,
-            512,
-            9,
-        );
-        InterruptHandler::<T>::enable_interrupts();
-        Self::cmd(emmc_cmd::send_ext_csd(), true)?;
-
-        let res = Self::complete_datapath_transfer(true).await;
-
-        if res.is_ok() {
-            on_drop.defuse();
-            Self::stop_datapath();
-            drop(transfer);
-
-            card.ext_csd = unsafe { core::mem::transmute::<_, [u32; 128]>(data_block.0) }.into();
-        }
-        res
-    }
 }
 
-impl<'d, T: Instance> Drop for Sdmmc<'d, T> {
+impl<'d> Drop for Sdmmc<'d> {
     fn drop(&mut self) {
-        T::Interrupt::disable();
-        Self::on_drop();
+        // T::Interrupt::disable();
+        self.on_drop();
 
         critical_section::with(|_| {
             self.clk.set_as_disconnected();
@@ -1791,9 +1173,28 @@ impl<'d, T: Instance> Drop for Sdmmc<'d, T> {
 
 //////////////////////////////////////////////////////
 
+type Regs = RegBlock;
+
+struct Info {
+    regs: Regs,
+    rcc: RccInfo,
+}
+
+struct State {
+    waker: AtomicWaker,
+}
+
+impl State {
+    const fn new() -> Self {
+        Self {
+            waker: AtomicWaker::new(),
+        }
+    }
+}
+
 trait SealedInstance {
-    fn regs() -> RegBlock;
-    fn state() -> &'static AtomicWaker;
+    fn info() -> &'static Info;
+    fn state() -> &'static State;
 }
 
 /// SDMMC instance trait.
@@ -1820,13 +1221,17 @@ dma_trait!(SdmmcDma, Instance);
 foreach_peripheral!(
     (sdmmc, $inst:ident) => {
         impl SealedInstance for peripherals::$inst {
-            fn regs() -> RegBlock {
-                crate::pac::$inst
+            fn info() -> &'static Info {
+                static INFO: Info = Info {
+                    regs: unsafe { Regs::from_ptr(crate::pac::$inst.as_ptr()) },
+                    rcc: crate::peripherals::$inst::RCC_INFO,
+                };
+                &INFO
             }
 
-            fn state() -> &'static ::embassy_sync::waitqueue::AtomicWaker {
-                static WAKER: ::embassy_sync::waitqueue::AtomicWaker = ::embassy_sync::waitqueue::AtomicWaker::new();
-                &WAKER
+            fn state() -> &'static State {
+                static STATE: State = State::new();
+                &STATE
             }
         }
 
@@ -1835,46 +1240,3 @@ foreach_peripheral!(
         }
     };
 );
-
-impl<'d, T: Instance> block_device_driver::BlockDevice<512> for Sdmmc<'d, T> {
-    type Error = Error;
-    type Align = aligned::A4;
-
-    async fn read(
-        &mut self,
-        block_address: u32,
-        buf: &mut [aligned::Aligned<Self::Align, [u8; 512]>],
-    ) -> Result<(), Self::Error> {
-        // TODO: I think block_address needs to be adjusted by the partition start offset
-        if buf.len() == 1 {
-            let block = unsafe { &mut *(&mut buf[0] as *mut _ as *mut crate::sdmmc::DataBlock) };
-            self.read_block(block_address, block).await?;
-        } else {
-            let blocks: &mut [DataBlock] =
-                unsafe { core::slice::from_raw_parts_mut(buf.as_mut_ptr() as *mut DataBlock, buf.len()) };
-            self.read_blocks(block_address, blocks).await?;
-        }
-        Ok(())
-    }
-
-    async fn write(
-        &mut self,
-        block_address: u32,
-        buf: &[aligned::Aligned<Self::Align, [u8; 512]>],
-    ) -> Result<(), Self::Error> {
-        // TODO: I think block_address needs to be adjusted by the partition start offset
-        if buf.len() == 1 {
-            let block = unsafe { &*(&buf[0] as *const _ as *const crate::sdmmc::DataBlock) };
-            self.write_block(block_address, block).await?;
-        } else {
-            let blocks: &[DataBlock] =
-                unsafe { core::slice::from_raw_parts(buf.as_ptr() as *const DataBlock, buf.len()) };
-            self.write_blocks(block_address, blocks).await?;
-        }
-        Ok(())
-    }
-
-    async fn size(&mut self) -> Result<u64, Self::Error> {
-        Ok(self.card()?.size())
-    }
-}
diff --git a/embassy-stm32/src/sdmmc/sd.rs b/embassy-stm32/src/sdmmc/sd.rs
new file mode 100644
index 000000000..6190226b8
--- /dev/null
+++ b/embassy-stm32/src/sdmmc/sd.rs
@@ -0,0 +1,693 @@
+use core::default::Default;
+use core::ops::{Deref, DerefMut};
+
+use sdio_host::emmc::{EMMC, ExtCSD};
+use sdio_host::sd::{BusWidth, CIC, CID, CSD, CardCapacity, CardStatus, CurrentState, OCR, RCA, SCR, SD, SDStatus};
+use sdio_host::{common_cmd, emmc_cmd, sd_cmd};
+
+use crate::sdmmc::{BlockSize, Error, Sdmmc, Signalling, block_size, bus_width_vals, slice8_mut, slice8_ref};
+use crate::time::{Hertz, mhz};
+
+/// Aligned data block for SDMMC transfers.
+///
+/// This is a 512-byte array, aligned to 4 bytes to satisfy DMA requirements.
+#[repr(align(4))]
+#[derive(Debug, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct DataBlock(pub [u32; 128]);
+
+impl DataBlock {
+    /// Create a new DataBlock
+    pub const fn new() -> Self {
+        DataBlock([0u32; 128])
+    }
+}
+
+impl Deref for DataBlock {
+    type Target = [u8; 512];
+
+    fn deref(&self) -> &Self::Target {
+        unwrap!(slice8_ref(&self.0[..]).try_into())
+    }
+}
+
+impl DerefMut for DataBlock {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        unwrap!(slice8_mut(&mut self.0[..]).try_into())
+    }
+}
+
+/// Command Block buffer for SDMMC command transfers.
+///
+/// This is a 16-word array, exposed so that DMA commpatible memory can be used if required.
+#[derive(Debug, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct CmdBlock(pub [u32; 16]);
+
+impl CmdBlock {
+    /// Creates a new instance of CmdBlock
+    pub const fn new() -> Self {
+        Self([0u32; 16])
+    }
+}
+
+impl Deref for CmdBlock {
+    type Target = [u32; 16];
+
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+
+impl DerefMut for CmdBlock {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+
+/// Represents either an SD or EMMC card
+pub trait Addressable: Sized + Clone {
+    /// Associated type
+    type Ext;
+
+    /// Get this peripheral's address on the SDMMC bus
+    fn get_address(&self) -> u16;
+
+    /// Is this a standard or high capacity peripheral?
+    fn get_capacity(&self) -> CardCapacity;
+
+    /// Size in bytes
+    fn size(&self) -> u64;
+}
+
+/// Storage Device
+pub struct StorageDevice<'a, 'b, T: Addressable> {
+    info: T,
+    /// Inner member
+    pub sdmmc: &'a mut Sdmmc<'b>,
+}
+
+/// Card Storage Device
+impl<'a, 'b> StorageDevice<'a, 'b, Card> {
+    /// Create a new SD card
+    pub async fn new_sd_card(sdmmc: &'a mut Sdmmc<'b>, cmd_block: &mut CmdBlock, freq: Hertz) -> Result<Self, Error> {
+        let mut s = Self {
+            info: Card::default(),
+            sdmmc,
+        };
+
+        s.acquire(cmd_block, freq).await?;
+
+        Ok(s)
+    }
+
+    /// Initializes the card into a known state (or at least tries to).
+    async fn acquire(&mut self, cmd_block: &mut CmdBlock, freq: Hertz) -> Result<(), Error> {
+        let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
+        let regs = self.sdmmc.info.regs;
+
+        let _bus_width = match self.sdmmc.bus_width() {
+            BusWidth::Eight => return Err(Error::BusWidth),
+            bus_width => bus_width,
+        };
+
+        // While the SD/SDIO card or eMMC is in identification mode,
+        // the SDMMC_CK frequency must be no more than 400 kHz.
+        self.sdmmc.init_idle()?;
+
+        // Check if cards supports CMD8 (with pattern)
+        self.sdmmc.cmd(sd_cmd::send_if_cond(1, 0xAA), false)?;
+        let cic = CIC::from(regs.respr(0).read().cardstatus());
+
+        if cic.pattern() != 0xAA {
+            return Err(Error::UnsupportedCardVersion);
+        }
+
+        if cic.voltage_accepted() & 1 == 0 {
+            return Err(Error::UnsupportedVoltage);
+        }
+
+        let ocr = loop {
+            // Signal that next command is a app command
+            self.sdmmc.cmd(common_cmd::app_cmd(0), false)?; // CMD55
+
+            // 3.2-3.3V
+            let voltage_window = 1 << 5;
+            // Initialize card
+            match self
+                .sdmmc
+                .cmd(sd_cmd::sd_send_op_cond(true, false, true, voltage_window), false)
+            {
+                // ACMD41
+                Ok(_) => (),
+                Err(Error::Crc) => (),
+                Err(err) => return Err(err),
+            }
+
+            let ocr: OCR<SD> = regs.respr(0).read().cardstatus().into();
+            if !ocr.is_busy() {
+                // Power up done
+                break ocr;
+            }
+        };
+
+        if ocr.high_capacity() {
+            // Card is SDHC or SDXC or SDUC
+            self.info.card_type = CardCapacity::HighCapacity;
+        } else {
+            self.info.card_type = CardCapacity::StandardCapacity;
+        }
+        self.info.ocr = ocr;
+
+        self.info.cid = self.sdmmc.get_cid()?.into();
+
+        self.sdmmc.cmd(sd_cmd::send_relative_address(), false)?;
+        let rca = RCA::<SD>::from(regs.respr(0).read().cardstatus());
+        self.info.rca = rca.address();
+
+        self.info.csd = self.sdmmc.get_csd(self.info.get_address())?.into();
+        self.sdmmc.select_card(Some(self.info.get_address()))?;
+
+        self.info.scr = self.get_scr(cmd_block).await?;
+
+        let (bus_width, acmd_arg) = if !self.info.scr.bus_width_four() {
+            (BusWidth::One, 0)
+        } else {
+            (BusWidth::Four, 2)
+        };
+
+        self.sdmmc.cmd(common_cmd::app_cmd(self.info.rca), false)?;
+        self.sdmmc.cmd(sd_cmd::cmd6(acmd_arg), false)?;
+
+        self.sdmmc.clkcr_set_clkdiv(freq.clamp(mhz(0), mhz(25)), bus_width)?;
+
+        // Read status
+        self.info.status = self.read_sd_status(cmd_block).await?;
+
+        if freq > mhz(25) {
+            // Switch to SDR25
+            self.sdmmc.signalling = self.switch_signalling_mode(cmd_block, Signalling::SDR25).await?;
+
+            if self.sdmmc.signalling == Signalling::SDR25 {
+                // Set final clock frequency
+                self.sdmmc.clkcr_set_clkdiv(freq, bus_width)?;
+
+                if self.sdmmc.read_status(&self.info)?.state() != CurrentState::Transfer {
+                    return Err(Error::SignalingSwitchFailed);
+                }
+            }
+
+            // Read status after signalling change
+            self.read_sd_status(cmd_block).await?;
+        }
+
+        Ok(())
+    }
+
+    /// Switch mode using CMD6.
+    ///
+    /// Attempt to set a new signalling mode. The selected
+    /// signalling mode is returned. Expects the current clock
+    /// frequency to be > 12.5MHz.
+    ///
+    /// SD only.
+    async fn switch_signalling_mode(
+        &self,
+        cmd_block: &mut CmdBlock,
+        signalling: Signalling,
+    ) -> Result<Signalling, Error> {
+        // NB PLSS v7_10 4.3.10.4: "the use of SET_BLK_LEN command is not
+        // necessary"
+
+        let set_function = 0x8000_0000
+            | match signalling {
+                // See PLSS v7_10 Table 4-11
+                Signalling::DDR50 => 0xFF_FF04,
+                Signalling::SDR104 => 0xFF_1F03,
+                Signalling::SDR50 => 0xFF_1F02,
+                Signalling::SDR25 => 0xFF_FF01,
+                Signalling::SDR12 => 0xFF_FF00,
+            };
+
+        let buffer = &mut cmd_block.0[..64 / 4];
+
+        let transfer = self
+            .sdmmc
+            .prepare_datapath_read(buffer, block_size(size_of_val(buffer)), false);
+
+        self.sdmmc.cmd(sd_cmd::cmd6(set_function), true)?; // CMD6
+
+        self.sdmmc.complete_datapath_transfer(transfer, true).await?;
+
+        // Host is allowed to use the new functions at least 8
+        // clocks after the end of the switch command
+        // transaction. We know the current clock period is < 80ns,
+        // so a total delay of 640ns is required here
+        for _ in 0..300 {
+            cortex_m::asm::nop();
+        }
+
+        // Function Selection of Function Group 1
+        let selection = (u32::from_be(cmd_block[4]) >> 24) & 0xF;
+
+        match selection {
+            0 => Ok(Signalling::SDR12),
+            1 => Ok(Signalling::SDR25),
+            2 => Ok(Signalling::SDR50),
+            3 => Ok(Signalling::SDR104),
+            4 => Ok(Signalling::DDR50),
+            _ => Err(Error::UnsupportedCardType),
+        }
+    }
+
+    /// Reads the SCR register.
+    ///
+    /// SD only.
+    async fn get_scr(&self, cmd_block: &mut CmdBlock) -> Result<SCR, Error> {
+        // Read the 64-bit SCR register
+        self.sdmmc.cmd(common_cmd::set_block_length(8), false)?; // CMD16
+        self.sdmmc.cmd(common_cmd::app_cmd(self.info.rca), false)?;
+
+        let scr = &mut cmd_block.0[..2];
+
+        // Arm `OnDrop` after the buffer, so it will be dropped first
+
+        let transfer = self.sdmmc.prepare_datapath_read(scr, BlockSize::Size8, false);
+        self.sdmmc.cmd(sd_cmd::send_scr(), true)?;
+
+        self.sdmmc.complete_datapath_transfer(transfer, true).await?;
+
+        Ok(SCR(u64::from_be_bytes(unwrap!(slice8_mut(scr).try_into()))))
+    }
+
+    /// Reads the SD Status (ACMD13)
+    ///
+    /// SD only.
+    async fn read_sd_status(&self, cmd_block: &mut CmdBlock) -> Result<SDStatus, Error> {
+        let rca = self.info.rca;
+
+        self.sdmmc.cmd(common_cmd::set_block_length(64), false)?; // CMD16
+        self.sdmmc.cmd(common_cmd::app_cmd(rca), false)?; // APP
+
+        let buffer = &mut cmd_block.as_mut()[..64 / 4];
+
+        let transfer = self
+            .sdmmc
+            .prepare_datapath_read(buffer, block_size(size_of_val(buffer)), false);
+        self.sdmmc.cmd(sd_cmd::sd_status(), true)?;
+
+        self.sdmmc.complete_datapath_transfer(transfer, true).await?;
+
+        for byte in cmd_block.iter_mut() {
+            *byte = u32::from_be(*byte);
+        }
+
+        Ok(cmd_block.0.into())
+    }
+}
+
+/// Emmc storage device
+impl<'a, 'b> StorageDevice<'a, 'b, Emmc> {
+    /// Create a new EMMC card
+    pub async fn new_emmc(sdmmc: &'a mut Sdmmc<'b>, cmd_block: &mut CmdBlock, freq: Hertz) -> Result<Self, Error> {
+        let mut s = Self {
+            info: Emmc::default(),
+            sdmmc,
+        };
+
+        s.acquire(cmd_block, freq).await?;
+
+        Ok(s)
+    }
+
+    async fn acquire(&mut self, _cmd_block: &mut CmdBlock, freq: Hertz) -> Result<(), Error> {
+        let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
+        let regs = self.sdmmc.info.regs;
+
+        let bus_width = self.sdmmc.bus_width();
+
+        // While the SD/SDIO card or eMMC is in identification mode,
+        // the SDMMC_CK frequency must be no more than 400 kHz.
+        self.sdmmc.init_idle()?;
+
+        let ocr = loop {
+            let high_voltage = 0b0 << 7;
+            let access_mode = 0b10 << 29;
+            let op_cond = high_voltage | access_mode | 0b1_1111_1111 << 15;
+            // Initialize card
+            match self.sdmmc.cmd(emmc_cmd::send_op_cond(op_cond), false) {
+                Ok(_) => (),
+                Err(Error::Crc) => (),
+                Err(err) => return Err(err),
+            }
+            let ocr: OCR<EMMC> = regs.respr(0).read().cardstatus().into();
+            if !ocr.is_busy() {
+                // Power up done
+                break ocr;
+            }
+        };
+
+        self.info.capacity = if ocr.access_mode() == 0b10 {
+            // Card is SDHC or SDXC or SDUC
+            CardCapacity::HighCapacity
+        } else {
+            CardCapacity::StandardCapacity
+        };
+        self.info.ocr = ocr;
+
+        self.info.cid = self.sdmmc.get_cid()?.into();
+
+        self.info.rca = 1u16.into();
+        self.sdmmc
+            .cmd(emmc_cmd::assign_relative_address(self.info.rca), false)?;
+
+        self.info.csd = self.sdmmc.get_csd(self.info.get_address())?.into();
+        self.sdmmc.select_card(Some(self.info.get_address()))?;
+
+        let (widbus, _) = bus_width_vals(bus_width);
+
+        // Write bus width to ExtCSD byte 183
+        self.sdmmc.cmd(
+            emmc_cmd::modify_ext_csd(emmc_cmd::AccessMode::WriteByte, 183, widbus),
+            false,
+        )?;
+
+        // Wait for ready after R1b response
+        loop {
+            let status = self.sdmmc.read_status(&self.info)?;
+
+            if status.ready_for_data() {
+                break;
+            }
+        }
+
+        self.sdmmc.clkcr_set_clkdiv(freq.clamp(mhz(0), mhz(25)), bus_width)?;
+        self.info.ext_csd = self.read_ext_csd().await?;
+
+        Ok(())
+    }
+
+    /// Gets the EXT_CSD register.
+    ///
+    /// eMMC only.
+    async fn read_ext_csd(&self) -> Result<ExtCSD, Error> {
+        // Note: cmd_block can't be used because ExtCSD is too long to fit.
+        let mut data_block = DataBlock::new();
+
+        self.sdmmc
+            .cmd(common_cmd::set_block_length(size_of::<DataBlock>() as u32), false)
+            .unwrap(); // CMD16
+
+        let transfer = self
+            .sdmmc
+            .prepare_datapath_read(&mut data_block.0, block_size(size_of::<DataBlock>()), false);
+        self.sdmmc.cmd(emmc_cmd::send_ext_csd(), true)?;
+
+        self.sdmmc.complete_datapath_transfer(transfer, true).await?;
+
+        Ok(data_block.0.into())
+    }
+}
+
+/// Card or Emmc storage device
+impl<'a, 'b, A: Addressable> StorageDevice<'a, 'b, A> {
+    /// Write a block
+    pub fn card(&self) -> A {
+        self.info.clone()
+    }
+
+    /// Read a data block.
+    #[inline]
+    pub async fn read_block(&mut self, block_idx: u32, buffer: &mut DataBlock) -> Result<(), Error> {
+        let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
+        let card_capacity = self.info.get_capacity();
+
+        // Always read 1 block of 512 bytes
+        // SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
+        let address = match card_capacity {
+            CardCapacity::StandardCapacity => block_idx * size_of::<DataBlock>() as u32,
+            _ => block_idx,
+        };
+        self.sdmmc
+            .cmd(common_cmd::set_block_length(size_of::<DataBlock>() as u32), false)?; // CMD16
+
+        let transfer = self
+            .sdmmc
+            .prepare_datapath_read(&mut buffer.0, block_size(size_of::<DataBlock>()), false);
+        self.sdmmc.cmd(common_cmd::read_single_block(address), true)?;
+
+        self.sdmmc.complete_datapath_transfer(transfer, true).await?;
+
+        Ok(())
+    }
+
+    /// Read multiple data blocks.
+    #[inline]
+    pub async fn read_blocks(&mut self, block_idx: u32, blocks: &mut [DataBlock]) -> Result<(), Error> {
+        let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
+        let card_capacity = self.info.get_capacity();
+
+        // NOTE(unsafe) reinterpret buffer as &mut [u32]
+        let buffer = unsafe {
+            core::slice::from_raw_parts_mut(
+                blocks.as_mut_ptr() as *mut u32,
+                blocks.len() * size_of::<DataBlock>() / size_of::<u32>(),
+            )
+        };
+
+        // Always read 1 block of 512 bytes
+        // SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
+        let address = match card_capacity {
+            CardCapacity::StandardCapacity => block_idx * size_of::<DataBlock>() as u32,
+            _ => block_idx,
+        };
+        self.sdmmc
+            .cmd(common_cmd::set_block_length(size_of::<DataBlock>() as u32), false)?; // CMD16
+
+        let transfer = self
+            .sdmmc
+            .prepare_datapath_read(buffer, block_size(size_of::<DataBlock>()), false);
+        self.sdmmc.cmd(common_cmd::read_multiple_blocks(address), true)?;
+
+        self.sdmmc.complete_datapath_transfer(transfer, false).await?;
+
+        self.sdmmc.cmd(common_cmd::stop_transmission(), false)?; // CMD12
+        self.sdmmc.clear_interrupt_flags();
+
+        Ok(())
+    }
+
+    /// Write a data block.
+    pub async fn write_block(&mut self, block_idx: u32, buffer: &DataBlock) -> Result<(), Error>
+    where
+        CardStatus<A::Ext>: From<u32>,
+    {
+        let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
+
+        // Always read 1 block of 512 bytes
+        //  cards are byte addressed hence the blockaddress is in multiples of 512 bytes
+        let address = match self.info.get_capacity() {
+            CardCapacity::StandardCapacity => block_idx * size_of::<DataBlock>() as u32,
+            _ => block_idx,
+        };
+        self.sdmmc
+            .cmd(common_cmd::set_block_length(size_of::<DataBlock>() as u32), false)?; // CMD16
+
+        // sdmmc_v1 uses different cmd/dma order than v2, but only for writes
+        #[cfg(sdmmc_v1)]
+        self.sdmmc.cmd(common_cmd::write_single_block(address), true)?;
+
+        let transfer = self
+            .sdmmc
+            .prepare_datapath_write(&buffer.0, block_size(size_of::<DataBlock>()), false);
+
+        #[cfg(sdmmc_v2)]
+        self.sdmmc.cmd(common_cmd::write_single_block(address), true)?;
+
+        self.sdmmc.complete_datapath_transfer(transfer, true).await?;
+
+        // TODO: Make this configurable
+        let mut timeout: u32 = 0x00FF_FFFF;
+
+        while timeout > 0 {
+            let ready_for_data = self.sdmmc.read_status(&self.info)?.ready_for_data();
+            if ready_for_data {
+                return Ok(());
+            }
+            timeout -= 1;
+        }
+
+        Err(Error::SoftwareTimeout)
+    }
+
+    /// Write multiple data blocks.
+    pub async fn write_blocks(&mut self, block_idx: u32, blocks: &[DataBlock]) -> Result<(), Error>
+    where
+        CardStatus<A::Ext>: From<u32>,
+    {
+        let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
+
+        // NOTE(unsafe) reinterpret buffer as &[u32]
+        let buffer = unsafe {
+            core::slice::from_raw_parts(
+                blocks.as_ptr() as *const u32,
+                blocks.len() * size_of::<DataBlock>() / size_of::<u32>(),
+            )
+        };
+        // Always read 1 block of 512 bytes
+        // SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
+        let address = match self.info.get_capacity() {
+            CardCapacity::StandardCapacity => block_idx * size_of::<DataBlock>() as u32,
+            _ => block_idx,
+        };
+
+        self.sdmmc
+            .cmd(common_cmd::set_block_length(size_of::<DataBlock>() as u32), false)?; // CMD16
+
+        #[cfg(sdmmc_v1)]
+        self.sdmmc.cmd(common_cmd::write_multiple_blocks(address), true)?; // CMD25
+
+        // Setup write command
+        let transfer = self
+            .sdmmc
+            .prepare_datapath_write(buffer, block_size(size_of::<DataBlock>()), false);
+
+        #[cfg(sdmmc_v2)]
+        self.sdmmc.cmd(common_cmd::write_multiple_blocks(address), true)?; // CMD25
+
+        self.sdmmc.complete_datapath_transfer(transfer, false).await?;
+
+        self.sdmmc.cmd(common_cmd::stop_transmission(), false)?; // CMD12
+        self.sdmmc.clear_interrupt_flags();
+
+        // TODO: Make this configurable
+        let mut timeout: u32 = 0x00FF_FFFF;
+
+        while timeout > 0 {
+            let ready_for_data = self.sdmmc.read_status(&self.info)?.ready_for_data();
+
+            if ready_for_data {
+                return Ok(());
+            }
+            timeout -= 1;
+        }
+        Err(Error::SoftwareTimeout)
+    }
+}
+
+#[derive(Clone, Copy, Debug, Default)]
+/// SD Card
+pub struct Card {
+    /// The type of this card
+    pub card_type: CardCapacity,
+    /// Operation Conditions Register
+    pub ocr: OCR<SD>,
+    /// Relative Card Address
+    pub rca: u16,
+    /// Card ID
+    pub cid: CID<SD>,
+    /// Card Specific Data
+    pub csd: CSD<SD>,
+    /// SD CARD Configuration Register
+    pub scr: SCR,
+    /// SD Status
+    pub status: SDStatus,
+}
+
+impl Addressable for Card {
+    type Ext = SD;
+
+    /// Get this peripheral's address on the SDMMC bus
+    fn get_address(&self) -> u16 {
+        self.rca
+    }
+
+    /// Is this a standard or high capacity peripheral?
+    fn get_capacity(&self) -> CardCapacity {
+        self.card_type
+    }
+
+    /// Size in bytes
+    fn size(&self) -> u64 {
+        u64::from(self.csd.block_count()) * 512
+    }
+}
+
+#[derive(Clone, Copy, Debug, Default)]
+/// eMMC storage
+pub struct Emmc {
+    /// The capacity of this card
+    pub capacity: CardCapacity,
+    /// Operation Conditions Register
+    pub ocr: OCR<EMMC>,
+    /// Relative Card Address
+    pub rca: u16,
+    /// Card ID
+    pub cid: CID<EMMC>,
+    /// Card Specific Data
+    pub csd: CSD<EMMC>,
+    /// Extended Card Specific Data
+    pub ext_csd: ExtCSD,
+}
+
+impl Addressable for Emmc {
+    type Ext = EMMC;
+
+    /// Get this peripheral's address on the SDMMC bus
+    fn get_address(&self) -> u16 {
+        self.rca
+    }
+
+    /// Is this a standard or high capacity peripheral?
+    fn get_capacity(&self) -> CardCapacity {
+        self.capacity
+    }
+
+    /// Size in bytes
+    fn size(&self) -> u64 {
+        u64::from(self.ext_csd.sector_count()) * 512
+    }
+}
+
+impl<'d, 'e, A: Addressable> block_device_driver::BlockDevice<512> for StorageDevice<'d, 'e, A> {
+    type Error = Error;
+    type Align = aligned::A4;
+
+    async fn read(
+        &mut self,
+        block_address: u32,
+        buf: &mut [aligned::Aligned<Self::Align, [u8; 512]>],
+    ) -> Result<(), Self::Error> {
+        // TODO: I think block_address needs to be adjusted by the partition start offset
+        if buf.len() == 1 {
+            let block = unsafe { &mut *(&mut buf[0] as *mut _ as *mut DataBlock) };
+            self.read_block(block_address, block).await?;
+        } else {
+            let blocks: &mut [DataBlock] =
+                unsafe { core::slice::from_raw_parts_mut(buf.as_mut_ptr() as *mut DataBlock, buf.len()) };
+            self.read_blocks(block_address, blocks).await?;
+        }
+        Ok(())
+    }
+
+    async fn write(
+        &mut self,
+        block_address: u32,
+        buf: &[aligned::Aligned<Self::Align, [u8; 512]>],
+    ) -> Result<(), Self::Error> {
+        // TODO: I think block_address needs to be adjusted by the partition start offset
+        if buf.len() == 1 {
+            let block = unsafe { &*(&buf[0] as *const _ as *const DataBlock) };
+            self.write_block(block_address, block).await?;
+        } else {
+            let blocks: &[DataBlock] =
+                unsafe { core::slice::from_raw_parts(buf.as_ptr() as *const DataBlock, buf.len()) };
+            self.write_blocks(block_address, blocks).await?;
+        }
+        Ok(())
+    }
+
+    async fn size(&mut self) -> Result<u64, Self::Error> {
+        Ok(self.info.size())
+    }
+}
diff --git a/embassy-stm32/src/sdmmc/sdio.rs b/embassy-stm32/src/sdmmc/sdio.rs
new file mode 100644
index 000000000..1412b21fc
--- /dev/null
+++ b/embassy-stm32/src/sdmmc/sdio.rs
@@ -0,0 +1,177 @@
+use core::ops::{Deref, DerefMut};
+
+use sdio_host::common_cmd::{R1, Rz, cmd};
+use sdio_host::sd::BusWidth;
+use sdio_host::sd_cmd;
+
+use crate::sdmmc::{Error, Sdmmc, block_size, slice8_mut, slice8_ref};
+use crate::time::Hertz;
+
+/// Aligned data block for SDMMC transfers.
+///
+/// This is a 64-byte array, aligned to 4 bytes to satisfy DMA requirements.
+#[repr(align(4))]
+#[derive(Debug, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct DataBlock(pub [u32; 16]);
+
+impl DataBlock {
+    /// Create a new DataBlock
+    pub const fn new() -> Self {
+        DataBlock([0u32; 16])
+    }
+}
+
+impl Deref for DataBlock {
+    type Target = [u8; 64];
+
+    fn deref(&self) -> &Self::Target {
+        unwrap!(slice8_ref(&self.0[..]).try_into())
+    }
+}
+
+impl DerefMut for DataBlock {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        unwrap!(slice8_mut(&mut self.0[..]).try_into())
+    }
+}
+
+/// Storage Device
+pub struct SerialDataInterface<'a, 'b> {
+    /// Inner member
+    pub sdmmc: &'a mut Sdmmc<'b>,
+}
+
+/// Card Storage Device
+impl<'a, 'b> SerialDataInterface<'a, 'b> {
+    /// Create a new SD card
+    pub async fn new(sdmmc: &'a mut Sdmmc<'b>, freq: Hertz) -> Result<Self, Error> {
+        let mut s = Self { sdmmc };
+
+        s.acquire(freq).await?;
+
+        Ok(s)
+    }
+
+    /// Initializes the card into a known state (or at least tries to).
+    async fn acquire(&mut self, _freq: Hertz) -> Result<(), Error> {
+        let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
+
+        let _bus_width = match self.sdmmc.bus_width() {
+            BusWidth::Eight => return Err(Error::BusWidth),
+            bus_width => bus_width,
+        };
+
+        // While the SD/SDIO card or eMMC is in identification mode,
+        // the SDMMC_CK frequency must be no more than 400 kHz.
+        self.sdmmc.init_idle()?;
+
+        self.sdmmc.cmd(cmd::<Rz>(5, 0), false)?;
+
+        // Get RCA
+        let rca = self.sdmmc.cmd(sd_cmd::send_relative_address(), false)?;
+
+        // Select the card with RCA
+        self.sdmmc.select_card(Some(rca.try_into().unwrap()))?;
+
+        Ok(())
+    }
+
+    /// Set the bus to the 4-bit high-speed frequency
+    pub fn set_bus_to_high_speed(&mut self, frequency: Hertz) -> Result<(), Error> {
+        self.sdmmc.clkcr_set_clkdiv(frequency, BusWidth::Four)?;
+
+        Ok(())
+    }
+
+    /// Run cmd52
+    pub async fn cmd52(&mut self, arg: u32) -> Result<u32, Error> {
+        self.sdmmc.cmd(cmd::<R1>(52, arg), false)
+    }
+
+    /// Read in block mode using cmd53
+    pub async fn cmd53_block_read(&mut self, arg: u32, blocks: &mut [DataBlock]) -> Result<(), Error> {
+        let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
+
+        // NOTE(unsafe) reinterpret buffer as &mut [u32]
+        let buffer = unsafe {
+            core::slice::from_raw_parts_mut(
+                blocks.as_mut_ptr() as *mut u32,
+                blocks.len() * size_of::<DataBlock>() / size_of::<u32>(),
+            )
+        };
+
+        let transfer = self
+            .sdmmc
+            .prepare_datapath_read(buffer, block_size(size_of::<DataBlock>()), false);
+        self.sdmmc.cmd(cmd::<Rz>(53, arg), true)?;
+
+        self.sdmmc.complete_datapath_transfer(transfer, false).await?;
+        self.sdmmc.clear_interrupt_flags();
+
+        Ok(())
+    }
+
+    /// Read in multibyte mode using cmd53
+    pub async fn cmd53_byte_read(&mut self, arg: u32, buffer: &mut [u32]) -> Result<(), Error> {
+        let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
+
+        let transfer = self
+            .sdmmc
+            .prepare_datapath_read(buffer, block_size(size_of::<DataBlock>()), true);
+        self.sdmmc.cmd(cmd::<Rz>(53, arg), true)?;
+
+        self.sdmmc.complete_datapath_transfer(transfer, false).await?;
+        self.sdmmc.clear_interrupt_flags();
+
+        Ok(())
+    }
+
+    /// Write in block mode using cmd53
+    pub async fn cmd53_block_write(&mut self, arg: u32, blocks: &[DataBlock]) -> Result<(), Error> {
+        let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
+
+        // NOTE(unsafe) reinterpret buffer as &mut [u32]
+        let buffer = unsafe {
+            core::slice::from_raw_parts_mut(
+                blocks.as_ptr() as *mut u32,
+                blocks.len() * size_of::<DataBlock>() / size_of::<u32>(),
+            )
+        };
+
+        #[cfg(sdmmc_v1)]
+        self.sdmmc.cmd(cmd::<Rz>(53, arg), true)?;
+
+        let transfer = self
+            .sdmmc
+            .prepare_datapath_read(buffer, block_size(size_of::<DataBlock>()), false);
+
+        #[cfg(sdmmc_v2)]
+        self.sdmmc.cmd(cmd::<Rz>(53, arg), true)?;
+
+        self.sdmmc.complete_datapath_transfer(transfer, false).await?;
+        self.sdmmc.clear_interrupt_flags();
+
+        Ok(())
+    }
+
+    /// Write in multibyte mode using cmd53
+    pub async fn cmd53_byte_write(&mut self, arg: u32, buffer: &[u32]) -> Result<(), Error> {
+        let _scoped_block_stop = self.sdmmc.info.rcc.block_stop();
+
+        #[cfg(sdmmc_v1)]
+        self.sdmmc.cmd(cmd::<Rz>(53, arg), true)?;
+
+        let transfer = self
+            .sdmmc
+            .prepare_datapath_write(buffer, block_size(size_of::<DataBlock>()), true);
+
+        #[cfg(sdmmc_v2)]
+        self.sdmmc.cmd(cmd::<Rz>(53, arg), true)?;
+
+        self.sdmmc.complete_datapath_transfer(transfer, false).await?;
+        self.sdmmc.clear_interrupt_flags();
+
+        Ok(())
+    }
+}
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index abb80ed26..c90e0cef4 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -54,6 +54,16 @@ pub enum BitOrder {
     MsbFirst,
 }
 
+/// SPI Direction.
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Direction {
+    /// Transmit
+    Transmit,
+    /// Receive
+    Receive,
+}
+
 /// SPI configuration.
 #[non_exhaustive]
 #[derive(Copy, Clone)]
@@ -72,6 +82,10 @@ pub struct Config {
     /// signal rise/fall speed (slew rate) - defaults to `Medium`.
     /// Increase for high SPI speeds. Change to `Low` to reduce ringing.
     pub gpio_speed: Speed,
+    /// If True sets SSOE to zero even if SPI is in Master Mode.
+    /// NSS output enabled (SSM = 0, SSOE = 1): The NSS signal is driven low when the master starts the communication and is kept low until the SPI is disabled.
+    /// NSS output disabled (SSM = 0, SSOE = 0): For devices set as slave, the NSS pin acts as a classical NSS input: the slave is selected when NSS is low and deselected when NSS high.
+    pub nss_output_disable: bool,
 }
 
 impl Default for Config {
@@ -82,6 +96,7 @@ impl Default for Config {
             frequency: Hertz(1_000_000),
             miso_pull: Pull::None,
             gpio_speed: Speed::VeryHigh,
+            nss_output_disable: false,
         }
     }
 }
@@ -215,13 +230,35 @@ impl<'d, M: PeriMode, CM: CommunicationMode> Spi<'d, M, CM> {
         let cpol = config.raw_polarity();
         let lsbfirst = config.raw_byte_order();
 
-        self.info.rcc.enable_and_reset();
+        self.info.rcc.enable_and_reset_without_stop();
+
+        /*
+        - Software NSS management (SSM = 1)
+        The slave select information is driven internally by the value of the SSI bit in the
+        SPI_CR1 register. The external NSS pin remains free for other application uses.
+
+        - Hardware NSS management (SSM = 0)
+        Two configurations are possible depending on the NSS output configuration (SSOE bit
+        in register SPI_CR1).
+
+        -- NSS output enabled (SSM = 0, SSOE = 1)
+          This configuration is used only when the device operates in master mode. The
+          NSS signal is driven low when the master starts the communication and is kept
+          low until the SPI is disabled.
+
+        -- NSS output disabled (SSM = 0, SSOE = 0)
+            This configuration allows multimaster capability for devices operating in master
+            mode. For devices set as slave, the NSS pin acts as a classical NSS input: the
+            slave is selected when NSS is low and deselected when NSS high
+         */
+        let ssm = self.nss.is_none();
 
         let regs = self.info.regs;
         #[cfg(any(spi_v1, spi_v2))]
         {
+            let ssoe = CM::MASTER == vals::Mstr::MASTER && !config.nss_output_disable;
             regs.cr2().modify(|w| {
-                w.set_ssoe(false);
+                w.set_ssoe(ssoe);
             });
             regs.cr1().modify(|w| {
                 w.set_cpha(cpha);
@@ -232,7 +269,7 @@ impl<'d, M: PeriMode, CM: CommunicationMode> Spi<'d, M, CM> {
                 w.set_spe(true);
                 w.set_lsbfirst(lsbfirst);
                 w.set_ssi(CM::MASTER == vals::Mstr::MASTER);
-                w.set_ssm(CM::MASTER == vals::Mstr::MASTER);
+                w.set_ssm(ssm);
                 w.set_crcen(false);
                 w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
                 // we're doing "fake rxonly", by actually writing one
@@ -244,11 +281,12 @@ impl<'d, M: PeriMode, CM: CommunicationMode> Spi<'d, M, CM> {
         }
         #[cfg(spi_v3)]
         {
+            let ssoe = CM::MASTER == vals::Mstr::MASTER && !config.nss_output_disable;
             regs.cr2().modify(|w| {
                 let (ds, frxth) = <u8 as SealedWord>::CONFIG;
                 w.set_frxth(frxth);
                 w.set_ds(ds);
-                w.set_ssoe(false);
+                w.set_ssoe(ssoe);
             });
             regs.cr1().modify(|w| {
                 w.set_cpha(cpha);
@@ -258,7 +296,7 @@ impl<'d, M: PeriMode, CM: CommunicationMode> Spi<'d, M, CM> {
                 w.set_br(br);
                 w.set_lsbfirst(lsbfirst);
                 w.set_ssi(CM::MASTER == vals::Mstr::MASTER);
-                w.set_ssm(CM::MASTER == vals::Mstr::MASTER);
+                w.set_ssm(ssm);
                 w.set_crcen(false);
                 w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
                 w.set_spe(true);
@@ -266,14 +304,14 @@ impl<'d, M: PeriMode, CM: CommunicationMode> Spi<'d, M, CM> {
         }
         #[cfg(any(spi_v4, spi_v5, spi_v6))]
         {
+            let ssoe = CM::MASTER == vals::Master::MASTER && !config.nss_output_disable;
             regs.ifcr().write(|w| w.0 = 0xffff_ffff);
             regs.cfg2().modify(|w| {
-                //w.set_ssoe(true);
-                w.set_ssoe(false);
+                w.set_ssoe(ssoe);
                 w.set_cpha(cpha);
                 w.set_cpol(cpol);
                 w.set_lsbfirst(lsbfirst);
-                w.set_ssm(CM::MASTER == vals::Master::MASTER);
+                w.set_ssm(ssm);
                 w.set_master(CM::MASTER);
                 w.set_comm(vals::Comm::FULL_DUPLEX);
                 w.set_ssom(vals::Ssom::ASSERTED);
@@ -348,6 +386,20 @@ impl<'d, M: PeriMode, CM: CommunicationMode> Spi<'d, M, CM> {
         Ok(())
     }
 
+    /// Set SPI direction
+    #[cfg(any(spi_v1, spi_v2, spi_v3))]
+    pub fn set_direction(&mut self, dir: Option<Direction>) {
+        let (bidimode, bidioe) = match dir {
+            Some(Direction::Transmit) => (vals::Bidimode::BIDIRECTIONAL, vals::Bidioe::TRANSMIT),
+            Some(Direction::Receive) => (vals::Bidimode::BIDIRECTIONAL, vals::Bidioe::RECEIVE),
+            None => (vals::Bidimode::UNIDIRECTIONAL, vals::Bidioe::TRANSMIT),
+        };
+        self.info.regs.cr1().modify(|w| {
+            w.set_bidimode(bidimode);
+            w.set_bidioe(bidioe);
+        });
+    }
+
     /// Get current SPI configuration.
     pub fn get_current_config(&self) -> Config {
         #[cfg(any(spi_v1, spi_v2, spi_v3))]
@@ -357,6 +409,11 @@ impl<'d, M: PeriMode, CM: CommunicationMode> Spi<'d, M, CM> {
         #[cfg(any(spi_v4, spi_v5, spi_v6))]
         let cfg1 = self.info.regs.cfg1().read();
 
+        #[cfg(any(spi_v1, spi_v2, spi_v3))]
+        let ssoe = self.info.regs.cr2().read().ssoe();
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
+        let ssoe = cfg.ssoe();
+
         let polarity = if cfg.cpol() == vals::Cpol::IDLE_LOW {
             Polarity::IdleLow
         } else {
@@ -386,12 +443,16 @@ impl<'d, M: PeriMode, CM: CommunicationMode> Spi<'d, M, CM> {
 
         let frequency = compute_frequency(self.kernel_clock, br);
 
+        // NSS output disabled if SSOE=0 or if SSM=1 software slave management enabled
+        let nss_output_disable = !ssoe || cfg.ssm();
+
         Config {
             mode: Mode { polarity, phase },
             bit_order,
             frequency,
             miso_pull,
             gpio_speed: self.gpio_speed,
+            nss_output_disable,
         }
     }
 
@@ -708,6 +769,30 @@ impl<'d> Spi<'d, Async, Master> {
         )
     }
 
+    /// Create a new SPI driver, in bidirectional mode, specifically in tranmit mode    
+    #[cfg(any(spi_v1, spi_v2, spi_v3))]
+    pub fn new_bidi<T: Instance, #[cfg(afio)] A>(
+        peri: Peri<'d, T>,
+        sck: Peri<'d, if_afio!(impl SckPin<T, A>)>,
+        sdio: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
+        tx_dma: Peri<'d, impl TxDma<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
+        config: Config,
+    ) -> Self {
+        let mut this = Self::new_inner(
+            peri,
+            new_pin!(sck, config.sck_af()),
+            new_pin!(sdio, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            None,
+            None,
+            new_dma!(tx_dma),
+            new_dma!(rx_dma),
+            config,
+        );
+        this.set_direction(Some(Direction::Transmit));
+        this
+    }
+
     /// Create a new SPI driver, in TX-only mode, without SCK pin.
     ///
     /// This can be useful for bit-banging non-SPI protocols.
@@ -763,6 +848,7 @@ impl<'d> Spi<'d, Async, Master> {
 impl<'d, CM: CommunicationMode> Spi<'d, Async, CM> {
     /// SPI write, using DMA.
     pub async fn write<W: Word>(&mut self, data: &[W]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         if data.is_empty() {
             return Ok(());
         }
@@ -794,6 +880,7 @@ impl<'d, CM: CommunicationMode> Spi<'d, Async, CM> {
     /// SPI read, using DMA.
     #[cfg(any(spi_v4, spi_v5, spi_v6))]
     pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         if data.is_empty() {
             return Ok(());
         }
@@ -881,6 +968,7 @@ impl<'d, CM: CommunicationMode> Spi<'d, Async, CM> {
     /// SPI read, using DMA.
     #[cfg(any(spi_v1, spi_v2, spi_v3))]
     pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         if data.is_empty() {
             return Ok(());
         }
@@ -928,6 +1016,7 @@ impl<'d, CM: CommunicationMode> Spi<'d, Async, CM> {
     }
 
     async fn transfer_inner<W: Word>(&mut self, read: *mut [W], write: *const [W]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
         assert_eq!(read.len(), write.len());
         if read.len() == 0 {
             return Ok(());
@@ -979,6 +1068,8 @@ impl<'d, CM: CommunicationMode> Spi<'d, Async, CM> {
     /// The transfer runs for `max(read.len(), write.len())` bytes. If `read` is shorter extra bytes are ignored.
     /// If `write` is shorter it is padded with zero bytes.
     pub async fn transfer<W: Word>(&mut self, read: &mut [W], write: &[W]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
+
         self.transfer_inner(read, write).await
     }
 
@@ -986,6 +1077,8 @@ impl<'d, CM: CommunicationMode> Spi<'d, Async, CM> {
     ///
     /// This writes the contents of `data` on MOSI, and puts the received data on MISO in `data`, at the same time.
     pub async fn transfer_in_place<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
+        let _scoped_block_stop = self.info.rcc.block_stop();
+
         self.transfer_inner(data, data).await
     }
 }
diff --git a/embassy-stm32/src/time.rs b/embassy-stm32/src/time.rs
index 532877f70..88a28ee3d 100644
--- a/embassy-stm32/src/time.rs
+++ b/embassy-stm32/src/time.rs
@@ -4,7 +4,7 @@ use core::fmt::Display;
 use core::ops::{Div, Mul};
 
 /// Hertz
-#[derive(Eq, PartialEq, Ord, PartialOrd, Clone, Copy, Debug)]
+#[derive(Eq, PartialEq, Ord, PartialOrd, Clone, Copy, Debug, Default)]
 pub struct Hertz(pub u32);
 
 impl Display for Hertz {
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index cfcf5f3fd..ed5d902bd 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -329,6 +329,12 @@ impl RtcDriver {
         regs_gp16().cr1().modify(|w| w.set_cen(true));
     }
 
+    #[cfg(feature = "low-power")]
+    /// Returns whether time is currently stopped
+    pub(crate) fn is_stopped(&self) -> bool {
+        !regs_gp16().cr1().read().cen()
+    }
+
     fn set_alarm(&self, cs: CriticalSection, timestamp: u64) -> bool {
         let r = regs_gp16();
 
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 77f19a37b..620d7858e 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -2,16 +2,17 @@
 
 use core::marker::PhantomData;
 
-pub use stm32_metapac::timer::vals::{Ckd, Mms2, Ossi, Ossr};
-
 use super::low_level::{CountingMode, OutputPolarity, Timer};
 use super::simple_pwm::PwmPin;
 use super::{AdvancedInstance4Channel, Ch1, Ch2, Ch3, Ch4, Channel, TimerComplementaryPin};
 use crate::Peri;
-use crate::gpio::{AnyPin, OutputType};
+use crate::dma::word::Word;
+use crate::gpio::{AfType, AnyPin, OutputType};
+pub use crate::pac::timer::vals::{Ccds, Ckd, Mms2, Ossi, Ossr};
 use crate::time::Hertz;
 use crate::timer::TimerChannel;
 use crate::timer::low_level::OutputCompareMode;
+use crate::timer::simple_pwm::PwmPinConfig;
 
 /// Complementary PWM pin wrapper.
 ///
@@ -27,9 +28,27 @@ impl<'d, T: AdvancedInstance4Channel, C: TimerChannel, #[cfg(afio)] A> if_afio!(
     pub fn new(pin: Peri<'d, if_afio!(impl TimerComplementaryPin<T, C, A>)>, output_type: OutputType) -> Self {
         critical_section::with(|_| {
             pin.set_low();
-            set_as_af!(
-                pin,
-                crate::gpio::AfType::output(output_type, crate::gpio::Speed::VeryHigh)
+            set_as_af!(pin, AfType::output(output_type, crate::gpio::Speed::VeryHigh));
+        });
+        ComplementaryPwmPin {
+            pin: pin.into(),
+            phantom: PhantomData,
+        }
+    }
+
+    /// Create a new PWM pin instance with config.
+    pub fn new_with_config(
+        pin: Peri<'d, if_afio!(impl TimerComplementaryPin<T, C, A>)>,
+        pin_config: PwmPinConfig,
+    ) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            #[cfg(gpio_v1)]
+            set_as_af!(pin, AfType::output(pin_config.output_type, pin_config.speed));
+            #[cfg(gpio_v2)]
+            pin.set_as_af(
+                pin.af_num(),
+                AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull),
             );
         });
         ComplementaryPwmPin {
@@ -176,20 +195,20 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Get max duty value.
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
-    pub fn get_max_duty(&self) -> u16 {
+    pub fn get_max_duty(&self) -> u32 {
         if self.inner.get_counting_mode().is_center_aligned() {
-            self.inner.get_max_compare_value() as u16
+            self.inner.get_max_compare_value().into()
         } else {
-            self.inner.get_max_compare_value() as u16 + 1
+            self.inner.get_max_compare_value().into() + 1
         }
     }
 
     /// Set the duty for a given channel.
     ///
     /// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
-    pub fn set_duty(&mut self, channel: Channel, duty: u16) {
+    pub fn set_duty(&mut self, channel: Channel, duty: u32) {
         assert!(duty <= self.get_max_duty());
-        self.inner.set_compare_value(channel, duty as _)
+        self.inner.set_compare_value(channel, unwrap!(duty.try_into()))
     }
 
     /// Set the output polarity for a given channel.
@@ -219,9 +238,34 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Generate a sequence of PWM waveform
     ///
     /// Note:
+    /// The DMA channel provided does not need to correspond to the requested channel.
+    pub async fn waveform<C: TimerChannel, W: Word + Into<T::Word>>(
+        &mut self,
+        dma: Peri<'_, impl super::Dma<T, C>>,
+        channel: Channel,
+        duty: &[W],
+    ) {
+        self.inner.enable_channel(channel, true);
+        self.inner.enable_channel(C::CHANNEL, true);
+        self.inner.clamp_compare_value::<W>(channel);
+        self.inner.set_cc_dma_selection(Ccds::ON_UPDATE);
+        self.inner.set_cc_dma_enable_state(C::CHANNEL, true);
+        self.inner.setup_channel_update_dma(dma, channel, duty).await;
+        self.inner.set_cc_dma_enable_state(C::CHANNEL, false);
+    }
+
+    /// Generate a sequence of PWM waveform
+    ///
+    /// Note:
     /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
-    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
+    pub async fn waveform_up<W: Word + Into<T::Word>>(
+        &mut self,
+        dma: Peri<'_, impl super::UpDma<T>>,
+        channel: Channel,
+        duty: &[W],
+    ) {
         self.inner.enable_channel(channel, true);
+        self.inner.clamp_compare_value::<W>(channel);
         self.inner.enable_update_dma(true);
         self.inner.setup_update_dma(dma, channel, duty).await;
         self.inner.enable_update_dma(false);
@@ -256,13 +300,21 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
     ///
-    pub async fn waveform_up_multi_channel(
+    pub async fn waveform_up_multi_channel<W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'_, impl super::UpDma<T>>,
         starting_channel: Channel,
         ending_channel: Channel,
-        duty: &[u16],
+        duty: &[W],
     ) {
+        [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
+            .iter()
+            .filter(|ch| ch.index() >= starting_channel.index())
+            .filter(|ch| ch.index() <= ending_channel.index())
+            .for_each(|ch| {
+                self.inner.enable_channel(*ch, true);
+                self.inner.clamp_compare_value::<W>(*ch);
+            });
         self.inner.enable_update_dma(true);
         self.inner
             .setup_update_dma_burst(dma, starting_channel, ending_channel, duty)
@@ -291,20 +343,20 @@ impl<'d, T: AdvancedInstance4Channel> embedded_hal_02::Pwm for ComplementaryPwm<
     }
 
     fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
-        self.inner.get_compare_value(channel) as u16
+        unwrap!(self.inner.get_compare_value(channel).try_into())
     }
 
     fn get_max_duty(&self) -> Self::Duty {
         if self.inner.get_counting_mode().is_center_aligned() {
-            self.inner.get_max_compare_value() as u16
+            unwrap!(self.inner.get_max_compare_value().try_into())
         } else {
-            self.inner.get_max_compare_value() as u16 + 1
+            unwrap!(self.inner.get_max_compare_value().try_into()) + 1
         }
     }
 
     fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
-        assert!(duty <= self.get_max_duty());
-        self.inner.set_compare_value(channel, duty as u32)
+        assert!(duty <= unwrap!(self.get_max_duty().try_into()));
+        self.inner.set_compare_value(channel, unwrap!(duty.try_into()))
     }
 
     fn set_period<P>(&mut self, period: P)
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index 9cf0f8c34..3e1482b67 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -97,7 +97,7 @@ impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
 
     /// Get capture value for a channel.
     pub fn get_capture_value(&self, channel: Channel) -> u32 {
-        self.inner.get_capture_value(channel)
+        self.inner.get_capture_value(channel).into()
     }
 
     /// Get input interrupt.
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index aba08081f..82e936f3a 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -13,7 +13,7 @@ use embassy_hal_internal::Peri;
 pub use stm32_metapac::timer::vals::{FilterValue, Mms as MasterMode, Sms as SlaveMode, Ts as TriggerSource};
 
 use super::*;
-use crate::dma::{Transfer, WritableRingBuffer};
+use crate::dma::{self, Transfer, WritableRingBuffer};
 use crate::pac::timer::vals;
 use crate::rcc;
 use crate::time::Hertz;
@@ -268,6 +268,11 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
         unsafe { crate::pac::timer::TimGp32::from_ptr(T::regs()) }
     }
 
+    #[cfg(stm32l0)]
+    fn regs_gp32_unchecked(&self) -> crate::pac::timer::TimGp16 {
+        unsafe { crate::pac::timer::TimGp16::from_ptr(T::regs()) }
+    }
+
     /// Start the timer.
     pub fn start(&self) {
         self.regs_core().cr1().modify(|r| r.set_cen(true));
@@ -296,7 +301,12 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
 
     /// get the capability of the timer
     pub fn bits(&self) -> TimerBits {
-        T::BITS
+        match T::Word::bits() {
+            16 => TimerBits::Bits16,
+            #[cfg(not(stm32l0))]
+            32 => TimerBits::Bits32,
+            _ => unreachable!(),
+        }
     }
 
     /// Set the frequency of how many times per second the timer counts up to the max value or down to 0.
@@ -306,18 +316,10 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
     /// In center-aligned mode (which not all timers support), the wrap-around frequency is effectively halved
     /// because it needs to count up and down.
     pub fn set_frequency(&self, frequency: Hertz) {
-        match T::BITS {
-            TimerBits::Bits16 => {
-                self.set_frequency_internal(frequency, 16);
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                self.set_frequency_internal(frequency, 32);
-            }
-        }
+        self.set_frequency_internal(frequency, T::Word::bits());
     }
 
-    pub(crate) fn set_frequency_internal(&self, frequency: Hertz, max_divide_by_bits: u8) {
+    pub(crate) fn set_frequency_internal(&self, frequency: Hertz, max_divide_by_bits: usize) {
         let f = frequency.0;
         assert!(f > 0);
         let timer_f = T::frequency().0;
@@ -326,25 +328,15 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
         let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << max_divide_by_bits)).try_into());
         let divide_by = pclk_ticks_per_timer_period / (u64::from(psc) + 1);
 
-        match T::BITS {
-            TimerBits::Bits16 => {
-                // the timer counts `0..=arr`, we want it to count `0..divide_by`
-                let arr = unwrap!(u16::try_from(divide_by - 1));
-
-                let regs = self.regs_core();
-                regs.psc().write_value(psc);
-                regs.arr().write(|r| r.set_arr(arr));
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                // the timer counts `0..=arr`, we want it to count `0..divide_by`
-                let arr: u32 = unwrap!(u32::try_from(divide_by - 1));
+        // the timer counts `0..=arr`, we want it to count `0..divide_by`
+        let arr: T::Word = unwrap!(T::Word::try_from(divide_by - 1));
 
-                let regs = self.regs_gp32_unchecked();
-                regs.psc().write_value(psc);
-                regs.arr().write_value(arr);
-            }
-        }
+        let regs = self.regs_gp32_unchecked();
+        regs.psc().write_value(psc);
+        #[cfg(stm32l0)]
+        regs.arr().write(|r| r.set_arr(unwrap!(arr.try_into())));
+        #[cfg(not(stm32l0))]
+        regs.arr().write_value(arr.into());
     }
 
     /// Set tick frequency.
@@ -393,23 +385,14 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
     pub fn get_frequency(&self) -> Hertz {
         let timer_f = T::frequency();
 
-        match T::BITS {
-            TimerBits::Bits16 => {
-                let regs = self.regs_core();
-                let arr = regs.arr().read().arr();
-                let psc = regs.psc().read();
+        let regs = self.regs_gp32_unchecked();
+        #[cfg(not(stm32l0))]
+        let arr = regs.arr().read();
+        #[cfg(stm32l0)]
+        let arr = regs.arr().read().arr();
+        let psc = regs.psc().read();
 
-                timer_f / arr / (psc + 1)
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                let regs = self.regs_gp32_unchecked();
-                let arr = regs.arr().read();
-                let psc = regs.psc().read();
-
-                timer_f / arr / (psc + 1)
-            }
-        }
+        timer_f / arr / (psc + 1)
     }
 
     /// Get the clock frequency of the timer (before prescaler is applied).
@@ -469,42 +452,29 @@ impl<'d, T: GeneralInstance1Channel> Timer<'d, T> {
     }
 
     /// Get max compare value. This depends on the timer frequency and the clock frequency from RCC.
-    pub fn get_max_compare_value(&self) -> u32 {
-        match T::BITS {
-            TimerBits::Bits16 => self.regs_1ch().arr().read().arr() as u32,
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => self.regs_gp32_unchecked().arr().read(),
-        }
+    pub fn get_max_compare_value(&self) -> T::Word {
+        #[cfg(not(stm32l0))]
+        return unwrap!(self.regs_gp32_unchecked().arr().read().try_into());
+        #[cfg(stm32l0)]
+        return unwrap!(self.regs_gp32_unchecked().arr().read().arr().try_into());
     }
 
     /// Set the max compare value.
     ///
     /// An update event is generated to load the new value. The update event is
     /// generated such that it will not cause an interrupt or DMA request.
-    pub fn set_max_compare_value(&self, ticks: u32) {
-        match T::BITS {
-            TimerBits::Bits16 => {
-                let arr = unwrap!(u16::try_from(ticks));
+    pub fn set_max_compare_value(&self, ticks: T::Word) {
+        let arr = ticks;
 
-                let regs = self.regs_1ch();
-                regs.arr().write(|r| r.set_arr(arr));
+        let regs = self.regs_gp32_unchecked();
+        #[cfg(not(stm32l0))]
+        regs.arr().write_value(arr.into());
+        #[cfg(stm32l0)]
+        regs.arr().write(|r| r.set_arr(unwrap!(arr.try_into())));
 
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                let arr = ticks;
-
-                let regs = self.regs_gp32_unchecked();
-                regs.arr().write_value(arr);
-
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
-            }
-        }
+        regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
+        regs.egr().write(|r| r.set_ug(true));
+        regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
     }
 }
 
@@ -638,35 +608,44 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
     }
 
     /// Set compare value for a channel.
-    pub fn set_compare_value(&self, channel: Channel, value: u32) {
-        match T::BITS {
-            TimerBits::Bits16 => {
-                let value = unwrap!(u16::try_from(value));
-                self.regs_gp16().ccr(channel.index()).modify(|w| w.set_ccr(value));
-            }
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => {
-                self.regs_gp32_unchecked().ccr(channel.index()).write_value(value);
-            }
-        }
+    pub fn set_compare_value(&self, channel: Channel, value: T::Word) {
+        #[cfg(not(stm32l0))]
+        self.regs_gp32_unchecked()
+            .ccr(channel.index())
+            .write_value(value.into());
+        #[cfg(stm32l0)]
+        self.regs_gp16()
+            .ccr(channel.index())
+            .modify(|w| w.set_ccr(unwrap!(value.try_into())));
     }
 
     /// Get compare value for a channel.
-    pub fn get_compare_value(&self, channel: Channel) -> u32 {
-        match T::BITS {
-            TimerBits::Bits16 => self.regs_gp16().ccr(channel.index()).read().ccr() as u32,
-            #[cfg(not(stm32l0))]
-            TimerBits::Bits32 => self.regs_gp32_unchecked().ccr(channel.index()).read(),
-        }
+    pub fn get_compare_value(&self, channel: Channel) -> T::Word {
+        #[cfg(not(stm32l0))]
+        return unwrap!(self.regs_gp32_unchecked().ccr(channel.index()).read().try_into());
+        #[cfg(stm32l0)]
+        return unwrap!(self.regs_gp32_unchecked().ccr(channel.index()).read().ccr().try_into());
+    }
+
+    pub(crate) fn clamp_compare_value<W: Word>(&mut self, channel: Channel) {
+        self.set_compare_value(
+            channel,
+            unwrap!(
+                self.get_compare_value(channel)
+                    .into()
+                    .clamp(0, W::max() as u32)
+                    .try_into()
+            ),
+        );
     }
 
     /// Setup a ring buffer for the channel
-    pub fn setup_ring_buffer<'a>(
+    pub fn setup_ring_buffer<'a, W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'a, impl super::UpDma<T>>,
         channel: Channel,
-        dma_buf: &'a mut [u16],
-    ) -> WritableRingBuffer<'a, u16> {
+        dma_buf: &'a mut [W],
+    ) -> WritableRingBuffer<'a, W> {
         #[allow(clippy::let_unit_value)] // eg. stm32f334
         let req = dma.request();
 
@@ -686,7 +665,7 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
             WritableRingBuffer::new(
                 dma,
                 req,
-                self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
+                self.regs_1ch().ccr(channel.index()).as_ptr() as *mut W,
                 dma_buf,
                 dma_transfer_option,
             )
@@ -697,15 +676,35 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
     ///
     /// Note:
     /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
-    pub fn setup_update_dma<'a>(
+    pub fn setup_update_dma<'a, W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'a, impl super::UpDma<T>>,
         channel: Channel,
-        duty: &'a [u16],
+        duty: &'a [W],
     ) -> Transfer<'a> {
-        #[allow(clippy::let_unit_value)] // eg. stm32f334
-        let req = dma.request();
+        self.setup_update_dma_inner(dma.request(), dma, channel, duty)
+    }
 
+    /// Generate a sequence of PWM waveform
+    ///
+    /// Note:
+    /// The DMA channel provided does not need to correspond to the requested channel.
+    pub fn setup_channel_update_dma<'a, C: TimerChannel, W: Word + Into<T::Word>>(
+        &mut self,
+        dma: Peri<'a, impl super::Dma<T, C>>,
+        channel: Channel,
+        duty: &'a [W],
+    ) -> Transfer<'a> {
+        self.setup_update_dma_inner(dma.request(), dma, channel, duty)
+    }
+
+    fn setup_update_dma_inner<'a, W: Word + Into<T::Word>>(
+        &mut self,
+        request: dma::Request,
+        dma: Peri<'a, impl dma::Channel>,
+        channel: Channel,
+        duty: &'a [W],
+    ) -> Transfer<'a> {
         unsafe {
             #[cfg(not(any(bdma, gpdma)))]
             use crate::dma::{Burst, FifoThreshold};
@@ -719,29 +718,13 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
                 ..Default::default()
             };
 
-            match self.bits() {
-                TimerBits::Bits16 => Transfer::new_write(
-                    dma,
-                    req,
-                    duty,
-                    self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
-                    dma_transfer_option,
-                ),
-                #[cfg(not(any(stm32l0)))]
-                TimerBits::Bits32 => {
-                    #[cfg(not(any(bdma, gpdma)))]
-                    panic!("unsupported timer bits");
-
-                    #[cfg(any(bdma, gpdma))]
-                    Transfer::new_write(
-                        dma,
-                        req,
-                        duty,
-                        self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u32,
-                        dma_transfer_option,
-                    )
-                }
-            }
+            Transfer::new_write(
+                dma,
+                request,
+                duty,
+                self.regs_gp16().ccr(channel.index()).as_ptr() as *mut W,
+                dma_transfer_option,
+            )
         }
     }
 
@@ -774,12 +757,12 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
     ///
-    pub fn setup_update_dma_burst<'a>(
+    pub fn setup_update_dma_burst<'a, W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'a, impl super::UpDma<T>>,
         starting_channel: Channel,
         ending_channel: Channel,
-        duty: &'a [u16],
+        duty: &'a [W],
     ) -> Transfer<'a> {
         let cr1_addr = self.regs_gp16().cr1().as_ptr() as u32;
         let start_ch_index = starting_channel.index();
@@ -815,14 +798,14 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
                 dma,
                 req,
                 duty,
-                self.regs_gp16().dmar().as_ptr() as *mut u16,
+                self.regs_gp16().dmar().as_ptr() as *mut W,
                 dma_transfer_option,
             )
         }
     }
 
     /// Get capture value for a channel.
-    pub fn get_capture_value(&self, channel: Channel) -> u32 {
+    pub fn get_capture_value(&self, channel: Channel) -> T::Word {
         self.get_compare_value(channel)
     }
 
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 3fa363881..998e3a6f4 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -15,6 +15,8 @@ pub mod qei;
 pub mod ringbuffered;
 pub mod simple_pwm;
 
+use crate::dma::word::Word;
+use crate::fmt::Debuggable;
 use crate::interrupt;
 use crate::rcc::RccPeripheral;
 
@@ -163,7 +165,12 @@ pub trait CoreInstance: SealedInstance + 'static {
     type UpdateInterrupt: interrupt::typelevel::Interrupt;
 
     /// Amount of bits this timer has.
-    const BITS: TimerBits;
+    type Word: Word
+        + TryInto<u16, Error: Debuggable>
+        + From<u16>
+        + TryFrom<u32, Error: Debuggable>
+        + Into<u32>
+        + TryFrom<u64, Error: Debuggable>;
 
     /// Registers for this timer.
     ///
@@ -241,7 +248,7 @@ dma_trait!(Dma, GeneralInstance4Channel, TimerChannel);
 
 #[allow(unused)]
 macro_rules! impl_core_timer {
-    ($inst:ident, $bits:expr) => {
+    ($inst:ident, $bits:ident) => {
         impl SealedInstance for crate::peripherals::$inst {
             fn state() -> &'static State {
                 static STATE: State = State::new();
@@ -251,8 +258,7 @@ macro_rules! impl_core_timer {
 
         impl CoreInstance for crate::peripherals::$inst {
             type UpdateInterrupt = crate::_generated::peripheral_interrupts::$inst::UP;
-
-            const BITS: TimerBits = $bits;
+            type Word = $bits;
 
             fn regs() -> *mut () {
                 crate::pac::$inst.as_ptr()
@@ -306,13 +312,13 @@ macro_rules! impl_general_4ch_blank_sealed {
 
 foreach_interrupt! {
     ($inst:ident, timer, TIM_BASIC, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
     };
 
     ($inst:ident, timer, TIM_1CH, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -322,7 +328,7 @@ foreach_interrupt! {
     };
 
     ($inst:ident, timer, TIM_2CH, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -332,7 +338,7 @@ foreach_interrupt! {
     };
 
     ($inst:ident, timer, TIM_GP16, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -342,7 +348,7 @@ foreach_interrupt! {
     };
 
     ($inst:ident, timer, TIM_GP32, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits32);
+        impl_core_timer!($inst, u32);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -353,7 +359,7 @@ foreach_interrupt! {
     };
 
     ($inst:ident, timer, TIM_1CH_CMP, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -366,7 +372,7 @@ foreach_interrupt! {
     };
 
     ($inst:ident, timer, TIM_2CH_CMP, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -379,7 +385,7 @@ foreach_interrupt! {
     };
 
     ($inst:ident, timer, TIM_ADV, UP, $irq:ident) => {
-        impl_core_timer!($inst, TimerBits::Bits16);
+        impl_core_timer!($inst, u16);
         impl BasicNoCr2Instance for crate::peripherals::$inst {}
         impl BasicInstance for crate::peripherals::$inst {}
         impl_general_1ch!($inst);
@@ -400,7 +406,7 @@ pub struct UpdateInterruptHandler<T: CoreInstance> {
 impl<T: CoreInstance> interrupt::typelevel::Handler<T::UpdateInterrupt> for UpdateInterruptHandler<T> {
     unsafe fn on_interrupt() {
         #[cfg(feature = "low-power")]
-        crate::low_power::Executor::on_wakeup_irq();
+        crate::low_power::Executor::on_wakeup_irq_or_event();
 
         let regs = crate::pac::timer::TimCore::from_ptr(T::regs());
 
@@ -430,7 +436,7 @@ impl<T: GeneralInstance1Channel> interrupt::typelevel::Handler<T::CaptureCompare
 {
     unsafe fn on_interrupt() {
         #[cfg(feature = "low-power")]
-        crate::low_power::Executor::on_wakeup_irq();
+        crate::low_power::Executor::on_wakeup_irq_or_event();
 
         let regs = crate::pac::timer::TimGp16::from_ptr(T::regs());
 
diff --git a/embassy-stm32/src/timer/one_pulse.rs b/embassy-stm32/src/timer/one_pulse.rs
index fe8681356..989e1d630 100644
--- a/embassy-stm32/src/timer/one_pulse.rs
+++ b/embassy-stm32/src/timer/one_pulse.rs
@@ -199,7 +199,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     fn new_inner(&mut self, freq: Hertz, pulse_end: u32, counting_mode: CountingMode) {
         self.inner.set_counting_mode(counting_mode);
         self.inner.set_tick_freq(freq);
-        self.inner.set_max_compare_value(pulse_end);
+        self.inner.set_max_compare_value(unwrap!(pulse_end.try_into()));
         self.inner.regs_core().cr1().modify(|r| r.set_opm(true));
         // Required for advanced timers, see GeneralInstance4Channel for details
         self.inner.enable_outputs();
@@ -211,14 +211,14 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
 
     /// Get the end of the pulse in ticks from the trigger.
     pub fn pulse_end(&self) -> u32 {
-        let max = self.inner.get_max_compare_value();
+        let max: u32 = self.inner.get_max_compare_value().into();
         assert!(max < u32::MAX);
         max + 1
     }
 
     /// Set the end of the pulse in ticks from the trigger.
     pub fn set_pulse_end(&mut self, ticks: u32) {
-        self.inner.set_max_compare_value(ticks)
+        self.inner.set_max_compare_value(unwrap!(ticks.try_into()))
     }
 
     /// Reset the timer on each trigger
@@ -327,7 +327,7 @@ pub struct OnePulseChannel<'d, T: GeneralInstance4Channel> {
 impl<'d, T: GeneralInstance4Channel> OnePulseChannel<'d, T> {
     /// Get the end of the pulse in ticks from the trigger.
     pub fn pulse_end(&self) -> u32 {
-        let max = self.inner.get_max_compare_value();
+        let max: u32 = self.inner.get_max_compare_value().into();
         assert!(max < u32::MAX);
         max + 1
     }
@@ -339,13 +339,13 @@ impl<'d, T: GeneralInstance4Channel> OnePulseChannel<'d, T> {
 
     /// Get the start of the pulse in ticks from the trigger.
     pub fn pulse_delay(&mut self) -> u32 {
-        self.inner.get_compare_value(self.channel)
+        self.inner.get_compare_value(self.channel).into()
     }
 
     /// Set the start of the pulse in ticks from the trigger.
     pub fn set_pulse_delay(&mut self, delay: u32) {
         assert!(delay <= self.pulse_end());
-        self.inner.set_compare_value(self.channel, delay);
+        self.inner.set_compare_value(self.channel, unwrap!(delay.try_into()));
     }
 
     /// Set the pulse width in ticks.
diff --git a/embassy-stm32/src/timer/pwm_input.rs b/embassy-stm32/src/timer/pwm_input.rs
index 057ab011a..f2f00927d 100644
--- a/embassy-stm32/src/timer/pwm_input.rs
+++ b/embassy-stm32/src/timer/pwm_input.rs
@@ -91,16 +91,18 @@ impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
 
     /// Get the period tick count
     pub fn get_period_ticks(&self) -> u32 {
-        self.inner.get_capture_value(self.channel)
+        self.inner.get_capture_value(self.channel).into()
     }
 
     /// Get the pulse width tick count
     pub fn get_width_ticks(&self) -> u32 {
-        self.inner.get_capture_value(match self.channel {
-            Channel::Ch1 => Channel::Ch2,
-            Channel::Ch2 => Channel::Ch1,
-            _ => panic!("Invalid channel for PWM input"),
-        })
+        self.inner
+            .get_capture_value(match self.channel {
+                Channel::Ch1 => Channel::Ch2,
+                Channel::Ch2 => Channel::Ch1,
+                _ => panic!("Invalid channel for PWM input"),
+            })
+            .into()
     }
 
     /// Get the duty cycle in 100%
diff --git a/embassy-stm32/src/timer/ringbuffered.rs b/embassy-stm32/src/timer/ringbuffered.rs
index e8f97bf59..fbb6b19ea 100644
--- a/embassy-stm32/src/timer/ringbuffered.rs
+++ b/embassy-stm32/src/timer/ringbuffered.rs
@@ -7,6 +7,7 @@ use super::low_level::Timer;
 use super::{Channel, GeneralInstance4Channel};
 use crate::dma::WritableRingBuffer;
 use crate::dma::ringbuffer::Error;
+use crate::dma::word::Word;
 
 /// A PWM channel that uses a DMA ring buffer for continuous waveform generation.
 ///
@@ -23,17 +24,17 @@ use crate::dma::ringbuffer::Error;
 /// channel.start(); // Start DMA transfer
 /// channel.write(&[100, 200, 300]).ok(); // Update duty cycles
 /// ```
-pub struct RingBufferedPwmChannel<'d, T: GeneralInstance4Channel> {
+pub struct RingBufferedPwmChannel<'d, T: GeneralInstance4Channel, W: Word + Into<T::Word>> {
     timer: ManuallyDrop<Timer<'d, T>>,
-    ring_buf: WritableRingBuffer<'d, u16>,
+    ring_buf: WritableRingBuffer<'d, W>,
     channel: Channel,
 }
 
-impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
+impl<'d, T: GeneralInstance4Channel, W: Word + Into<T::Word>> RingBufferedPwmChannel<'d, T, W> {
     pub(crate) fn new(
         timer: ManuallyDrop<Timer<'d, T>>,
         channel: Channel,
-        ring_buf: WritableRingBuffer<'d, u16>,
+        ring_buf: WritableRingBuffer<'d, W>,
     ) -> Self {
         Self {
             timer,
@@ -55,18 +56,18 @@ impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
     }
 
     /// Write elements directly to the raw buffer. This can be used to fill the buffer before starting the DMA transfer.
-    pub fn write_immediate(&mut self, buf: &[u16]) -> Result<(usize, usize), Error> {
+    pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), Error> {
         self.ring_buf.write_immediate(buf)
     }
 
     /// Write elements from the ring buffer
     /// Return a tuple of the length written and the length remaining in the buffer
-    pub fn write(&mut self, buf: &[u16]) -> Result<(usize, usize), Error> {
+    pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), Error> {
         self.ring_buf.write(buf)
     }
 
     /// Write an exact number of elements to the ringbuffer.
-    pub async fn write_exact(&mut self, buffer: &[u16]) -> Result<usize, Error> {
+    pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, Error> {
         self.ring_buf.write_exact(buffer).await
     }
 
@@ -140,7 +141,7 @@ impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
     pub fn max_duty_cycle(&self) -> u16 {
-        let max = self.timer.get_max_compare_value();
+        let max: u32 = self.timer.get_max_compare_value().into();
         assert!(max < u16::MAX as u32);
         max as u16 + 1
     }
@@ -155,15 +156,3 @@ impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
         self.timer.set_output_compare_mode(self.channel, mode);
     }
 }
-
-/// A group of four [`SimplePwmChannel`]s, obtained from [`SimplePwm::split`].
-pub struct RingBufferedPwmChannels<'d, T: GeneralInstance4Channel> {
-    /// Channel 1
-    pub ch1: RingBufferedPwmChannel<'d, T>,
-    /// Channel 2
-    pub ch2: RingBufferedPwmChannel<'d, T>,
-    /// Channel 3
-    pub ch3: RingBufferedPwmChannel<'d, T>,
-    /// Channel 4
-    pub ch4: RingBufferedPwmChannel<'d, T>,
-}
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 484e9fd81..9a5f0fd1d 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -7,9 +7,11 @@ use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer};
 use super::ringbuffered::RingBufferedPwmChannel;
 use super::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance4Channel, TimerChannel, TimerPin};
 use crate::Peri;
+use crate::dma::word::Word;
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
+use crate::pac::timer::vals::Ccds;
 use crate::time::Hertz;
 
 /// PWM pin wrapper.
@@ -98,18 +100,16 @@ impl<'d, T: GeneralInstance4Channel> SimplePwmChannel<'d, T> {
     /// Get max duty value.
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
-    pub fn max_duty_cycle(&self) -> u16 {
-        let max = self.timer.get_max_compare_value();
-        assert!(max < u16::MAX as u32);
-        max as u16 + 1
+    pub fn max_duty_cycle(&self) -> u32 {
+        self.timer.get_max_compare_value().into() + 1
     }
 
     /// Set the duty for a given channel.
     ///
     /// The value ranges from 0 for 0% duty, to [`max_duty_cycle`](Self::max_duty_cycle) for 100% duty, both included.
-    pub fn set_duty_cycle(&mut self, duty: u16) {
+    pub fn set_duty_cycle(&mut self, duty: u32) {
         assert!(duty <= (*self).max_duty_cycle());
-        self.timer.set_compare_value(self.channel, duty.into())
+        self.timer.set_compare_value(self.channel, unwrap!(duty.try_into()))
     }
 
     /// Set the duty cycle to 0%, or always inactive.
@@ -126,21 +126,21 @@ impl<'d, T: GeneralInstance4Channel> SimplePwmChannel<'d, T> {
     ///
     /// The caller is responsible for ensuring that `num` is less than or equal to `denom`,
     /// and that `denom` is not zero.
-    pub fn set_duty_cycle_fraction(&mut self, num: u16, denom: u16) {
+    pub fn set_duty_cycle_fraction(&mut self, num: u32, denom: u32) {
         assert!(denom != 0);
         assert!(num <= denom);
         let duty = u32::from(num) * u32::from(self.max_duty_cycle()) / u32::from(denom);
 
         // This is safe because we know that `num <= denom`, so `duty <= self.max_duty_cycle()` (u16)
         #[allow(clippy::cast_possible_truncation)]
-        self.set_duty_cycle(duty as u16);
+        self.set_duty_cycle(unwrap!(duty.try_into()));
     }
 
     /// Set the duty cycle to `percent / 100`
     ///
     /// The caller is responsible for ensuring that `percent` is less than or equal to 100.
     pub fn set_duty_cycle_percent(&mut self, percent: u8) {
-        self.set_duty_cycle_fraction(u16::from(percent), 100)
+        self.set_duty_cycle_fraction(percent as u32, 100)
     }
 
     /// Get the duty for a given channel.
@@ -171,13 +171,14 @@ impl<'d, T: GeneralInstance4Channel> SimplePwmChannel<'d, T> {
     ///
     /// # Panics
     /// Panics if `dma_buf` is empty or longer than 65535 elements.
-    pub fn into_ring_buffered_channel(
+    pub fn into_ring_buffered_channel<W: Word + Into<T::Word>>(
         mut self,
         tx_dma: Peri<'d, impl super::UpDma<T>>,
-        dma_buf: &'d mut [u16],
-    ) -> RingBufferedPwmChannel<'d, T> {
+        dma_buf: &'d mut [W],
+    ) -> RingBufferedPwmChannel<'d, T, W> {
         assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
 
+        self.timer.clamp_compare_value::<W>(self.channel);
         self.timer.enable_update_dma(true);
 
         RingBufferedPwmChannel::new(
@@ -332,10 +333,27 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Get max duty value.
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
-    pub fn max_duty_cycle(&self) -> u16 {
-        let max = self.inner.get_max_compare_value();
-        assert!(max < u16::MAX as u32);
-        max as u16 + 1
+    pub fn max_duty_cycle(&self) -> u32 {
+        self.inner.get_max_compare_value().into() + 1
+    }
+
+    /// Generate a sequence of PWM waveform
+    ///
+    /// Note:
+    /// The DMA channel provided does not need to correspond to the requested channel.
+    pub async fn waveform<C: TimerChannel, W: Word + Into<T::Word>>(
+        &mut self,
+        dma: Peri<'_, impl super::Dma<T, C>>,
+        channel: Channel,
+        duty: &[W],
+    ) {
+        self.inner.enable_channel(channel, true);
+        self.inner.enable_channel(C::CHANNEL, true);
+        self.inner.clamp_compare_value::<W>(channel);
+        self.inner.set_cc_dma_selection(Ccds::ON_UPDATE);
+        self.inner.set_cc_dma_enable_state(C::CHANNEL, true);
+        self.inner.setup_channel_update_dma(dma, channel, duty).await;
+        self.inner.set_cc_dma_enable_state(C::CHANNEL, false);
     }
 
     /// Generate a sequence of PWM waveform
@@ -344,8 +362,14 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
-    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
+    pub async fn waveform_up<W: Word + Into<T::Word>>(
+        &mut self,
+        dma: Peri<'_, impl super::UpDma<T>>,
+        channel: Channel,
+        duty: &[W],
+    ) {
         self.inner.enable_channel(channel, true);
+        self.inner.clamp_compare_value::<W>(channel);
         self.inner.enable_update_dma(true);
         self.inner.setup_update_dma(dma, channel, duty).await;
         self.inner.enable_update_dma(false);
@@ -380,13 +404,21 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
     ///
-    pub async fn waveform_up_multi_channel(
+    pub async fn waveform_up_multi_channel<W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'_, impl super::UpDma<T>>,
         starting_channel: Channel,
         ending_channel: Channel,
-        duty: &[u16],
+        duty: &[W],
     ) {
+        [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
+            .iter()
+            .filter(|ch| ch.index() >= starting_channel.index())
+            .filter(|ch| ch.index() <= ending_channel.index())
+            .for_each(|ch| {
+                self.inner.enable_channel(*ch, true);
+                self.inner.clamp_compare_value::<W>(*ch);
+            });
         self.inner.enable_update_dma(true);
         self.inner
             .setup_update_dma_burst(dma, starting_channel, ending_channel, duty)
@@ -401,11 +433,11 @@ impl<'d, T: GeneralInstance4Channel> embedded_hal_1::pwm::ErrorType for SimplePw
 
 impl<'d, T: GeneralInstance4Channel> embedded_hal_1::pwm::SetDutyCycle for SimplePwmChannel<'d, T> {
     fn max_duty_cycle(&self) -> u16 {
-        self.max_duty_cycle()
+        unwrap!(self.max_duty_cycle().try_into())
     }
 
     fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
-        self.set_duty_cycle(duty);
+        self.set_duty_cycle(duty.into());
         Ok(())
     }
 
@@ -420,7 +452,7 @@ impl<'d, T: GeneralInstance4Channel> embedded_hal_1::pwm::SetDutyCycle for Simpl
     }
 
     fn set_duty_cycle_fraction(&mut self, num: u16, denom: u16) -> Result<(), Self::Error> {
-        self.set_duty_cycle_fraction(num, denom);
+        self.set_duty_cycle_fraction(num.into(), denom.into());
         Ok(())
     }
 
@@ -448,16 +480,16 @@ impl<'d, T: GeneralInstance4Channel> embedded_hal_02::Pwm for SimplePwm<'d, T> {
     }
 
     fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
-        self.inner.get_compare_value(channel)
+        self.inner.get_compare_value(channel).into()
     }
 
     fn get_max_duty(&self) -> Self::Duty {
-        self.inner.get_max_compare_value() + 1
+        self.inner.get_max_compare_value().into() + 1
     }
 
     fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
         assert!(duty <= self.max_duty_cycle() as u32);
-        self.inner.set_compare_value(channel, duty)
+        self.inner.set_compare_value(channel, unwrap!(duty.try_into()))
     }
 
     fn set_period<P>(&mut self, period: P)
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 8047d6005..d2c361c61 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -491,7 +491,7 @@ impl<'d> UartTx<'d, Async> {
 
     /// Initiate an asynchronous UART write
     pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
-        let _ = self.info.rcc.block_stop();
+        let _scoped_block_stop = self.info.rcc.block_stop();
 
         let r = self.info.regs;
 
@@ -510,7 +510,7 @@ impl<'d> UartTx<'d, Async> {
 
     /// Wait until transmission complete
     pub async fn flush(&mut self) -> Result<(), Error> {
-        let _ = self.info.rcc.block_stop();
+        let _scoped_block_stop = self.info.rcc.block_stop();
 
         flush(&self.info, &self.state).await
     }
@@ -730,7 +730,7 @@ impl<'d> UartRx<'d, Async> {
 
     /// Initiate an asynchronous UART read
     pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
-        let _ = self.info.rcc.block_stop();
+        let _scoped_block_stop = self.info.rcc.block_stop();
 
         self.inner_read(buffer, false).await?;
 
@@ -739,7 +739,7 @@ impl<'d> UartRx<'d, Async> {
 
     /// Initiate an asynchronous read with idle line detection enabled
     pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
-        let _ = self.info.rcc.block_stop();
+        let _scoped_block_stop = self.info.rcc.block_stop();
 
         self.inner_read(buffer, true).await
     }
diff --git a/embassy-time/src/timer.rs b/embassy-time/src/timer.rs
index 2f5967c63..e6d1aed84 100644
--- a/embassy-time/src/timer.rs
+++ b/embassy-time/src/timer.rs
@@ -253,7 +253,7 @@ impl Ticker {
     }
 
     /// Reset the ticker at the deadline.
-    /// If the deadline is in the past, the ticker will fire instantly.
+    /// If the deadline is in the past, the ticker will fire before the next scheduled tick.
     pub fn reset_at(&mut self, deadline: Instant) {
         self.expires_at = deadline + self.duration;
     }
diff --git a/embassy-usb/CHANGELOG.md b/embassy-usb/CHANGELOG.md
index 3dd71ffbc..431f4ddde 100644
--- a/embassy-usb/CHANGELOG.md
+++ b/embassy-usb/CHANGELOG.md
@@ -10,6 +10,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 - Add support for USB HID Boot Protocol Mode 
 - Bump usbd-hid from 0.8.1 to 0.9.0
+- Fix a bug where CDC ACM BufferedReceiver repeats data when its future is dropped
+- Expose `dtr()` and `rts()` on `cdc_acm::ControlChanged`
 
 ## 0.5.1 - 2025-08-26
 
diff --git a/embassy-usb/src/class/cdc_acm.rs b/embassy-usb/src/class/cdc_acm.rs
index 388e21fbd..ab2311f4e 100644
--- a/embassy-usb/src/class/cdc_acm.rs
+++ b/embassy-usb/src/class/cdc_acm.rs
@@ -366,6 +366,16 @@ impl<'d> ControlChanged<'d> {
     pub async fn control_changed(&self) {
         self.control.changed().await;
     }
+
+    /// Gets the DTR (data terminal ready) state
+    pub fn dtr(&self) -> bool {
+        self.control.dtr.load(Ordering::Relaxed)
+    }
+
+    /// Gets the RTS (request to send) state
+    pub fn rts(&self) -> bool {
+        self.control.rts.load(Ordering::Relaxed)
+    }
 }
 
 /// CDC ACM class packet sender.
@@ -545,9 +555,12 @@ impl<'d, D: Driver<'d>> embedded_io_async::Read for BufferedReceiver<'d, D> {
             return self.receiver.read_packet(buf).await;
         }
 
-        // Otherwise read a packet into the internal buffer, and return some of it to the caller
-        self.start = 0;
+        // Otherwise read a packet into the internal buffer, and return some of it to the caller.
+        //
+        // It's important that `start` and `end` be updated in this order so they're left in a
+        // consistent state if the `read` future is dropped mid-execution, e.g. from a timeout.
         self.end = self.receiver.read_packet(&mut self.buffer).await?;
+        self.start = 0;
         return Ok(self.read_from_buffer(buf));
     }
 }
diff --git a/examples/boot/application/nrf/Cargo.toml b/examples/boot/application/nrf/Cargo.toml
index 55053bc33..79286e295 100644
--- a/examples/boot/application/nrf/Cargo.toml
+++ b/examples/boot/application/nrf/Cargo.toml
@@ -9,7 +9,7 @@ publish = false
 embassy-sync = { version = "0.7.2", path = "../../../../embassy-sync" }
 embassy-executor = { version = "0.9.0", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.5.0", path = "../../../../embassy-time", features = [] }
-embassy-nrf = { version = "0.8.0", path = "../../../../embassy-nrf", features = ["time-driver-rtc1", "gpiote", ] }
+embassy-nrf = { version = "0.8.0", path = "../../../../embassy-nrf", features = ["gpiote", ] }
 embassy-boot = { version = "0.6.1", path = "../../../../embassy-boot", features = [] }
 embassy-boot-nrf = { version = "0.9.0", path = "../../../../embassy-boot-nrf", features = [] }
 embassy-embedded-hal = { version = "0.5.0", path = "../../../../embassy-embedded-hal" }
@@ -33,12 +33,14 @@ defmt = [
       "embassy-boot-nrf/defmt",
       "embassy-sync/defmt",
 ]
+nrf54 = ["embassy-nrf/time-driver-grtc"]
 
 [package.metadata.embassy]
 build = [
-  { target = "thumbv7em-none-eabi", features = ["embassy-nrf/nrf52840", "skip-include"], artifact-dir = "out/examples/boot/nrf52840" },
-  { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9160-ns", "skip-include"], artifact-dir = "out/examples/boot/nrf9160" },
-  { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9120-ns", "skip-include"], artifact-dir = "out/examples/boot/nrf9120" },
-  { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9151-ns", "skip-include"], artifact-dir = "out/examples/boot/nrf9151" },
-  { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9161-ns", "skip-include"], artifact-dir = "out/examples/boot/nrf9161" }
+  { target = "thumbv7em-none-eabi", features = ["embassy-nrf/nrf52840", "embassy-nrf/time-driver-rtc1", "skip-include"], artifact-dir = "out/examples/boot/nrf52840" },
+  { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9160-ns", "embassy-nrf/time-driver-rtc1", "skip-include"], artifact-dir = "out/examples/boot/nrf9160" },
+  { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9120-ns", "embassy-nrf/time-driver-rtc1", "skip-include"], artifact-dir = "out/examples/boot/nrf9120" },
+  { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9151-ns", "embassy-nrf/time-driver-rtc1", "skip-include"], artifact-dir = "out/examples/boot/nrf9151" },
+  { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9161-ns", "embassy-nrf/time-driver-rtc1", "skip-include"], artifact-dir = "out/examples/boot/nrf9161" },
+  { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf54l15-app-s", "nrf54", "skip-include"], artifact-dir = "out/examples/boot/nrf54l15" }
 ]
diff --git a/examples/boot/application/nrf/README.md b/examples/boot/application/nrf/README.md
index 9d6d20336..c92ccb358 100644
--- a/examples/boot/application/nrf/README.md
+++ b/examples/boot/application/nrf/README.md
@@ -22,7 +22,7 @@ cp memory-bl.x ../../bootloader/nrf/memory.x
 # Flash bootloader
 cargo flash --manifest-path ../../bootloader/nrf/Cargo.toml --features embassy-nrf/nrf52840 --target thumbv7em-none-eabi --release --chip nRF52840_xxAA
 # Build 'b'
-cargo build --release --bin b --features embassy-nrf/nrf52840
+cargo build --release --bin b --features embassy-nrf/nrf52840,time-driver-rtc1
 # Generate binary for 'b'
 cargo objcopy --release --bin b --features embassy-nrf/nrf52840 --target thumbv7em-none-eabi -- -O binary b.bin
 ```
diff --git a/examples/boot/application/nrf/src/bin/a.rs b/examples/boot/application/nrf/src/bin/a.rs
index 2c1d1a7bb..035ffe214 100644
--- a/examples/boot/application/nrf/src/bin/a.rs
+++ b/examples/boot/application/nrf/src/bin/a.rs
@@ -23,10 +23,21 @@ static APP_B: &[u8] = include_bytes!("../../b.bin");
 async fn main(_spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
 
+    #[cfg(not(feature = "nrf54"))]
     let mut button = Input::new(p.P0_11, Pull::Up);
+    #[cfg(not(feature = "nrf54"))]
     let mut led = Output::new(p.P0_13, Level::Low, OutputDrive::Standard);
+    #[cfg(not(feature = "nrf54"))]
     let mut led_reverted = Output::new(p.P0_14, Level::High, OutputDrive::Standard);
 
+    // nRF54 DK
+    #[cfg(feature = "nrf54")]
+    let mut button = Input::new(p.P1_13, Pull::Up);
+    #[cfg(feature = "nrf54")]
+    let mut led = Output::new(p.P1_14, Level::Low, OutputDrive::Standard);
+    #[cfg(feature = "nrf54")]
+    let mut led_reverted = Output::new(p.P2_09, Level::High, OutputDrive::Standard);
+
     //let mut led = Output::new(p.P1_10, Level::Low, OutputDrive::Standard);
     //let mut button = Input::new(p.P1_02, Pull::Up);
 
@@ -40,8 +51,12 @@ async fn main(_spawner: Spawner) {
     // the watchdog will cause the device to reset as per its configured timeout in the bootloader.
     // This helps is avoid a situation where new firmware might be bad and block our executor.
     // If firmware is bad in this way then the bootloader will revert to any previous version.
-    let wdt_config = wdt::Config::try_new(&p.WDT).unwrap();
-    let (_wdt, [_wdt_handle]) = match Watchdog::try_new(p.WDT, wdt_config) {
+    #[cfg(feature = "nrf54")]
+    let wdt = p.WDT0;
+    #[cfg(not(feature = "nrf54"))]
+    let wdt = p.WDT;
+    let wdt_config = wdt::Config::try_new(&wdt).unwrap();
+    let (_wdt, [_wdt_handle]) = match Watchdog::try_new(wdt, wdt_config) {
         Ok(x) => x,
         Err(_) => {
             // Watchdog already active with the wrong number of handles, waiting for it to timeout...
@@ -51,11 +66,15 @@ async fn main(_spawner: Spawner) {
         }
     };
 
+    // RRAMC for nRF54
+    #[cfg(feature = "nrf54")]
+    let nvmc = Nvmc::new(p.RRAMC);
+    #[cfg(not(feature = "nrf54"))]
     let nvmc = Nvmc::new(p.NVMC);
     let nvmc = Mutex::new(BlockingAsync::new(nvmc));
 
     let config = FirmwareUpdaterConfig::from_linkerfile(&nvmc, &nvmc);
-    let mut magic = [0; 4];
+    let mut magic = [0; 16];
     let mut updater = FirmwareUpdater::new(config, &mut magic);
     let state = updater.get_state().await.unwrap();
     if state == State::Revert {
diff --git a/examples/boot/application/nrf/src/bin/b.rs b/examples/boot/application/nrf/src/bin/b.rs
index de97b6a22..6718df5a1 100644
--- a/examples/boot/application/nrf/src/bin/b.rs
+++ b/examples/boot/application/nrf/src/bin/b.rs
@@ -10,11 +10,15 @@ use panic_reset as _;
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
+    #[cfg(not(feature = "nrf54"))]
     let mut led = Output::new(p.P0_13, Level::Low, OutputDrive::Standard);
     // let mut led = Output::new(p.P1_10, Level::Low, OutputDrive::Standard);
 
     // nRF91 DK
     // let mut led = Output::new(p.P0_02, Level::Low, OutputDrive::Standard);
+    // nrf54l15 dk
+    #[cfg(feature = "nrf54")]
+    let mut led = Output::new(p.P1_10, Level::Low, OutputDrive::Standard);
 
     loop {
         led.set_high();
diff --git a/examples/boot/bootloader/nrf/Cargo.toml b/examples/boot/bootloader/nrf/Cargo.toml
index 1fea2b7d7..59fc6e4ed 100644
--- a/examples/boot/bootloader/nrf/Cargo.toml
+++ b/examples/boot/bootloader/nrf/Cargo.toml
@@ -27,6 +27,7 @@ defmt = [
 softdevice = [
     "embassy-boot-nrf/softdevice",
 ]
+nrf54 = []
 
 [profile.dev]
 debug = 2
@@ -65,5 +66,6 @@ build = [
   { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9160-ns"] },
   { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9120-ns"] },
   { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9151-ns"] },
-  { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9161-ns"] }
+  { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf9161-ns"] },
+  { target = "thumbv8m.main-none-eabihf", features = ["embassy-nrf/nrf54l15-app-s", "nrf54"] }
 ]
diff --git a/examples/boot/bootloader/nrf/src/main.rs b/examples/boot/bootloader/nrf/src/main.rs
index 76c4c1048..9ba57e81b 100644
--- a/examples/boot/bootloader/nrf/src/main.rs
+++ b/examples/boot/bootloader/nrf/src/main.rs
@@ -28,7 +28,10 @@ fn main() -> ! {
     wdt_config.action_during_sleep = SleepConfig::RUN;
     wdt_config.action_during_debug_halt = HaltConfig::PAUSE;
 
+    #[cfg(not(feature = "nrf54"))]
     let flash = WatchdogFlash::start(Nvmc::new(p.NVMC), p.WDT, wdt_config);
+    #[cfg(feature = "nrf54")]
+    let flash = WatchdogFlash::start(Nvmc::new(p.RRAMC), p.WDT0, wdt_config);
     let flash = Mutex::new(RefCell::new(flash));
 
     let config = BootLoaderConfig::from_linkerfile_blocking(&flash, &flash, &flash);
diff --git a/examples/mcxa/.cargo/config.toml b/examples/mcxa/.cargo/config.toml
new file mode 100644
index 000000000..aedc55b06
--- /dev/null
+++ b/examples/mcxa/.cargo/config.toml
@@ -0,0 +1,17 @@
+[target.thumbv8m.main-none-eabihf]
+runner = 'probe-rs run --chip MCXA276 --preverify --verify --protocol swd --speed 12000'
+
+rustflags = [
+  "-C", "linker=flip-link",
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+  # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
+  # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
+  "-C", "link-arg=--nmagic",
+]
+
+[build]
+target = "thumbv8m.main-none-eabihf" # Cortex-M33
+
+[env]
+DEFMT_LOG = "trace"
diff --git a/examples/mcxa/.gitignore b/examples/mcxa/.gitignore
new file mode 100644
index 000000000..2f7896d1d
--- /dev/null
+++ b/examples/mcxa/.gitignore
@@ -0,0 +1 @@
+target/
diff --git a/examples/mcxa/Cargo.toml b/examples/mcxa/Cargo.toml
new file mode 100644
index 000000000..d07cc4272
--- /dev/null
+++ b/examples/mcxa/Cargo.toml
@@ -0,0 +1,34 @@
+[package]
+name = "embassy-mcxa-examples"
+version = "0.1.0"
+edition = "2021"
+license = "MIT OR Apache-2.0"
+publish = false
+
+[dependencies]
+cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
+cortex-m-rt = { version = "0.7", features = ["set-sp", "set-vtor"] }
+crc = "3.4.0"
+critical-section = "1.2.0"
+defmt = "1.0"
+defmt-rtt = "1.0"
+embassy-embedded-hal = "0.5.0"
+embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false }
+embassy-mcxa = { path = "../../embassy-mcxa", features = ["defmt", "unstable-pac", "time"] }
+embassy-sync = "0.7.2"
+embassy-time = "0.5.0"
+embassy-time-driver = "0.2.1"
+embedded-io-async = "0.6.1"
+heapless = "0.9.2"
+panic-probe = { version = "1.0", features = ["print-defmt"] }
+static_cell = "2.1.1"
+tmp108 = "0.4.0"
+
+[profile.release]
+lto = true # better optimizations
+debug = 2  # enough information for defmt/rtt locations
+
+[package.metadata.embassy]
+build = [
+  { target = "thumbv8m.main-none-eabihf", artifact-dir = "out/examples/mcxa" }
+]
diff --git a/examples/mcxa/build.rs b/examples/mcxa/build.rs
new file mode 100644
index 000000000..f076bba9f
--- /dev/null
+++ b/examples/mcxa/build.rs
@@ -0,0 +1,20 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+
+    // Generate memory.x - put "FLASH" at start of RAM, RAM after "FLASH"
+    // cortex-m-rt expects FLASH for code, RAM for data/bss/stack
+    // Both are in RAM, but separated to satisfy cortex-m-rt's expectations
+    // MCXA256 has 128KB RAM total
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
+
+    println!("cargo:rustc-link-search={}", out.display());
+    println!("cargo:rerun-if-changed=memory.x");
+}
diff --git a/examples/mcxa/memory.x b/examples/mcxa/memory.x
new file mode 100644
index 000000000..315ced58a
--- /dev/null
+++ b/examples/mcxa/memory.x
@@ -0,0 +1,5 @@
+MEMORY
+{
+    FLASH : ORIGIN = 0x00000000, LENGTH = 1M
+    RAM   : ORIGIN = 0x20000000, LENGTH = 128K
+}
diff --git a/examples/mcxa/src/bin/adc_interrupt.rs b/examples/mcxa/src/bin/adc_interrupt.rs
new file mode 100644
index 000000000..5876923a1
--- /dev/null
+++ b/examples/mcxa/src/bin/adc_interrupt.rs
@@ -0,0 +1,73 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use hal::adc::{Adc, InterruptHandler, LpadcConfig, TriggerPriorityPolicy};
+use hal::bind_interrupts;
+use hal::clocks::PoweredClock;
+use hal::clocks::config::Div8;
+use hal::clocks::periph_helpers::{AdcClockSel, Div4};
+use hal::config::Config;
+use hal::pac::adc1::cfg::{Pwrsel, Refsel};
+use hal::pac::adc1::cmdl1::{Adch, Mode};
+use hal::pac::adc1::ctrl::CalAvgs;
+use hal::pac::adc1::tctrl::Tcmd;
+use hal::peripherals::ADC1;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    ADC1 => InterruptHandler<ADC1>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1);
+
+    let p = hal::init(config);
+
+    defmt::info!("ADC interrupt Example");
+
+    let adc_config = LpadcConfig {
+        enable_in_doze_mode: true,
+        conversion_average_mode: CalAvgs::Average128,
+        enable_analog_preliminary: true,
+        power_up_delay: 0x80,
+        reference_voltage_source: Refsel::Option3,
+        power_level_mode: Pwrsel::Lowest,
+        trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed,
+        enable_conv_pause: false,
+        conv_pause_delay: 0,
+        fifo_watermark: 0,
+        power: PoweredClock::NormalEnabledDeepSleepDisabled,
+        source: AdcClockSel::FroLfDiv,
+        div: Div4::no_div(),
+    };
+    let mut adc = Adc::new_async(p.ADC1, p.P1_10, Irqs, adc_config).unwrap();
+
+    adc.do_offset_calibration();
+    adc.do_auto_calibration();
+
+    let mut conv_command_config = adc.get_default_conv_command_config();
+    conv_command_config.channel_number = Adch::SelectCorrespondingChannel8;
+    conv_command_config.conversion_resolution_mode = Mode::Data16Bits;
+    adc.set_conv_command_config(1, &conv_command_config).unwrap();
+
+    let mut conv_trigger_config = adc.get_default_conv_trigger_config();
+    conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1;
+    conv_trigger_config.enable_hardware_trigger = false;
+    adc.set_conv_trigger_config(0, &conv_trigger_config);
+
+    defmt::info!("ADC configuration done...");
+
+    loop {
+        match adc.read().await {
+            Ok(value) => {
+                defmt::info!("*** ADC interrupt TRIGGERED! *** -- value: {}", value);
+            }
+            Err(e) => {
+                defmt::error!("ADC read error: {:?}", e);
+            }
+        }
+    }
+}
diff --git a/examples/mcxa/src/bin/adc_polling.rs b/examples/mcxa/src/bin/adc_polling.rs
new file mode 100644
index 000000000..d048bb56f
--- /dev/null
+++ b/examples/mcxa/src/bin/adc_polling.rs
@@ -0,0 +1,72 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use hal::adc::{Adc, LpadcConfig, TriggerPriorityPolicy};
+use hal::clocks::PoweredClock;
+use hal::clocks::config::Div8;
+use hal::clocks::periph_helpers::{AdcClockSel, Div4};
+use hal::config::Config;
+use hal::pac::adc1::cfg::{Pwrsel, Refsel};
+use hal::pac::adc1::cmdl1::{Adch, Mode};
+use hal::pac::adc1::ctrl::CalAvgs;
+use hal::pac::adc1::tctrl::Tcmd;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+const G_LPADC_RESULT_SHIFT: u32 = 0;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1);
+
+    let p = hal::init(config);
+
+    defmt::info!("=== ADC polling Example ===");
+
+    let adc_config = LpadcConfig {
+        enable_in_doze_mode: true,
+        conversion_average_mode: CalAvgs::Average128,
+        enable_analog_preliminary: true,
+        power_up_delay: 0x80,
+        reference_voltage_source: Refsel::Option3,
+        power_level_mode: Pwrsel::Lowest,
+        trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed,
+        enable_conv_pause: false,
+        conv_pause_delay: 0,
+        fifo_watermark: 0,
+        power: PoweredClock::NormalEnabledDeepSleepDisabled,
+        source: AdcClockSel::FroLfDiv,
+        div: Div4::no_div(),
+    };
+    let adc = Adc::new_blocking(p.ADC1, p.P1_10, adc_config).unwrap();
+
+    adc.do_offset_calibration();
+    adc.do_auto_calibration();
+
+    let mut conv_command_config = adc.get_default_conv_command_config();
+    conv_command_config.channel_number = Adch::SelectCorrespondingChannel8;
+    conv_command_config.conversion_resolution_mode = Mode::Data16Bits;
+    adc.set_conv_command_config(1, &conv_command_config).unwrap();
+
+    let mut conv_trigger_config = adc.get_default_conv_trigger_config();
+    conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1;
+    conv_trigger_config.enable_hardware_trigger = false;
+    adc.set_conv_trigger_config(0, &conv_trigger_config);
+
+    defmt::info!("=== ADC configuration done... ===");
+
+    loop {
+        adc.do_software_trigger(1);
+        let result = loop {
+            match adc.get_conv_result() {
+                Ok(res) => break res,
+                Err(_) => {
+                    // Conversion not ready, continue polling
+                }
+            }
+        };
+        let value = result.conv_value >> G_LPADC_RESULT_SHIFT;
+        defmt::info!("ADC value: {=u16}", value);
+    }
+}
diff --git a/examples/mcxa/src/bin/blinky.rs b/examples/mcxa/src/bin/blinky.rs
new file mode 100644
index 000000000..dd08ec0d9
--- /dev/null
+++ b/examples/mcxa/src/bin/blinky.rs
@@ -0,0 +1,36 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_time::Timer;
+use hal::gpio::{DriveStrength, Level, Output, SlewRate};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    defmt::info!("Blink example");
+
+    let mut red = Output::new(p.P3_18, Level::High, DriveStrength::Normal, SlewRate::Fast);
+    let mut green = Output::new(p.P3_19, Level::High, DriveStrength::Normal, SlewRate::Fast);
+    let mut blue = Output::new(p.P3_21, Level::High, DriveStrength::Normal, SlewRate::Fast);
+
+    loop {
+        defmt::info!("Toggle LEDs");
+
+        red.toggle();
+        Timer::after_millis(250).await;
+
+        red.toggle();
+        green.toggle();
+        Timer::after_millis(250).await;
+
+        green.toggle();
+        blue.toggle();
+        Timer::after_millis(250).await;
+        blue.toggle();
+
+        Timer::after_millis(250).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/button.rs b/examples/mcxa/src/bin/button.rs
new file mode 100644
index 000000000..943edbb15
--- /dev/null
+++ b/examples/mcxa/src/bin/button.rs
@@ -0,0 +1,23 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_time::Timer;
+use hal::gpio::{Input, Pull};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    defmt::info!("Button example");
+
+    // This button is labeled "WAKEUP" on the FRDM-MCXA276
+    // The board already has a 10K pullup
+    let monitor = Input::new(p.P1_7, Pull::Disabled);
+
+    loop {
+        defmt::info!("Pin level is {:?}", monitor.get_level());
+        Timer::after_millis(1000).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/button_async.rs b/examples/mcxa/src/bin/button_async.rs
new file mode 100644
index 000000000..6cc7b62cd
--- /dev/null
+++ b/examples/mcxa/src/bin/button_async.rs
@@ -0,0 +1,29 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_time::Timer;
+use hal::gpio::{Input, Pull};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    defmt::info!("GPIO interrupt example");
+
+    // This button is labeled "WAKEUP" on the FRDM-MCXA276
+    // The board already has a 10K pullup
+    let mut pin = Input::new(p.P1_7, Pull::Disabled);
+
+    let mut press_count = 0u32;
+
+    loop {
+        pin.wait_for_falling_edge().await;
+
+        press_count += 1;
+
+        defmt::info!("Button pressed! Count: {}", press_count);
+        Timer::after_millis(50).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/clkout.rs b/examples/mcxa/src/bin/clkout.rs
new file mode 100644
index 000000000..bfd963540
--- /dev/null
+++ b/examples/mcxa/src/bin/clkout.rs
@@ -0,0 +1,69 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clkout::{ClockOut, ClockOutSel, Config, Div4};
+use embassy_mcxa::clocks::PoweredClock;
+use embassy_mcxa::gpio::{DriveStrength, SlewRate};
+use embassy_mcxa::{Level, Output};
+use embassy_time::Timer;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+/// Demonstrate CLKOUT, using Pin P4.2
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+    let mut pin = p.P4_2;
+    let mut clkout = p.CLKOUT;
+
+    loop {
+        defmt::info!("Set Low...");
+        let mut output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow);
+        Timer::after_millis(500).await;
+
+        defmt::info!("Set High...");
+        output.set_high();
+        Timer::after_millis(400).await;
+
+        defmt::info!("Set Low...");
+        output.set_low();
+        Timer::after_millis(500).await;
+
+        defmt::info!("16k...");
+        // Run Clock Out with the 16K clock
+        let _clock_out = ClockOut::new(
+            clkout.reborrow(),
+            pin.reborrow(),
+            Config {
+                sel: ClockOutSel::Clk16K,
+                div: Div4::no_div(),
+                level: PoweredClock::NormalEnabledDeepSleepDisabled,
+            },
+        )
+        .unwrap();
+
+        Timer::after_millis(3000).await;
+
+        defmt::info!("Set Low...");
+        drop(_clock_out);
+
+        let _output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow);
+        Timer::after_millis(500).await;
+
+        // Run Clock Out with the 12M clock, divided by 3
+        defmt::info!("4M...");
+        let _clock_out = ClockOut::new(
+            clkout.reborrow(),
+            pin.reborrow(),
+            Config {
+                sel: ClockOutSel::Fro12M,
+                div: const { Div4::from_divisor(3).unwrap() },
+                level: PoweredClock::NormalEnabledDeepSleepDisabled,
+            },
+        )
+        .unwrap();
+
+        // Let it run for 3 seconds...
+        Timer::after_millis(3000).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/crc.rs b/examples/mcxa/src/bin/crc.rs
new file mode 100644
index 000000000..0125e625c
--- /dev/null
+++ b/examples/mcxa/src/bin/crc.rs
@@ -0,0 +1,154 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use hal::config::Config;
+use hal::crc::Crc;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+const CCITT_FALSE: crc::Algorithm<u16> = crc::Algorithm {
+    width: 16,
+    poly: 0x1021,
+    init: 0xffff,
+    refin: false,
+    refout: false,
+    xorout: 0,
+    check: 0x29b1,
+    residue: 0x0000,
+};
+
+const POSIX: crc::Algorithm<u32> = crc::Algorithm {
+    width: 32,
+    poly: 0x04c1_1db7,
+    init: 0,
+    refin: false,
+    refout: false,
+    xorout: 0xffff_ffff,
+    check: 0x765e_7680,
+    residue: 0x0000,
+};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let config = Config::default();
+    let mut p = hal::init(config);
+
+    defmt::info!("CRC example");
+
+    let buf_u8 = [0x00u8, 0x11, 0x22, 0x33];
+    let buf_u16 = [0x0000u16, 0x1111, 0x2222, 0x3333];
+    let buf_u32 = [0x0000_0000u32, 0x1111_1111, 0x2222_2222, 0x3333_3333];
+
+    // CCITT False
+
+    let sw_crc = crc::Crc::<u16>::new(&CCITT_FALSE);
+    let mut digest = sw_crc.digest();
+    digest.update(&buf_u8);
+    let sw_sum = digest.finalize();
+
+    let mut crc = Crc::new_ccitt_false(p.CRC0.reborrow());
+    crc.feed(&buf_u8);
+    let sum = crc.finalize();
+    assert_eq!(sum, sw_sum);
+
+    let mut crc = Crc::new_ccitt_false(p.CRC0.reborrow());
+    crc.feed(&buf_u16);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0xa467);
+
+    let mut crc = Crc::new_ccitt_false(p.CRC0.reborrow());
+    crc.feed(&buf_u32);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0xe5c7);
+
+    // Maxim
+
+    let sw_crc = crc::Crc::<u16>::new(&crc::CRC_16_MAXIM_DOW);
+    let mut digest = sw_crc.digest();
+    digest.update(&buf_u8);
+    let sw_sum = digest.finalize();
+
+    let mut crc = Crc::new_maxim(p.CRC0.reborrow());
+    crc.feed(&buf_u8);
+    let sum = crc.finalize();
+    assert_eq!(sum, sw_sum);
+
+    let mut crc = Crc::new_maxim(p.CRC0.reborrow());
+    crc.feed(&buf_u16);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x2afe);
+
+    let mut crc = Crc::new_maxim(p.CRC0.reborrow());
+    crc.feed(&buf_u32);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x17d7);
+
+    // Kermit
+
+    let sw_crc = crc::Crc::<u16>::new(&crc::CRC_16_KERMIT);
+    let mut digest = sw_crc.digest();
+    digest.update(&buf_u8);
+    let sw_sum = digest.finalize();
+
+    let mut crc = Crc::new_kermit(p.CRC0.reborrow());
+    crc.feed(&buf_u8);
+    let sum = crc.finalize();
+    assert_eq!(sum, sw_sum);
+
+    let mut crc = Crc::new_kermit(p.CRC0.reborrow());
+    crc.feed(&buf_u16);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x66eb);
+
+    let mut crc = Crc::new_kermit(p.CRC0.reborrow());
+    crc.feed(&buf_u32);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x75ea);
+
+    // ISO HDLC
+
+    let sw_crc = crc::Crc::<u32>::new(&crc::CRC_32_ISO_HDLC);
+    let mut digest = sw_crc.digest();
+    digest.update(&buf_u8);
+    let sw_sum = digest.finalize();
+
+    let mut crc = Crc::new_iso_hdlc(p.CRC0.reborrow());
+    crc.feed(&buf_u8);
+    let sum = crc.finalize();
+    assert_eq!(sum, sw_sum);
+
+    let mut crc = Crc::new_iso_hdlc(p.CRC0.reborrow());
+    crc.feed(&buf_u16);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x8a61_4178);
+
+    let mut crc = Crc::new_iso_hdlc(p.CRC0.reborrow());
+    crc.feed(&buf_u32);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0xfab5_d04e);
+
+    // POSIX
+
+    let sw_crc = crc::Crc::<u32>::new(&POSIX);
+    let mut digest = sw_crc.digest();
+    digest.update(&buf_u8);
+    let sw_sum = digest.finalize();
+
+    let mut crc = Crc::new_posix(p.CRC0.reborrow());
+    crc.feed(&buf_u8);
+    let sum = crc.finalize();
+
+    assert_eq!(sum, sw_sum);
+
+    let mut crc = Crc::new_posix(p.CRC0.reborrow());
+    crc.feed(&buf_u16);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x6d76_4f58);
+
+    let mut crc = Crc::new_posix(p.CRC0.reborrow());
+    crc.feed(&buf_u32);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x2a5b_cb90);
+
+    defmt::info!("CRC successful");
+}
diff --git a/examples/mcxa/src/bin/dma_mem_to_mem.rs b/examples/mcxa/src/bin/dma_mem_to_mem.rs
new file mode 100644
index 000000000..b38baccb5
--- /dev/null
+++ b/examples/mcxa/src/bin/dma_mem_to_mem.rs
@@ -0,0 +1,118 @@
+//! DMA memory-to-memory transfer example for MCXA276.
+//!
+//! This example demonstrates using DMA to copy data between memory buffers
+//! using the Embassy-style async API with type-safe transfers.
+//!
+//! # Embassy-style features demonstrated:
+//! - `TransferOptions` for configuration
+//! - Type-safe `mem_to_mem<u32>()` method with async `.await`
+//! - `Transfer` Future that can be `.await`ed
+//! - `Word` trait for automatic transfer width detection
+//! - `memset()` method for filling memory with a pattern
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::{DmaChannel, TransferOptions};
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+const BUFFER_LENGTH: usize = 4;
+
+// Buffers in RAM (static mut is automatically placed in .bss/.data)
+static SRC_BUFFER: ConstStaticCell<[u32; BUFFER_LENGTH]> = ConstStaticCell::new([1, 2, 3, 4]);
+static DEST_BUFFER: ConstStaticCell<[u32; BUFFER_LENGTH]> = ConstStaticCell::new([0; BUFFER_LENGTH]);
+static MEMSET_BUFFER: ConstStaticCell<[u32; BUFFER_LENGTH]> = ConstStaticCell::new([0; BUFFER_LENGTH]);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA memory-to-memory example starting...");
+
+    defmt::info!("EDMA memory to memory example begin.");
+
+    let src = SRC_BUFFER.take();
+    let dst = DEST_BUFFER.take();
+    let mst = MEMSET_BUFFER.take();
+
+    defmt::info!("Source Buffer: {=[?]}", src.as_slice());
+    defmt::info!("Destination Buffer (before): {=[?]}", dst.as_slice());
+    defmt::info!("Configuring DMA with Embassy-style API...");
+
+    // Create DMA channel
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+
+    // Configure transfer options (Embassy-style)
+    // TransferOptions defaults to: complete_transfer_interrupt = true
+    let options = TransferOptions::default();
+
+    // =========================================================================
+    // Part 1: Embassy-style async API demonstration (mem_to_mem)
+    // =========================================================================
+    //
+    // Use the new type-safe `mem_to_mem<u32>()` method:
+    // - Automatically determines transfer width from buffer element type (u32)
+    // - Returns a `Transfer` future that can be `.await`ed
+    // - Uses TransferOptions for consistent configuration
+    //
+    // Using async `.await` - the executor can run other tasks while waiting!
+
+    // Perform type-safe memory-to-memory transfer using Embassy-style async API
+    // Using async `.await` - the executor can run other tasks while waiting!
+    let transfer = dma_ch0.mem_to_mem(src, dst, options).unwrap();
+    transfer.await.unwrap();
+
+    defmt::info!("DMA mem-to-mem transfer complete!");
+    defmt::info!("Destination Buffer (after): {=[?]}", dst.as_slice());
+
+    // Verify data
+    if src != dst {
+        defmt::error!("FAIL: mem_to_mem mismatch!");
+    } else {
+        defmt::info!("PASS: mem_to_mem verified.");
+    }
+
+    // =========================================================================
+    // Part 2: memset() demonstration
+    // =========================================================================
+    //
+    // The `memset()` method fills a buffer with a pattern value:
+    // - Fixed source address (pattern is read repeatedly)
+    // - Incrementing destination address
+    // - Uses the same Transfer future pattern
+
+    defmt::info!("--- Demonstrating memset() feature ---");
+
+    defmt::info!("Memset Buffer (before): {=[?]}", mst.as_slice());
+
+    // Fill buffer with a pattern value using DMA memset
+    let pattern: u32 = 0xDEADBEEF;
+    defmt::info!("Filling with pattern 0xDEADBEEF...");
+
+    // Using blocking_wait() for demonstration - also shows non-async usage
+    let transfer = dma_ch0.memset(&pattern, mst, options);
+    transfer.blocking_wait();
+
+    defmt::info!("DMA memset complete!");
+    defmt::info!("Memset Buffer (after): {=[?]}", mst.as_slice());
+
+    // Verify memset result
+    if !mst.iter().all(|&v| v == pattern) {
+        defmt::error!("FAIL: memset mismatch!");
+    } else {
+        defmt::info!("PASS: memset verified.");
+    }
+
+    defmt::info!("=== All DMA tests complete ===");
+}
diff --git a/examples/mcxa/src/bin/dma_scatter_gather_builder.rs b/examples/mcxa/src/bin/dma_scatter_gather_builder.rs
new file mode 100644
index 000000000..30ce20c96
--- /dev/null
+++ b/examples/mcxa/src/bin/dma_scatter_gather_builder.rs
@@ -0,0 +1,130 @@
+//! DMA Scatter-Gather Builder example for MCXA276.
+//!
+//! This example demonstrates using the new `ScatterGatherBuilder` API for
+//! chaining multiple DMA transfers with a type-safe builder pattern.
+//!
+//! # Features demonstrated:
+//! - `ScatterGatherBuilder::new()` for creating a builder
+//! - `add_transfer()` for adding memory-to-memory segments
+//! - `build()` to start the chained transfer
+//! - Automatic TCD linking and ESG bit management
+//!
+//! # Comparison with manual scatter-gather:
+//! The manual approach (see `dma_scatter_gather.rs`) requires:
+//! - Manual TCD pool allocation and alignment
+//! - Manual CSR/ESG/INTMAJOR bit manipulation
+//! - Manual dlast_sga address calculations
+//!
+//! The builder approach handles all of this automatically!
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::{DmaChannel, ScatterGatherBuilder};
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Source buffers (multiple segments)
+static SRC1: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0x11111111, 0x22222222, 0x33333333, 0x44444444]);
+static SRC2: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0xAAAAAAAA, 0xBBBBBBBB, 0xCCCCCCCC, 0xDDDDDDDD]);
+static SRC3: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0x12345678, 0x9ABCDEF0, 0xFEDCBA98, 0x76543210]);
+
+// Destination buffers (one per segment)
+static DST1: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0; 4]);
+static DST2: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0; 4]);
+static DST3: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0; 4]);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA Scatter-Gather Builder example starting...");
+
+    defmt::info!("DMA Scatter-Gather Builder Example");
+    defmt::info!("===================================");
+    let src1 = SRC1.take();
+    let src2 = SRC2.take();
+    let src3 = SRC3.take();
+    let dst1 = DST1.take();
+    let dst2 = DST2.take();
+    let dst3 = DST3.take();
+
+    // Show source buffers
+    defmt::info!("Source buffers:");
+    defmt::info!("  SRC1: {=[?]}", src1.as_slice());
+    defmt::info!("  SRC2: {=[?]}", src2.as_slice());
+    defmt::info!("  SRC3: {=[?]}", src3.as_slice());
+
+    defmt::info!("Destination buffers (before):");
+    defmt::info!("  DST1: {=[?]}", dst1.as_slice());
+    defmt::info!("  DST2: {=[?]}", dst2.as_slice());
+    defmt::info!("  DST3: {=[?]}", dst3.as_slice());
+
+    // Create DMA channel
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+
+    defmt::info!("Building scatter-gather chain with builder API...");
+
+    // =========================================================================
+    // ScatterGatherBuilder API demonstration
+    // =========================================================================
+    //
+    // The builder pattern makes scatter-gather transfers much easier:
+    // 1. Create a builder
+    // 2. Add transfer segments with add_transfer()
+    // 3. Call build() to start the entire chain
+    // No manual TCD manipulation required!
+
+    let mut builder = ScatterGatherBuilder::<u32>::new();
+
+    // Add three transfer segments - the builder handles TCD linking automatically
+    builder.add_transfer(src1, dst1);
+    builder.add_transfer(src2, dst2);
+    builder.add_transfer(src3, dst3);
+
+    defmt::info!("Added 3 transfer segments to chain.");
+    defmt::info!("Starting scatter-gather transfer with .await...");
+
+    // Build and execute the scatter-gather chain
+    // The build() method:
+    // - Links all TCDs together with ESG bit
+    // - Sets INTMAJOR on all TCDs
+    // - Loads the first TCD into hardware
+    // - Returns a Transfer future
+    let transfer = builder.build(&dma_ch0).expect("Failed to build scatter-gather");
+    transfer.blocking_wait();
+
+    defmt::info!("Scatter-gather transfer complete!");
+
+    // Show results
+    defmt::info!("Destination buffers (after):");
+    defmt::info!("  DST1: {=[?]}", dst1.as_slice());
+    defmt::info!("  DST2: {=[?]}", dst2.as_slice());
+    defmt::info!("  DST3: {=[?]}", dst3.as_slice());
+
+    let comps = [(src1, dst1), (src2, dst2), (src3, dst3)];
+
+    // Verify all three segments
+    let mut all_ok = true;
+    for (src, dst) in comps {
+        all_ok &= src == dst;
+    }
+
+    if all_ok {
+        defmt::info!("PASS: All segments verified!");
+    } else {
+        defmt::error!("FAIL: Mismatch detected!");
+    }
+
+    defmt::info!("=== Scatter-Gather Builder example complete ===");
+}
diff --git a/examples/mcxa/src/bin/dma_wrap_transfer.rs b/examples/mcxa/src/bin/dma_wrap_transfer.rs
new file mode 100644
index 000000000..acfd29f08
--- /dev/null
+++ b/examples/mcxa/src/bin/dma_wrap_transfer.rs
@@ -0,0 +1,184 @@
+//! DMA wrap transfer example for MCXA276.
+//!
+//! This example demonstrates using DMA with modulo addressing to wrap around
+//! a source buffer, effectively repeating the source data in the destination.
+//!
+//! # Embassy-style features demonstrated:
+//! - `DmaChannel::is_done()` and `clear_done()` helper methods
+//! - No need to pass register block around
+
+#![no_std]
+#![no_main]
+
+use core::fmt::Write as _;
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::DmaChannel;
+use embassy_mcxa::lpuart::{Blocking, Config, Lpuart, LpuartTx};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Source buffer: 4 words (16 bytes), aligned to 16 bytes for modulo
+#[repr(align(16))]
+struct AlignedSrc([u32; 4]);
+
+static mut SRC: AlignedSrc = AlignedSrc([0; 4]);
+static mut DST: [u32; 8] = [0; 8];
+
+/// Helper to print a buffer to UART
+fn print_buffer(tx: &mut LpuartTx<'_, Blocking>, buf_ptr: *const u32, len: usize) {
+    write!(tx, "{:?}", unsafe { core::slice::from_raw_parts(buf_ptr, len) }).ok();
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA wrap transfer example starting...");
+
+    let config = Config {
+        baudrate_bps: 115_200,
+        ..Default::default()
+    };
+
+    let lpuart = Lpuart::new_blocking(p.LPUART2, p.P2_2, p.P2_3, config).unwrap();
+    let (mut tx, _rx) = lpuart.split();
+
+    tx.blocking_write(b"EDMA wrap transfer example begin.\r\n\r\n").unwrap();
+
+    // Initialize buffers
+    unsafe {
+        SRC.0 = [1, 2, 3, 4];
+        DST = [0; 8];
+    }
+
+    tx.blocking_write(b"Source Buffer:              ").unwrap();
+    print_buffer(&mut tx, unsafe { core::ptr::addr_of!(SRC.0) } as *const u32, 4);
+    tx.blocking_write(b"\r\n").unwrap();
+
+    tx.blocking_write(b"Destination Buffer (before): ").unwrap();
+    print_buffer(&mut tx, core::ptr::addr_of!(DST) as *const u32, 8);
+    tx.blocking_write(b"\r\n").unwrap();
+
+    tx.blocking_write(b"Configuring DMA with Embassy-style API...\r\n")
+        .unwrap();
+
+    // Create DMA channel using Embassy-style API
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+
+    // Configure wrap transfer using direct TCD access:
+    // SRC is 16 bytes (4 * u32). We want to transfer 32 bytes (8 * u32).
+    // SRC modulo is 16 bytes (2^4 = 16) - wraps source address.
+    // DST modulo is 0 (disabled).
+    // This causes the source address to wrap around after 16 bytes,
+    // effectively repeating the source data.
+    unsafe {
+        let t = dma_ch0.tcd();
+
+        // Reset channel state
+        t.ch_csr().write(|w| {
+            w.erq()
+                .disable()
+                .earq()
+                .disable()
+                .eei()
+                .no_error()
+                .ebw()
+                .disable()
+                .done()
+                .clear_bit_by_one()
+        });
+        t.ch_es().write(|w| w.bits(0));
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+
+        // Source/destination addresses
+        t.tcd_saddr()
+            .write(|w| w.saddr().bits(core::ptr::addr_of!(SRC.0) as u32));
+        t.tcd_daddr()
+            .write(|w| w.daddr().bits(core::ptr::addr_of_mut!(DST) as u32));
+
+        // Offsets: both increment by 4 bytes
+        t.tcd_soff().write(|w| w.soff().bits(4));
+        t.tcd_doff().write(|w| w.doff().bits(4));
+
+        // Attributes: 32-bit transfers (size = 2)
+        // SMOD = 4 (2^4 = 16 byte modulo for source), DMOD = 0 (disabled)
+        t.tcd_attr().write(|w| {
+            w.ssize()
+                .bits(2)
+                .dsize()
+                .bits(2)
+                .smod()
+                .bits(4) // Source modulo: 2^4 = 16 bytes
+                .dmod()
+                .bits(0) // Dest modulo: disabled
+        });
+
+        // Transfer 32 bytes total in one minor loop
+        let nbytes = 32u32;
+        t.tcd_nbytes_mloffno().write(|w| w.nbytes().bits(nbytes));
+
+        // Source wraps via modulo, no adjustment needed
+        t.tcd_slast_sda().write(|w| w.slast_sda().bits(0));
+        // Reset dest address after major loop
+        t.tcd_dlast_sga().write(|w| w.dlast_sga().bits(-(nbytes as i32) as u32));
+
+        // Major loop count = 1
+        t.tcd_biter_elinkno().write(|w| w.biter().bits(1));
+        t.tcd_citer_elinkno().write(|w| w.citer().bits(1));
+
+        // Enable interrupt on major loop completion
+        t.tcd_csr().write(|w| w.intmajor().set_bit());
+
+        cortex_m::asm::dsb();
+
+        tx.blocking_write(b"Triggering transfer...\r\n").unwrap();
+        dma_ch0.trigger_start();
+    }
+
+    // Wait for completion using channel helper method
+    while !dma_ch0.is_done() {
+        cortex_m::asm::nop();
+    }
+    unsafe {
+        dma_ch0.clear_done();
+    }
+
+    tx.blocking_write(b"\r\nEDMA wrap transfer example finish.\r\n\r\n")
+        .unwrap();
+    tx.blocking_write(b"Destination Buffer (after):  ").unwrap();
+    print_buffer(&mut tx, core::ptr::addr_of!(DST) as *const u32, 8);
+    tx.blocking_write(b"\r\n\r\n").unwrap();
+
+    // Verify: DST should be [1, 2, 3, 4, 1, 2, 3, 4]
+    let expected = [1u32, 2, 3, 4, 1, 2, 3, 4];
+    let mut mismatch = false;
+    unsafe {
+        for i in 0..8 {
+            if DST[i] != expected[i] {
+                mismatch = true;
+                break;
+            }
+        }
+    }
+
+    if mismatch {
+        tx.blocking_write(b"FAIL: Mismatch detected!\r\n").unwrap();
+        defmt::error!("FAIL: Mismatch detected!");
+    } else {
+        tx.blocking_write(b"PASS: Data verified.\r\n").unwrap();
+        defmt::info!("PASS: Data verified.");
+    }
+
+    loop {
+        cortex_m::asm::wfe();
+    }
+}
diff --git a/examples/mcxa/src/bin/hello.rs b/examples/mcxa/src/bin/hello.rs
new file mode 100644
index 000000000..e371d9413
--- /dev/null
+++ b/examples/mcxa/src/bin/hello.rs
@@ -0,0 +1,119 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use hal::lpuart::{Blocking, Config, Lpuart};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+/// Simple helper to write a byte as hex to UART
+fn write_hex_byte(uart: &mut Lpuart<'_, Blocking>, byte: u8) {
+    const HEX_DIGITS: &[u8] = b"0123456789ABCDEF";
+    let _ = uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]);
+    let _ = uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]);
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("boot");
+
+    // Create UART configuration
+    let config = Config {
+        baudrate_bps: 115_200,
+        ..Default::default()
+    };
+
+    // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX
+    let mut uart = Lpuart::new_blocking(
+        p.LPUART2, // Peripheral
+        p.P2_2,    // TX pin
+        p.P2_3,    // RX pin
+        config,
+    )
+    .unwrap();
+
+    // Print welcome message before any async delays to guarantee early console output
+    uart.write_str_blocking("\r\n=== MCXA276 UART Echo Demo ===\r\n");
+    uart.write_str_blocking("Available commands:\r\n");
+    uart.write_str_blocking("  help     - Show this help\r\n");
+    uart.write_str_blocking("  echo <text> - Echo back the text\r\n");
+    uart.write_str_blocking("  hex <byte> - Display byte in hex (0-255)\r\n");
+    uart.write_str_blocking("Type a command: ");
+
+    let mut buffer = [0u8; 64];
+    let mut buf_idx = 0;
+
+    loop {
+        // Read a byte from UART
+        let byte = uart.read_byte_blocking();
+
+        // Echo the character back
+        if byte == b'\r' || byte == b'\n' {
+            // Enter pressed - process command
+            uart.write_str_blocking("\r\n");
+
+            if buf_idx > 0 {
+                let command = &buffer[0..buf_idx];
+
+                if command == b"help" {
+                    uart.write_str_blocking("Available commands:\r\n");
+                    uart.write_str_blocking("  help     - Show this help\r\n");
+                    uart.write_str_blocking("  echo <text> - Echo back the text\r\n");
+                    uart.write_str_blocking("  hex <byte> - Display byte in hex (0-255)\r\n");
+                } else if command.starts_with(b"echo ") && command.len() > 5 {
+                    uart.write_str_blocking("Echo: ");
+                    uart.write_str_blocking(core::str::from_utf8(&command[5..]).unwrap_or(""));
+                    uart.write_str_blocking("\r\n");
+                } else if command.starts_with(b"hex ") && command.len() > 4 {
+                    // Parse the byte value
+                    let num_str = &command[4..];
+                    if let Ok(num) = parse_u8(num_str) {
+                        uart.write_str_blocking("Hex: 0x");
+                        write_hex_byte(&mut uart, num);
+                        uart.write_str_blocking("\r\n");
+                    } else {
+                        uart.write_str_blocking("Invalid number for hex command\r\n");
+                    }
+                } else if !command.is_empty() {
+                    uart.write_str_blocking("Unknown command: ");
+                    uart.write_str_blocking(core::str::from_utf8(command).unwrap_or(""));
+                    uart.write_str_blocking("\r\n");
+                }
+            }
+
+            // Reset buffer and prompt
+            buf_idx = 0;
+            uart.write_str_blocking("Type a command: ");
+        } else if byte == 8 || byte == 127 {
+            // Backspace
+            if buf_idx > 0 {
+                buf_idx -= 1;
+                uart.write_str_blocking("\x08 \x08"); // Erase character
+            }
+        } else if buf_idx < buffer.len() - 1 {
+            // Regular character
+            buffer[buf_idx] = byte;
+            buf_idx += 1;
+            let _ = uart.write_byte(byte);
+        }
+    }
+}
+
+/// Simple parser for u8 from ASCII bytes
+fn parse_u8(bytes: &[u8]) -> Result<u8, ()> {
+    let mut result = 0u8;
+    for &b in bytes {
+        if b.is_ascii_digit() {
+            result = result.checked_mul(10).ok_or(())?;
+            result = result.checked_add(b - b'0').ok_or(())?;
+        } else {
+            return Err(());
+        }
+    }
+    Ok(result)
+}
diff --git a/examples/mcxa/src/bin/i2c-async.rs b/examples/mcxa/src/bin/i2c-async.rs
new file mode 100644
index 000000000..edcfd5f22
--- /dev/null
+++ b/examples/mcxa/src/bin/i2c-async.rs
@@ -0,0 +1,39 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_time::Timer;
+use hal::bind_interrupts;
+use hal::clocks::config::Div8;
+use hal::config::Config;
+use hal::i2c::InterruptHandler;
+use hal::i2c::controller::{self, I2c, Speed};
+use hal::peripherals::LPI2C3;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+bind_interrupts!(
+    struct Irqs {
+        LPI2C3 => InterruptHandler<LPI2C3>;
+    }
+);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1);
+
+    let p = hal::init(config);
+
+    defmt::info!("I2C example");
+
+    let mut config = controller::Config::default();
+    config.speed = Speed::Standard;
+    let mut i2c = I2c::new_async(p.LPI2C3, p.P3_27, p.P3_28, Irqs, config).unwrap();
+    let mut buf = [0u8; 2];
+
+    loop {
+        i2c.async_write_read(0x48, &[0x00], &mut buf).await.unwrap();
+        defmt::info!("Buffer: {:02x}", buf);
+        Timer::after_secs(1).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/i2c-blocking.rs b/examples/mcxa/src/bin/i2c-blocking.rs
new file mode 100644
index 000000000..0f6c8cbae
--- /dev/null
+++ b/examples/mcxa/src/bin/i2c-blocking.rs
@@ -0,0 +1,31 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_time::Timer;
+use hal::clocks::config::Div8;
+use hal::config::Config;
+use hal::i2c::controller::{self, I2c, Speed};
+use tmp108::Tmp108;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1);
+
+    let p = hal::init(config);
+
+    defmt::info!("I2C example");
+
+    let mut config = controller::Config::default();
+    config.speed = Speed::Standard;
+    let i2c = I2c::new_blocking(p.LPI2C3, p.P3_27, p.P3_28, config).unwrap();
+    let mut tmp = Tmp108::new_with_a0_gnd(i2c);
+
+    loop {
+        let temperature = tmp.temperature().unwrap();
+        defmt::info!("Temperature: {}C", temperature);
+        Timer::after_secs(1).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/i2c-scan-blocking.rs b/examples/mcxa/src/bin/i2c-scan-blocking.rs
new file mode 100644
index 000000000..0197f9b1d
--- /dev/null
+++ b/examples/mcxa/src/bin/i2c-scan-blocking.rs
@@ -0,0 +1,41 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::Input;
+use embassy_mcxa::gpio::Pull;
+use embassy_time::Timer;
+use hal::clocks::config::Div8;
+use hal::config::Config;
+use hal::i2c::controller::{self, I2c, Speed};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1);
+
+    let p = hal::init(config);
+
+    defmt::info!("I2C example");
+
+    let mut config = controller::Config::default();
+    config.speed = Speed::Standard;
+
+    // Note: P0_2 is connected to P1_8 on the FRDM_MCXA276 via a resistor, and
+    // defaults to SWO on the debug peripheral. Explicitly make it a high-z
+    // input.
+    let _pin = Input::new(p.P0_2, Pull::Disabled);
+    let mut i2c = I2c::new_blocking(p.LPI2C2, p.P1_9, p.P1_8, config).unwrap();
+
+    for addr in 0x01..=0x7f {
+        let result = i2c.blocking_write(addr, &[]);
+        if result.is_ok() {
+            defmt::info!("Device found at addr {:02x}", addr);
+        }
+    }
+
+    loop {
+        Timer::after_secs(10).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/lpuart_buffered.rs b/examples/mcxa/src/bin/lpuart_buffered.rs
new file mode 100644
index 000000000..47b56b7c7
--- /dev/null
+++ b/examples/mcxa/src/bin/lpuart_buffered.rs
@@ -0,0 +1,62 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::lpuart::Config;
+use embassy_mcxa::lpuart::buffered::BufferedLpuart;
+use embassy_mcxa::{bind_interrupts, lpuart};
+use embedded_io_async::Write;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver
+bind_interrupts!(struct Irqs {
+    LPUART2 => lpuart::buffered::BufferedInterruptHandler::<hal::peripherals::LPUART2>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    // Configure NVIC for LPUART2
+    hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3);
+
+    // UART configuration (enable both TX and RX)
+    let config = Config {
+        baudrate_bps: 115_200,
+        rx_fifo_watermark: 0,
+        tx_fifo_watermark: 0,
+        ..Default::default()
+    };
+
+    let mut tx_buf = [0u8; 256];
+    let mut rx_buf = [0u8; 256];
+
+    // Create a buffered LPUART2 instance with both TX and RX
+    let mut uart = BufferedLpuart::new(
+        p.LPUART2,
+        p.P2_2, // TX pin
+        p.P2_3, // RX pin
+        Irqs,
+        &mut tx_buf,
+        &mut rx_buf,
+        config,
+    )
+    .unwrap();
+
+    // Split into TX and RX parts
+    let (tx, rx) = uart.split_ref();
+
+    tx.write(b"Hello buffered LPUART.\r\n").await.unwrap();
+    tx.write(b"Type characters to echo them back.\r\n").await.unwrap();
+
+    // Echo loop
+    let mut buf = [0u8; 4];
+    loop {
+        let used = rx.read(&mut buf).await.unwrap();
+        tx.write_all(&buf[..used]).await.unwrap();
+    }
+}
diff --git a/examples/mcxa/src/bin/lpuart_dma.rs b/examples/mcxa/src/bin/lpuart_dma.rs
new file mode 100644
index 000000000..cc86f6a40
--- /dev/null
+++ b/examples/mcxa/src/bin/lpuart_dma.rs
@@ -0,0 +1,68 @@
+//! LPUART DMA example for MCXA276.
+//!
+//! This example demonstrates using DMA for UART TX and RX operations.
+//! It sends a message using DMA, then waits for 16 characters to be received
+//! via DMA and echoes them back.
+//!
+//! The DMA request sources are automatically derived from the LPUART instance type.
+//! DMA clock/reset/init is handled automatically by the HAL.
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::lpuart::{Config, LpuartDma};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("LPUART DMA example starting...");
+
+    // Create UART configuration
+    let config = Config {
+        baudrate_bps: 115_200,
+        ..Default::default()
+    };
+
+    // Create UART instance with DMA channels
+    let mut lpuart = LpuartDma::new(
+        p.LPUART2, // Instance
+        p.P2_2,    // TX pin
+        p.P2_3,    // RX pin
+        p.DMA_CH0, // TX DMA channel
+        p.DMA_CH1, // RX DMA channel
+        config,
+    )
+    .unwrap();
+
+    // Send a message using DMA (DMA request source is automatically derived from LPUART2)
+    let tx_msg = b"Hello from LPUART2 DMA TX!\r\n";
+    lpuart.write_dma(tx_msg).await.unwrap();
+
+    defmt::info!("TX DMA complete");
+
+    // Send prompt
+    let prompt = b"Type 16 characters to echo via DMA:\r\n";
+    lpuart.write_dma(prompt).await.unwrap();
+
+    // Receive 16 characters using DMA
+    let mut rx_buf = [0u8; 16];
+    lpuart.read_dma(&mut rx_buf).await.unwrap();
+
+    defmt::info!("RX DMA complete");
+
+    // Echo back the received data
+    let echo_prefix = b"\r\nReceived: ";
+    lpuart.write_dma(echo_prefix).await.unwrap();
+    lpuart.write_dma(&rx_buf).await.unwrap();
+    let done_msg = b"\r\nDone!\r\n";
+    lpuart.write_dma(done_msg).await.unwrap();
+
+    defmt::info!("Example complete");
+}
diff --git a/examples/mcxa/src/bin/lpuart_polling.rs b/examples/mcxa/src/bin/lpuart_polling.rs
new file mode 100644
index 000000000..b80668834
--- /dev/null
+++ b/examples/mcxa/src/bin/lpuart_polling.rs
@@ -0,0 +1,47 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+use crate::hal::lpuart::{Config, Lpuart};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("boot");
+
+    // Create UART configuration
+    let config = Config {
+        baudrate_bps: 115_200,
+        ..Default::default()
+    };
+
+    // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX
+    let lpuart = Lpuart::new_blocking(
+        p.LPUART2, // Peripheral
+        p.P2_2,    // TX pin
+        p.P2_3,    // RX pin
+        config,
+    )
+    .unwrap();
+
+    // Split into separate TX and RX parts
+    let (mut tx, mut rx) = lpuart.split();
+
+    // Write hello messages
+    tx.blocking_write(b"Hello world.\r\n").unwrap();
+    tx.blocking_write(b"Echoing. Type characters...\r\n").unwrap();
+
+    // Echo loop
+    loop {
+        let mut buf = [0u8; 1];
+        rx.blocking_read(&mut buf).unwrap();
+        tx.blocking_write(&buf).unwrap();
+    }
+}
diff --git a/examples/mcxa/src/bin/lpuart_ring_buffer.rs b/examples/mcxa/src/bin/lpuart_ring_buffer.rs
new file mode 100644
index 000000000..be7fd4534
--- /dev/null
+++ b/examples/mcxa/src/bin/lpuart_ring_buffer.rs
@@ -0,0 +1,115 @@
+//! LPUART Ring Buffer DMA example for MCXA276.
+//!
+//! This example demonstrates using the high-level `LpuartRxDma::setup_ring_buffer()`
+//! API for continuous circular DMA reception from a UART peripheral.
+//!
+//! # Features demonstrated:
+//! - `LpuartRxDma::setup_ring_buffer()` for continuous peripheral-to-memory DMA
+//! - `RingBuffer` for async reading of received data
+//! - Handling of potential overrun conditions
+//! - Half-transfer and complete-transfer interrupts for timely wakeups
+//!
+//! # How it works:
+//! 1. Create an `LpuartRxDma` driver with a DMA channel
+//! 2. Call `setup_ring_buffer()` which handles all low-level DMA configuration
+//! 3. Application asynchronously reads data as it arrives via `ring_buf.read()`
+//! 4. Both half-transfer and complete-transfer interrupts wake the reader
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::lpuart::{Config, LpuartDma, LpuartTxDma};
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Ring buffer for RX - power of 2 is ideal for modulo efficiency
+static RX_RING_BUFFER: ConstStaticCell<[u8; 64]> = ConstStaticCell::new([0; 64]);
+
+/// Helper to write a byte as hex to UART
+fn write_hex<T: embassy_mcxa::lpuart::Instance, C: embassy_mcxa::dma::Channel>(
+    tx: &mut LpuartTxDma<'_, T, C>,
+    byte: u8,
+) {
+    const HEX: &[u8; 16] = b"0123456789ABCDEF";
+    let buf = [HEX[(byte >> 4) as usize], HEX[(byte & 0x0F) as usize]];
+    tx.blocking_write(&buf).ok();
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("LPUART Ring Buffer DMA example starting...");
+
+    // Create UART configuration
+    let config = Config {
+        baudrate_bps: 115_200,
+        ..Default::default()
+    };
+
+    // Create LPUART with DMA support for both TX and RX, then split
+    // This is the proper Embassy pattern - create once, split into TX and RX
+    let lpuart = LpuartDma::new(p.LPUART2, p.P2_2, p.P2_3, p.DMA_CH1, p.DMA_CH0, config).unwrap();
+    let (mut tx, rx) = lpuart.split();
+
+    tx.blocking_write(b"LPUART Ring Buffer DMA Example\r\n").unwrap();
+    tx.blocking_write(b"==============================\r\n\r\n").unwrap();
+
+    tx.blocking_write(b"Setting up circular DMA for UART RX...\r\n")
+        .unwrap();
+
+    let buf = RX_RING_BUFFER.take();
+    // Set up the ring buffer with circular DMA
+    let mut ring_buf = rx.into_ring_dma_rx(buf);
+
+    tx.blocking_write(b"Ring buffer ready! Type characters to see them echoed.\r\n")
+        .unwrap();
+    tx.blocking_write(b"The DMA continuously receives in the background.\r\n\r\n")
+        .unwrap();
+
+    // Main loop: read from ring buffer and echo back
+    let mut read_buf = [0u8; 16];
+    let mut total_received: usize = 0;
+
+    loop {
+        // Async read - waits until data is available
+        match ring_buf.read(&mut read_buf).await {
+            Ok(n) if n > 0 => {
+                total_received += n;
+
+                // Echo back what we received
+                tx.blocking_write(b"RX[").unwrap();
+                for (i, &byte) in read_buf.iter().enumerate().take(n) {
+                    write_hex(&mut tx, byte);
+                    if i < n - 1 {
+                        tx.blocking_write(b" ").unwrap();
+                    }
+                }
+                tx.blocking_write(b"]: ").unwrap();
+                tx.blocking_write(&read_buf[..n]).unwrap();
+                tx.blocking_write(b"\r\n").unwrap();
+
+                defmt::info!("Received {} bytes, total: {}", n, total_received);
+            }
+            Ok(_) => {
+                // No data, shouldn't happen with async read
+            }
+            Err(_) => {
+                // Overrun detected
+                tx.blocking_write(b"ERROR: Ring buffer overrun!\r\n").unwrap();
+                defmt::error!("Ring buffer overrun!");
+                ring_buf.clear();
+            }
+        }
+    }
+}
diff --git a/examples/mcxa/src/bin/raw_dma_channel_link.rs b/examples/mcxa/src/bin/raw_dma_channel_link.rs
new file mode 100644
index 000000000..74785e4f3
--- /dev/null
+++ b/examples/mcxa/src/bin/raw_dma_channel_link.rs
@@ -0,0 +1,278 @@
+//! DMA channel linking example for MCXA276.
+//!
+//! NOTE: this is a "raw dma" example! It exists as a proof of concept, as we don't have
+//! a high-level and safe API for. It should not be taken as typical, recommended, or
+//! stable usage!
+//!
+//! This example demonstrates DMA channel linking (minor and major loop linking):
+//! - Channel 0: Transfers SRC_BUFFER to DEST_BUFFER0, with:
+//!   - Minor Link to Channel 1 (triggers CH1 after each minor loop)
+//!   - Major Link to Channel 2 (triggers CH2 after major loop completes)
+//! - Channel 1: Transfers SRC_BUFFER to DEST_BUFFER1 (triggered by CH0 minor link)
+//! - Channel 2: Transfers SRC_BUFFER to DEST_BUFFER2 (triggered by CH0 major link)
+//!
+//! # Embassy-style features demonstrated:
+//! - `DmaChannel::new()` for channel creation
+//! - `DmaChannel::is_done()` and `clear_done()` helper methods
+//! - Channel linking with `set_minor_link()` and `set_major_link()`
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::DmaChannel;
+use embassy_mcxa::pac;
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Buffers
+static SRC_BUFFER: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([1, 2, 3, 4]);
+static DEST_BUFFER0: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0; 4]);
+static DEST_BUFFER1: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0; 4]);
+static DEST_BUFFER2: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0; 4]);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA channel link example starting...");
+
+    // DMA is initialized during hal::init() - no need to call ensure_init()
+
+    let pac_periphs = unsafe { pac::Peripherals::steal() };
+    let dma0 = &pac_periphs.dma0;
+    let edma = unsafe { &*pac::Edma0Tcd0::ptr() };
+
+    // Clear any residual state
+    for i in 0..3 {
+        let t = edma.tcd(i);
+        t.ch_csr().write(|w| w.erq().disable().done().clear_bit_by_one());
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+        t.ch_es().write(|w| w.err().clear_bit_by_one());
+        t.ch_mux().write(|w| unsafe { w.bits(0) });
+    }
+
+    // Clear Global Halt/Error state
+    dma0.mp_csr().modify(|_, w| {
+        w.halt()
+            .normal_operation()
+            .hae()
+            .normal_operation()
+            .ecx()
+            .normal_operation()
+            .cx()
+            .normal_operation()
+    });
+
+    defmt::info!("EDMA channel link example begin.");
+
+    // Initialize buffers
+    let src = SRC_BUFFER.take();
+    let dst0 = DEST_BUFFER0.take();
+    let dst1 = DEST_BUFFER1.take();
+    let dst2 = DEST_BUFFER2.take();
+
+    defmt::info!("Source Buffer: {=[?]}", src.as_slice());
+    defmt::info!("DEST0 (before): {=[?]}", dst0.as_slice());
+    defmt::info!("DEST1 (before): {=[?]}", dst1.as_slice());
+    defmt::info!("DEST2 (before): {=[?]}", dst2.as_slice());
+
+    defmt::info!("Configuring DMA channels with Embassy-style API...");
+
+    let ch0 = DmaChannel::new(p.DMA_CH0);
+    let ch1 = DmaChannel::new(p.DMA_CH1);
+    let ch2 = DmaChannel::new(p.DMA_CH2);
+
+    // Configure channels using direct TCD access (advanced feature demo)
+    // This example demonstrates channel linking which requires direct TCD manipulation
+
+    // Helper to configure TCD for memory-to-memory transfer
+    // Parameters: channel, src, dst, width, nbytes (minor loop), count (major loop), interrupt
+    #[allow(clippy::too_many_arguments)]
+    unsafe fn configure_tcd(
+        edma: &embassy_mcxa::pac::edma_0_tcd0::RegisterBlock,
+        ch: usize,
+        src: u32,
+        dst: u32,
+        width: u8,
+        nbytes: u32,
+        count: u16,
+        enable_int: bool,
+    ) {
+        let t = edma.tcd(ch);
+
+        // Reset channel state
+        t.ch_csr().write(|w| {
+            w.erq()
+                .disable()
+                .earq()
+                .disable()
+                .eei()
+                .no_error()
+                .ebw()
+                .disable()
+                .done()
+                .clear_bit_by_one()
+        });
+        t.ch_es().write(|w| w.bits(0));
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+
+        // Source/destination addresses
+        t.tcd_saddr().write(|w| w.saddr().bits(src));
+        t.tcd_daddr().write(|w| w.daddr().bits(dst));
+
+        // Offsets: increment by width
+        t.tcd_soff().write(|w| w.soff().bits(width as u16));
+        t.tcd_doff().write(|w| w.doff().bits(width as u16));
+
+        // Attributes: size = log2(width)
+        let size = match width {
+            1 => 0,
+            2 => 1,
+            4 => 2,
+            _ => 0,
+        };
+        t.tcd_attr().write(|w| w.ssize().bits(size).dsize().bits(size));
+
+        // Number of bytes per minor loop
+        t.tcd_nbytes_mloffno().write(|w| w.nbytes().bits(nbytes));
+
+        // Major loop: reset source address after major loop
+        let total_bytes = nbytes * count as u32;
+        t.tcd_slast_sda()
+            .write(|w| w.slast_sda().bits(-(total_bytes as i32) as u32));
+        t.tcd_dlast_sga()
+            .write(|w| w.dlast_sga().bits(-(total_bytes as i32) as u32));
+
+        // Major loop count
+        t.tcd_biter_elinkno().write(|w| w.biter().bits(count));
+        t.tcd_citer_elinkno().write(|w| w.citer().bits(count));
+
+        // Control/status: enable interrupt if requested
+        if enable_int {
+            t.tcd_csr().write(|w| w.intmajor().set_bit());
+        } else {
+            t.tcd_csr().write(|w| w.intmajor().clear_bit());
+        }
+
+        cortex_m::asm::dsb();
+    }
+
+    unsafe {
+        // Channel 0: Transfer 16 bytes total (8 bytes per minor loop, 2 major iterations)
+        // Minor Link -> Channel 1
+        // Major Link -> Channel 2
+        configure_tcd(
+            edma,
+            0,
+            src.as_ptr() as u32,
+            dst0.as_mut_ptr() as u32,
+            4,     // src width
+            8,     // nbytes (minor loop = 2 words)
+            2,     // count (major loop = 2 iterations)
+            false, // no interrupt
+        );
+        ch0.set_minor_link(1); // Link to CH1 after each minor loop
+        ch0.set_major_link(2); // Link to CH2 after major loop
+
+        // Channel 1: Transfer 16 bytes (triggered by CH0 minor link)
+        configure_tcd(
+            edma,
+            1,
+            src.as_ptr() as u32,
+            dst1.as_mut_ptr() as u32,
+            4,
+            16, // full buffer in one minor loop
+            1,  // 1 major iteration
+            false,
+        );
+
+        // Channel 2: Transfer 16 bytes (triggered by CH0 major link)
+        configure_tcd(
+            edma,
+            2,
+            src.as_ptr() as u32,
+            dst2.as_mut_ptr() as u32,
+            4,
+            16,   // full buffer in one minor loop
+            1,    // 1 major iteration
+            true, // enable interrupt
+        );
+    }
+
+    defmt::info!("Triggering Channel 0 (1st minor loop)...");
+
+    // Trigger first minor loop of CH0
+    unsafe {
+        ch0.trigger_start();
+    }
+
+    // Wait for CH1 to complete (triggered by CH0 minor link)
+    while !ch1.is_done() {
+        cortex_m::asm::nop();
+    }
+    unsafe {
+        ch1.clear_done();
+    }
+
+    defmt::info!("CH1 done (via minor link).");
+    defmt::info!("Triggering Channel 0 (2nd minor loop)...");
+
+    // Trigger second minor loop of CH0
+    unsafe {
+        ch0.trigger_start();
+    }
+
+    // Wait for CH0 major loop to complete
+    while !ch0.is_done() {
+        cortex_m::asm::nop();
+    }
+    unsafe {
+        ch0.clear_done();
+    }
+
+    defmt::info!("CH0 major loop done.");
+
+    // Wait for CH2 to complete (triggered by CH0 major link)
+    // Using is_done() instead of AtomicBool - the standard interrupt handler
+    // clears the interrupt flag and wakes wakers, but DONE bit remains set
+    while !ch2.is_done() {
+        cortex_m::asm::nop();
+    }
+    unsafe {
+        ch2.clear_done();
+    }
+
+    defmt::info!("CH2 done (via major link).");
+
+    defmt::info!("EDMA channel link example finish.");
+
+    defmt::info!("DEST0 (after): {=[?]}", dst0.as_slice());
+    defmt::info!("DEST1 (after): {=[?]}", dst1.as_slice());
+    defmt::info!("DEST2 (after): {=[?]}", dst2.as_slice());
+
+    // Verify all buffers match source
+    let mut success = true;
+    for sli in [dst0, dst1, dst2] {
+        success &= sli == src;
+    }
+
+    if success {
+        defmt::info!("PASS: Data verified.");
+    } else {
+        defmt::error!("FAIL: Mismatch detected!");
+    }
+
+    loop {
+        cortex_m::asm::wfe();
+    }
+}
diff --git a/examples/mcxa/src/bin/raw_dma_interleave_transfer.rs b/examples/mcxa/src/bin/raw_dma_interleave_transfer.rs
new file mode 100644
index 000000000..a383b6cf4
--- /dev/null
+++ b/examples/mcxa/src/bin/raw_dma_interleave_transfer.rs
@@ -0,0 +1,141 @@
+//! DMA interleaved transfer example for MCXA276.
+//!
+//! NOTE: this is a "raw dma" example! It exists as a proof of concept, as we don't have
+//! a high-level and safe API for. It should not be taken as typical, recommended, or
+//! stable usage!
+//!
+//! This example demonstrates using DMA with custom source/destination offsets
+//! to interleave data during transfer.
+//!
+//! # Embassy-style features demonstrated:
+//! - `TransferOptions::default()` for configuration (used internally)
+//! - DMA channel with `DmaChannel::new()`
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::DmaChannel;
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+const BUFFER_LENGTH: usize = 16;
+const HALF_BUFF_LENGTH: usize = BUFFER_LENGTH / 2;
+
+// Buffers in RAM
+static SRC_BUFFER: ConstStaticCell<[u32; HALF_BUFF_LENGTH]> = ConstStaticCell::new([0; HALF_BUFF_LENGTH]);
+static DEST_BUFFER: ConstStaticCell<[u32; BUFFER_LENGTH]> = ConstStaticCell::new([0; BUFFER_LENGTH]);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA interleave transfer example starting...");
+
+    defmt::info!("EDMA interleave transfer example begin.");
+
+    // Initialize buffers
+    let src = SRC_BUFFER.take();
+    *src = [1, 2, 3, 4, 5, 6, 7, 8];
+    let dst = DEST_BUFFER.take();
+
+    defmt::info!("Source Buffer: {=[?]}", src.as_slice());
+    defmt::info!("Destination Buffer (before): {=[?]}", dst.as_slice());
+
+    defmt::info!("Configuring DMA with Embassy-style API...");
+
+    // Create DMA channel using Embassy-style API
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+
+    // Configure interleaved transfer using direct TCD access:
+    // - src_offset = 4: advance source by 4 bytes after each read
+    // - dst_offset = 8: advance dest by 8 bytes after each write
+    // This spreads source data across every other word in destination
+    unsafe {
+        let t = dma_ch0.tcd();
+
+        // Reset channel state
+        t.ch_csr().write(|w| {
+            w.erq()
+                .disable()
+                .earq()
+                .disable()
+                .eei()
+                .no_error()
+                .ebw()
+                .disable()
+                .done()
+                .clear_bit_by_one()
+        });
+        t.ch_es().write(|w| w.bits(0));
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+
+        // Source/destination addresses
+        t.tcd_saddr().write(|w| w.saddr().bits(src.as_ptr() as u32));
+        t.tcd_daddr().write(|w| w.daddr().bits(dst.as_mut_ptr() as u32));
+
+        // Custom offsets for interleaving
+        t.tcd_soff().write(|w| w.soff().bits(4)); // src: +4 bytes per read
+        t.tcd_doff().write(|w| w.doff().bits(8)); // dst: +8 bytes per write
+
+        // Attributes: 32-bit transfers (size = 2)
+        t.tcd_attr().write(|w| w.ssize().bits(2).dsize().bits(2));
+
+        // Transfer entire source buffer in one minor loop
+        let nbytes = (HALF_BUFF_LENGTH * 4) as u32;
+        t.tcd_nbytes_mloffno().write(|w| w.nbytes().bits(nbytes));
+
+        // Reset source address after major loop
+        t.tcd_slast_sda().write(|w| w.slast_sda().bits(-(nbytes as i32) as u32));
+        // Destination uses 2x offset, so adjust accordingly
+        let dst_total = (HALF_BUFF_LENGTH * 8) as u32;
+        t.tcd_dlast_sga()
+            .write(|w| w.dlast_sga().bits(-(dst_total as i32) as u32));
+
+        // Major loop count = 1
+        t.tcd_biter_elinkno().write(|w| w.biter().bits(1));
+        t.tcd_citer_elinkno().write(|w| w.citer().bits(1));
+
+        // Enable interrupt on major loop completion
+        t.tcd_csr().write(|w| w.intmajor().set_bit());
+
+        cortex_m::asm::dsb();
+
+        defmt::info!("Triggering transfer...");
+        dma_ch0.trigger_start();
+    }
+
+    // Wait for completion using channel helper method
+    while !dma_ch0.is_done() {
+        cortex_m::asm::nop();
+    }
+    unsafe {
+        dma_ch0.clear_done();
+    }
+
+    defmt::info!("EDMA interleave transfer example finish.");
+    defmt::info!("Destination Buffer (after): {=[?]}", dst.as_slice());
+
+    // Verify: Even indices should match SRC_BUFFER[i/2], odd indices should be 0
+    let mut mismatch = false;
+    let diter = dst.chunks_exact(2);
+    let siter = src.iter();
+    for (ch, src) in diter.zip(siter) {
+        mismatch |= !matches!(ch, [a, 0] if a == src);
+    }
+
+    if mismatch {
+        defmt::error!("FAIL: Mismatch detected!");
+    } else {
+        defmt::info!("PASS: Data verified.");
+    }
+}
diff --git a/examples/mcxa/src/bin/raw_dma_memset.rs b/examples/mcxa/src/bin/raw_dma_memset.rs
new file mode 100644
index 000000000..7b3c06ffa
--- /dev/null
+++ b/examples/mcxa/src/bin/raw_dma_memset.rs
@@ -0,0 +1,129 @@
+//! DMA memset example for MCXA276.
+//!
+//! NOTE: this is a "raw dma" example! It exists as a proof of concept, as we don't have
+//! a high-level and safe API for. It should not be taken as typical, recommended, or
+//! stable usage!
+//!
+//! This example demonstrates using DMA to fill a buffer with a repeated pattern.
+//! The source address stays fixed while the destination increments.
+//!
+//! # Embassy-style features demonstrated:
+//! - `DmaChannel::is_done()` and `clear_done()` helper methods
+//! - No need to pass register block around
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::DmaChannel;
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+const BUFFER_LENGTH: usize = 4;
+
+// Buffers in RAM
+static PATTERN: u32 = 0xDEADBEEF;
+static DEST_BUFFER: ConstStaticCell<[u32; BUFFER_LENGTH]> = ConstStaticCell::new([0; BUFFER_LENGTH]);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA memset example starting...");
+    defmt::info!("EDMA memset example begin.");
+
+    // Initialize buffers
+    let pat = &PATTERN;
+    let dst = DEST_BUFFER.take();
+    defmt::info!("Pattern Value: {=u32}", pat);
+    defmt::info!("Destination Buffer (before): {=[?]}", dst.as_slice());
+    defmt::info!("Configuring DMA with Embassy-style API...");
+
+    // Create DMA channel using Embassy-style API
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+
+    // Configure memset transfer using direct TCD access:
+    // Source stays fixed (soff = 0, reads same pattern repeatedly)
+    // Destination increments (doff = 4)
+    unsafe {
+        let t = dma_ch0.tcd();
+
+        // Reset channel state
+        t.ch_csr().write(|w| {
+            w.erq()
+                .disable()
+                .earq()
+                .disable()
+                .eei()
+                .no_error()
+                .ebw()
+                .disable()
+                .done()
+                .clear_bit_by_one()
+        });
+        t.ch_es().write(|w| w.bits(0));
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+
+        // Source address (pattern) - fixed
+        t.tcd_saddr().write(|w| w.saddr().bits(pat as *const _ as u32));
+        // Destination address - increments
+        t.tcd_daddr().write(|w| w.daddr().bits(dst.as_mut_ptr() as u32));
+
+        // Source offset = 0 (stays fixed), Dest offset = 4 (increments)
+        t.tcd_soff().write(|w| w.soff().bits(0));
+        t.tcd_doff().write(|w| w.doff().bits(4));
+
+        // Attributes: 32-bit transfers (size = 2)
+        t.tcd_attr().write(|w| w.ssize().bits(2).dsize().bits(2));
+
+        // Transfer entire buffer in one minor loop
+        let nbytes = (BUFFER_LENGTH * 4) as u32;
+        t.tcd_nbytes_mloffno().write(|w| w.nbytes().bits(nbytes));
+
+        // Source doesn't need adjustment (stays fixed)
+        t.tcd_slast_sda().write(|w| w.slast_sda().bits(0));
+        // Reset dest address after major loop
+        t.tcd_dlast_sga().write(|w| w.dlast_sga().bits(-(nbytes as i32) as u32));
+
+        // Major loop count = 1
+        t.tcd_biter_elinkno().write(|w| w.biter().bits(1));
+        t.tcd_citer_elinkno().write(|w| w.citer().bits(1));
+
+        // Enable interrupt on major loop completion
+        t.tcd_csr().write(|w| w.intmajor().set_bit());
+
+        cortex_m::asm::dsb();
+
+        defmt::info!("Triggering transfer...");
+        dma_ch0.trigger_start();
+    }
+
+    // Wait for completion using channel helper method
+    while !dma_ch0.is_done() {
+        cortex_m::asm::nop();
+    }
+    unsafe {
+        dma_ch0.clear_done();
+    }
+
+    defmt::info!("EDMA memset example finish.");
+    defmt::info!("Destination Buffer (after): {=[?]}", dst.as_slice());
+
+    // Verify: All elements should equal PATTERN
+    let mismatch = dst.iter().any(|i| *i != *pat);
+
+    if mismatch {
+        defmt::error!("FAIL: Mismatch detected!");
+    } else {
+        defmt::info!("PASS: Data verified.");
+    }
+}
diff --git a/examples/mcxa/src/bin/raw_dma_ping_pong_transfer.rs b/examples/mcxa/src/bin/raw_dma_ping_pong_transfer.rs
new file mode 100644
index 000000000..80df40449
--- /dev/null
+++ b/examples/mcxa/src/bin/raw_dma_ping_pong_transfer.rs
@@ -0,0 +1,244 @@
+//! DMA ping-pong/double-buffer transfer example for MCXA276.
+//!
+//! NOTE: this is a "raw dma" example! It exists as a proof of concept, as we don't have
+//! a high-level and safe API for. It should not be taken as typical, recommended, or
+//! stable usage!
+//!
+//! This example demonstrates two approaches for ping-pong/double-buffering:
+//!
+//! ## Approach 1: Scatter/Gather with linked TCDs (manual)
+//! - Two TCDs link to each other for alternating transfers
+//! - Uses custom handler that delegates to on_interrupt() then signals completion
+//! - Note: With ESG=1, DONE bit is cleared by hardware when next TCD loads,
+//!   so we need an AtomicBool to track completion
+//!
+//! ## Approach 2: Half-transfer interrupt with wait_half() (NEW!)
+//! - Single continuous transfer over entire buffer
+//! - Uses half-transfer interrupt to know when first half is ready
+//! - Application can process first half while second half is being filled
+//!
+//! # Embassy-style features demonstrated:
+//! - `DmaChannel::new()` for channel creation
+//! - Scatter/gather with linked TCDs
+//! - Custom handler that delegates to HAL's `on_interrupt()` (best practice)
+//! - Standard `DmaCh1InterruptHandler` with `bind_interrupts!` macro
+//! - NEW: `wait_half()` for half-transfer interrupt handling
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::{DmaChannel, Tcd, TransferOptions};
+use embassy_mcxa::pac;
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Source and destination buffers for Approach 1 (scatter/gather)
+static SRC: ConstStaticCell<[u32; 8]> = ConstStaticCell::new([1, 2, 3, 4, 5, 6, 7, 8]);
+static DST: ConstStaticCell<[u32; 8]> = ConstStaticCell::new([0; 8]);
+
+// Source and destination buffers for Approach 2 (wait_half)
+static SRC2: ConstStaticCell<[u32; 8]> = ConstStaticCell::new([0xA1, 0xA2, 0xA3, 0xA4, 0xB1, 0xB2, 0xB3, 0xB4]);
+static DST2: ConstStaticCell<[u32; 8]> = ConstStaticCell::new([0; 8]);
+
+// TCD pool for scatter/gather - must be 32-byte aligned
+#[repr(C, align(32))]
+struct TcdPool([Tcd; 2]);
+
+static TCD_POOL: ConstStaticCell<TcdPool> = ConstStaticCell::new(TcdPool(
+    [Tcd {
+        saddr: 0,
+        soff: 0,
+        attr: 0,
+        nbytes: 0,
+        slast: 0,
+        daddr: 0,
+        doff: 0,
+        citer: 0,
+        dlast_sga: 0,
+        csr: 0,
+        biter: 0,
+    }; 2],
+));
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA ping-pong transfer example starting...");
+
+    defmt::info!("EDMA ping-pong transfer example begin.");
+
+    // Initialize buffers
+    let src = SRC.take();
+    let dst = DST.take();
+
+    defmt::info!("Source Buffer: {=[?]}", src.as_slice());
+    defmt::info!("Destination Buffer (before): {=[?]}", dst.as_slice());
+
+    defmt::info!("Configuring ping-pong DMA with Embassy-style API...");
+
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+
+    // Configure ping-pong transfer using direct TCD access:
+    // This sets up TCD0 and TCD1 in RAM, and loads TCD0 into the channel.
+    // TCD0 transfers first half (SRC[0..4] -> DST[0..4]), links to TCD1.
+    // TCD1 transfers second half (SRC[4..8] -> DST[4..8]), links to TCD0.
+    let tcds = &mut TCD_POOL.take().0;
+
+    let half_len = 4usize;
+    let half_bytes = (half_len * 4) as u32;
+
+    unsafe {
+        let tcd0_addr = &tcds[0] as *const _ as u32;
+        let tcd1_addr = &tcds[1] as *const _ as u32;
+
+        // TCD0: First half -> Links to TCD1
+        tcds[0] = Tcd {
+            saddr: src.as_ptr() as u32,
+            soff: 4,
+            attr: 0x0202, // 32-bit src/dst
+            nbytes: half_bytes,
+            slast: 0,
+            daddr: dst.as_mut_ptr() as u32,
+            doff: 4,
+            citer: 1,
+            dlast_sga: tcd1_addr as i32,
+            csr: 0x0012, // ESG | INTMAJOR
+            biter: 1,
+        };
+
+        // TCD1: Second half -> Links to TCD0
+        tcds[1] = Tcd {
+            saddr: src.as_ptr().add(half_len) as u32,
+            soff: 4,
+            attr: 0x0202,
+            nbytes: half_bytes,
+            slast: 0,
+            daddr: dst.as_mut_ptr().add(half_len) as u32,
+            doff: 4,
+            citer: 1,
+            dlast_sga: tcd0_addr as i32,
+            csr: 0x0012,
+            biter: 1,
+        };
+
+        // Load TCD0 into hardware registers
+        dma_ch0.load_tcd(&tcds[0]);
+    }
+
+    defmt::info!("Triggering first half transfer...");
+
+    // Trigger first transfer (first half: SRC[0..4] -> DST[0..4])
+    unsafe {
+        dma_ch0.trigger_start();
+    }
+
+    let tcd = dma_ch0.tcd();
+    // Wait for first half
+    loop {
+        if tcd.tcd_saddr().read().bits() != src.as_ptr() as u32 {
+            break;
+        }
+    }
+
+    defmt::info!("First half transferred.");
+    defmt::info!("Triggering second half transfer...");
+
+    // Trigger second transfer (second half: SRC[4..8] -> DST[4..8])
+    unsafe {
+        dma_ch0.trigger_start();
+    }
+
+    // Wait for second half
+    loop {
+        if tcd.tcd_saddr().read().bits() != unsafe { src.as_ptr().add(half_len) } as u32 {
+            break;
+        }
+    }
+
+    defmt::info!("Second half transferred.");
+
+    defmt::info!("EDMA ping-pong transfer example finish.");
+    defmt::info!("Destination Buffer (after): {=[?]}", dst.as_slice());
+
+    // Verify: DST should match SRC
+    let mismatch = src != dst;
+
+    if mismatch {
+        defmt::error!("FAIL: Approach 1 mismatch detected!");
+    } else {
+        defmt::info!("PASS: Approach 1 data verified.");
+    }
+
+    // =========================================================================
+    // Approach 2: Half-Transfer Interrupt with wait_half() (NEW!)
+    // =========================================================================
+    //
+    // This approach uses a single continuous DMA transfer with half-transfer
+    // interrupt enabled. The wait_half() method allows you to be notified
+    // when the first half of the buffer is complete, so you can process it
+    // while the second half is still being filled.
+    //
+    // Benefits:
+    // - Simpler setup (no TCD pool needed)
+    // - True async/await support
+    // - Good for streaming data processing
+
+    defmt::info!("--- Approach 2: wait_half() demo ---");
+
+    // Enable DMA CH1 interrupt
+    unsafe {
+        cortex_m::peripheral::NVIC::unmask(pac::Interrupt::DMA_CH1);
+    }
+
+    // Initialize approach 2 buffers
+    let src2 = SRC2.take();
+    let dst2 = DST2.take();
+
+    defmt::info!("SRC2: {=[?]}", src2.as_slice());
+
+    let dma_ch1 = DmaChannel::new(p.DMA_CH1);
+
+    // Configure transfer with half-transfer interrupt enabled
+    let mut options = TransferOptions::default();
+    options.half_transfer_interrupt = true; // Enable half-transfer interrupt
+    options.complete_transfer_interrupt = true;
+
+    defmt::info!("Starting transfer with half_transfer_interrupt...");
+
+    // Create the transfer
+    let mut transfer = dma_ch1.mem_to_mem(src2, dst2, options).unwrap();
+
+    // Wait for half-transfer (first 4 elements)
+    defmt::info!("Waiting for first half...");
+    let _ok = transfer.wait_half().await.unwrap();
+
+    defmt::info!("Half-transfer complete!");
+
+    // Wait for complete transfer
+    defmt::info!("Waiting for second half...");
+    transfer.await.unwrap();
+
+    defmt::info!("Transfer complete! Full DST2: {=[?]}", dst2.as_slice());
+
+    // Verify approach 2
+    let mismatch2 = src2 != dst2;
+
+    if mismatch2 {
+        defmt::error!("FAIL: Approach 2 mismatch!");
+    } else {
+        defmt::info!("PASS: Approach 2 verified.");
+    }
+
+    defmt::info!("=== All ping-pong demos complete ===");
+}
diff --git a/examples/mcxa/src/bin/raw_dma_scatter_gather.rs b/examples/mcxa/src/bin/raw_dma_scatter_gather.rs
new file mode 100644
index 000000000..eb9960764
--- /dev/null
+++ b/examples/mcxa/src/bin/raw_dma_scatter_gather.rs
@@ -0,0 +1,165 @@
+//! DMA scatter-gather transfer example for MCXA276.
+//!
+//! NOTE: this is a "raw dma" example! It exists as a proof of concept, as we don't have
+//! a high-level and safe API for. It should not be taken as typical, recommended, or
+//! stable usage!
+//!
+//! This example demonstrates using DMA with scatter/gather to chain multiple
+//! transfer descriptors. The first TCD transfers the first half of the buffer,
+//! then automatically loads the second TCD to transfer the second half.
+//!
+//! # Embassy-style features demonstrated:
+//! - `DmaChannel::new()` for channel creation
+//! - Scatter/gather with chained TCDs
+//! - Custom handler that delegates to HAL's `on_interrupt()` (best practice)
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::{DmaChannel, Tcd};
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Source and destination buffers
+static SRC: ConstStaticCell<[u32; 12]> = ConstStaticCell::new([1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]);
+static DST: ConstStaticCell<[u32; 12]> = ConstStaticCell::new([0; 12]);
+
+// TCD pool for scatter/gather - must be 32-byte aligned
+#[repr(C, align(32))]
+struct TcdPool([Tcd; 2]);
+
+static TCD_POOL: ConstStaticCell<TcdPool> = ConstStaticCell::new(TcdPool(
+    [Tcd {
+        saddr: 0,
+        soff: 0,
+        attr: 0,
+        nbytes: 0,
+        slast: 0,
+        daddr: 0,
+        doff: 0,
+        citer: 0,
+        dlast_sga: 0,
+        csr: 0,
+        biter: 0,
+    }; 2],
+));
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA scatter-gather transfer example starting...");
+
+    defmt::info!("EDMA scatter-gather transfer example begin.");
+
+    // Initialize buffers
+    let src = SRC.take();
+    let dst = DST.take();
+
+    defmt::info!("Source Buffer: {=[?]}", src.as_slice());
+    defmt::info!("Destination Buffer (before): {=[?]}", dst.as_slice());
+    defmt::info!("Configuring scatter-gather DMA with Embassy-style API...");
+
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+    let src_ptr = src.as_ptr();
+    let dst_ptr = dst.as_mut_ptr();
+
+    // Configure scatter-gather transfer using direct TCD access:
+    // This sets up TCD0 and TCD1 in RAM, and loads TCD0 into the channel.
+    // TCD0 transfers first half (SRC[0..4] -> DST[0..4]), then loads TCD1.
+    // TCD1 transfers second half (SRC[4..12] -> DST[4..12]), last TCD.
+    unsafe {
+        let tcds = &mut TCD_POOL.take().0;
+
+        // In the first transfer, copy
+        tcds[0] = Tcd {
+            saddr: src_ptr as u32,
+            soff: 4,
+            attr: 0x0202, // 32-bit src/dst
+            nbytes: 4 * 4,
+            slast: 0,
+            daddr: dst_ptr as u32,
+            doff: 4,
+            citer: 1,
+            dlast_sga: tcds.as_ptr().add(1) as i32,
+            // ESG (scatter/gather) for non-last, INTMAJOR for all
+            csr: 0x0012,
+            biter: 1,
+        };
+
+        tcds[1] = Tcd {
+            saddr: src_ptr.add(4) as u32,
+            soff: 4,
+            attr: 0x0202, // 32-bit src/dst
+            nbytes: 8 * 4,
+            slast: 0,
+            daddr: dst_ptr.add(4) as u32,
+            doff: 4,
+            citer: 1,
+            dlast_sga: 0,
+            // ESG (scatter/gather) for non-last, INTMAJOR for all
+            csr: 0x0002,
+            biter: 1,
+        };
+
+        // Load TCD0 into hardware registers
+        dma_ch0.load_tcd(&tcds[0]);
+    }
+
+    defmt::info!("Triggering first half transfer...");
+
+    let tcd = dma_ch0.tcd();
+
+    // Trigger first transfer (first half: SRC[0..4] -> DST[0..4])
+    // TCD0 is currently loaded.
+    unsafe {
+        dma_ch0.trigger_start();
+    }
+
+    // Wait for first half
+    loop {
+        if tcd.tcd_saddr().read().bits() != src_ptr as u32 {
+            defmt::info!("saddr: {=u32}", tcd.tcd_saddr().read().bits());
+            defmt::info!("srptr: {=u32}", src_ptr as u32);
+            break;
+        }
+    }
+
+    defmt::info!("First half transferred.");
+    defmt::info!("Triggering second half transfer...");
+
+    // Trigger second transfer (second half: SRC[4..8] -> DST[4..8])
+    // TCD1 should have been loaded by the scatter/gather engine.
+    unsafe {
+        dma_ch0.trigger_start();
+    }
+
+    // Wait for second half
+    while !dma_ch0.is_done() {
+        cortex_m::asm::nop();
+    }
+
+    defmt::info!("Second half transferred.");
+
+    defmt::info!("EDMA scatter-gather transfer example finish.");
+    defmt::info!("Destination Buffer (after): {=[?]}", dst.as_slice());
+
+    // Verify: DST should match SRC
+    let mismatch = src != dst;
+
+    if mismatch {
+        defmt::error!("FAIL: Mismatch detected!");
+    } else {
+        defmt::info!("PASS: Data verified.");
+    }
+}
diff --git a/examples/mcxa/src/bin/rtc_alarm.rs b/examples/mcxa/src/bin/rtc_alarm.rs
new file mode 100644
index 000000000..fe355888b
--- /dev/null
+++ b/examples/mcxa/src/bin/rtc_alarm.rs
@@ -0,0 +1,47 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::bind_interrupts;
+use hal::rtc::{InterruptHandler, Rtc, RtcDateTime};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    RTC => InterruptHandler<hal::rtc::Rtc0>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    defmt::info!("=== RTC Alarm Example ===");
+
+    let rtc_config = hal::rtc::get_default_config();
+
+    let mut rtc = Rtc::new(p.RTC0, Irqs, rtc_config);
+
+    let now = RtcDateTime {
+        year: 2025,
+        month: 10,
+        day: 15,
+        hour: 14,
+        minute: 30,
+        second: 0,
+    };
+
+    rtc.stop();
+
+    defmt::info!("Time set to: 2025-10-15 14:30:00");
+    rtc.set_datetime(now);
+
+    let mut alarm = now;
+    alarm.second += 10;
+
+    defmt::info!("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)");
+    defmt::info!("RTC started, waiting for alarm...");
+
+    rtc.wait_for_alarm(alarm).await;
+    defmt::info!("*** ALARM TRIGGERED! ***");
+
+    defmt::info!("Example complete - Test PASSED!");
+}
diff --git a/examples/nrf54lm20/.cargo/config.toml b/examples/nrf54lm20/.cargo/config.toml
new file mode 100644
index 000000000..0ffebed14
--- /dev/null
+++ b/examples/nrf54lm20/.cargo/config.toml
@@ -0,0 +1,9 @@
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# Note: it needs the latest git version of probe-rs
+runner = "probe-rs run --chip nrf54lm20a"
+
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[env]
+DEFMT_LOG = "trace"
diff --git a/examples/nrf54lm20/Cargo.toml b/examples/nrf54lm20/Cargo.toml
new file mode 100644
index 000000000..5482fc77a
--- /dev/null
+++ b/examples/nrf54lm20/Cargo.toml
@@ -0,0 +1,37 @@
+[package]
+edition = "2024"
+name = "embassy-nrf54lm20-examples"
+version = "0.1.0"
+license = "MIT OR Apache-2.0"
+publish = false
+
+[dependencies]
+embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
+embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
+embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
+embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
+embassy-nrf = { version = "0.8.0", path = "../../embassy-nrf", features = ["defmt", "nrf54lm20-app-s", "time-driver-grtc", "gpiote", "unstable-pac", "time"] }
+embedded-io = { version = "0.6.0", features = ["defmt-03"]  }
+embedded-io-async = { version = "0.6.1", features = ["defmt-03"] }
+
+rand = { version = "0.9.0", default-features = false }
+
+defmt = "1.0.1"
+defmt-rtt = "1.0.0"
+panic-probe = { version = "1.0.0", features = ["print-defmt"] }
+
+cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7.0"
+
+embedded-storage = "0.3.1"
+portable-atomic = "1"
+
+static_cell = "2"
+
+[profile.release]
+debug = 2
+
+[package.metadata.embassy]
+build = [
+  { target = "thumbv8m.main-none-eabihf", artifact-dir = "out/examples/nrf54lm20" }
+]
diff --git a/examples/nrf54lm20/build.rs b/examples/nrf54lm20/build.rs
new file mode 100644
index 000000000..30691aa97
--- /dev/null
+++ b/examples/nrf54lm20/build.rs
@@ -0,0 +1,35 @@
+//! This build script copies the `memory.x` file from the crate root into
+//! a directory where the linker can always find it at build time.
+//! For many projects this is optional, as the linker always searches the
+//! project root directory -- wherever `Cargo.toml` is. However, if you
+//! are using a workspace or have a more complicated build setup, this
+//! build script becomes required. Additionally, by requesting that
+//! Cargo re-run the build script whenever `memory.x` is changed,
+//! updating `memory.x` ensures a rebuild of the application with the
+//! new memory settings.
+
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    // Put `memory.x` in our output directory and ensure it's
+    // on the linker search path.
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    // By default, Cargo will re-run a build script whenever
+    // any file in the project changes. By specifying `memory.x`
+    // here, we ensure the build script is only re-run when
+    // `memory.x` is changed.
+    println!("cargo:rerun-if-changed=memory.x");
+
+    println!("cargo:rustc-link-arg-bins=--nmagic");
+    println!("cargo:rustc-link-arg-bins=-Tlink.x");
+    println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
+}
diff --git a/examples/nrf54lm20/memory.x b/examples/nrf54lm20/memory.x
new file mode 100644
index 000000000..564f488ac
--- /dev/null
+++ b/examples/nrf54lm20/memory.x
@@ -0,0 +1,5 @@
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 2036K
+  RAM : ORIGIN = 0x20000000, LENGTH = 512K
+}
diff --git a/examples/nrf54lm20/src/bin/blinky.rs b/examples/nrf54lm20/src/bin/blinky.rs
new file mode 100644
index 000000000..962e9f5a6
--- /dev/null
+++ b/examples/nrf54lm20/src/bin/blinky.rs
@@ -0,0 +1,23 @@
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_nrf::gpio::{Level, Output, OutputDrive};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_nrf::init(Default::default());
+    let mut led = Output::new(p.P1_22, Level::Low, OutputDrive::HighDrive);
+
+    loop {
+        info!("high!");
+        led.set_high();
+        Timer::after_millis(300).await;
+        info!("low!");
+        led.set_low();
+        Timer::after_millis(300).await;
+    }
+}
diff --git a/examples/nrf54lm20/src/bin/gpio.rs b/examples/nrf54lm20/src/bin/gpio.rs
new file mode 100644
index 000000000..4b6b4630d
--- /dev/null
+++ b/examples/nrf54lm20/src/bin/gpio.rs
@@ -0,0 +1,23 @@
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_nrf::gpio::{Input, Pull};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_nrf::init(Default::default());
+    let btn = Input::new(p.P1_26, Pull::Up);
+
+    loop {
+        if btn.is_high() {
+            info!("high");
+        } else {
+            info!("low");
+        }
+        Timer::after_millis(100).await;
+    }
+}
diff --git a/examples/nrf54lm20/src/bin/gpiote_channel.rs b/examples/nrf54lm20/src/bin/gpiote_channel.rs
new file mode 100644
index 000000000..0f30f06c7
--- /dev/null
+++ b/examples/nrf54lm20/src/bin/gpiote_channel.rs
@@ -0,0 +1,49 @@
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_nrf::gpio::Pull;
+use embassy_nrf::gpiote::{InputChannel, InputChannelPolarity};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_nrf::init(Default::default());
+    info!("Starting!");
+
+    let mut ch1 = InputChannel::new(p.GPIOTE20_CH0, p.P1_26, Pull::Up, InputChannelPolarity::HiToLo);
+    let mut ch2 = InputChannel::new(p.GPIOTE20_CH1, p.P1_09, Pull::Up, InputChannelPolarity::LoToHi);
+    let mut ch3 = InputChannel::new(p.GPIOTE20_CH2, p.P1_08, Pull::Up, InputChannelPolarity::Toggle);
+    let mut ch4 = InputChannel::new(p.GPIOTE30_CH0, p.P0_05, Pull::Up, InputChannelPolarity::Toggle);
+
+    let button1 = async {
+        loop {
+            ch1.wait().await;
+            info!("Button 1 pressed")
+        }
+    };
+
+    let button2 = async {
+        loop {
+            ch2.wait().await;
+            info!("Button 2 released")
+        }
+    };
+
+    let button3 = async {
+        loop {
+            ch3.wait().await;
+            info!("Button 3 toggled")
+        }
+    };
+
+    let button4 = async {
+        loop {
+            ch4.wait().await;
+            info!("Button 4 toggled")
+        }
+    };
+
+    embassy_futures::join::join4(button1, button2, button3, button4).await;
+}
diff --git a/examples/nrf54lm20/src/bin/gpiote_port.rs b/examples/nrf54lm20/src/bin/gpiote_port.rs
new file mode 100644
index 000000000..6dbd63d92
--- /dev/null
+++ b/examples/nrf54lm20/src/bin/gpiote_port.rs
@@ -0,0 +1,33 @@
+#![no_std]
+#![no_main]
+
+use defmt::{info, unwrap};
+use embassy_executor::Spawner;
+use embassy_nrf::gpio::{Input, Pull};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::task(pool_size = 4)]
+async fn button_task(n: usize, mut pin: Input<'static>) {
+    loop {
+        pin.wait_for_low().await;
+        info!("Button {:?} pressed!", n);
+        pin.wait_for_high().await;
+        info!("Button {:?} released!", n);
+    }
+}
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let p = embassy_nrf::init(Default::default());
+    info!("Starting!");
+
+    let btn1 = Input::new(p.P1_26, Pull::Up);
+    let btn2 = Input::new(p.P1_09, Pull::Up);
+    let btn3 = Input::new(p.P1_08, Pull::Up);
+    let btn4 = Input::new(p.P0_05, Pull::Up);
+
+    spawner.spawn(unwrap!(button_task(1, btn1)));
+    spawner.spawn(unwrap!(button_task(2, btn2)));
+    spawner.spawn(unwrap!(button_task(3, btn3)));
+    spawner.spawn(unwrap!(button_task(4, btn4)));
+}
diff --git a/examples/nrf54lm20/src/bin/timer.rs b/examples/nrf54lm20/src/bin/timer.rs
new file mode 100644
index 000000000..68acc91c1
--- /dev/null
+++ b/examples/nrf54lm20/src/bin/timer.rs
@@ -0,0 +1,30 @@
+#![no_std]
+#![no_main]
+
+use defmt::{info, unwrap};
+use embassy_executor::Spawner;
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::task]
+async fn run1() {
+    loop {
+        info!("BIG INFREQUENT TICK");
+        Timer::after_secs(10).await;
+    }
+}
+
+#[embassy_executor::task]
+async fn run2() {
+    loop {
+        info!("tick");
+        Timer::after_secs(1).await;
+    }
+}
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let _p = embassy_nrf::init(Default::default());
+    spawner.spawn(unwrap!(run1()));
+    spawner.spawn(unwrap!(run2()));
+}
diff --git a/examples/rp235x/src/bin/pio_i2s.rs b/examples/rp235x/src/bin/pio_i2s.rs
index cfcb0221d..7ed952a40 100644
--- a/examples/rp235x/src/bin/pio_i2s.rs
+++ b/examples/rp235x/src/bin/pio_i2s.rs
@@ -5,7 +5,7 @@
 //!   bclk : GPIO 18
 //!   lrc  : GPIO 19
 //!   din  : GPIO 20
-//! Then hold down the boot select button to trigger a rising triangle waveform.
+//! Then short GPIO 0 to GND to trigger a rising triangle waveform.
 
 #![no_std]
 #![no_main]
@@ -70,7 +70,7 @@ async fn main(_spawner: Spawner) {
         // but don't await the returned future, yet
         let dma_future = i2s.write(front_buffer);
 
-        // fade in audio when bootsel is pressed
+        // fade in audio when GPIO 0 pin is shorted to GND
         let fade_target = if fade_input.is_low() { i32::MAX } else { 0 };
 
         // fill back buffer with fresh audio samples before awaiting the dma future
diff --git a/examples/stm32f4/src/bin/pwm_complementary.rs b/examples/stm32f4/src/bin/pwm_complementary.rs
index 50008a37b..5e39a06f5 100644
--- a/examples/stm32f4/src/bin/pwm_complementary.rs
+++ b/examples/stm32f4/src/bin/pwm_complementary.rs
@@ -33,7 +33,7 @@ async fn main(_spawner: Spawner) {
     );
 
     let max = pwm.get_max_duty();
-    pwm.set_dead_time(max / 1024);
+    pwm.set_dead_time((max / 1024) as u16);
 
     pwm.enable(Channel::Ch1);
 
diff --git a/examples/stm32f4/src/bin/sdmmc.rs b/examples/stm32f4/src/bin/sdmmc.rs
index fe0f887bf..098fd6986 100644
--- a/examples/stm32f4/src/bin/sdmmc.rs
+++ b/examples/stm32f4/src/bin/sdmmc.rs
@@ -3,7 +3,8 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::sdmmc::{DataBlock, Sdmmc};
+use embassy_stm32::sdmmc::Sdmmc;
+use embassy_stm32::sdmmc::sd::{CmdBlock, DataBlock, StorageDevice};
 use embassy_stm32::time::{Hertz, mhz};
 use embassy_stm32::{Config, bind_interrupts, peripherals, sdmmc};
 use {defmt_rtt as _, panic_probe as _};
@@ -57,31 +58,24 @@ async fn main(_spawner: Spawner) {
     // Should print 400kHz for initialization
     info!("Configured clock: {}", sdmmc.clock().0);
 
-    let mut err = None;
-    loop {
-        match sdmmc.init_sd_card(mhz(24)).await {
-            Ok(_) => break,
-            Err(e) => {
-                if err != Some(e) {
-                    info!("waiting for card error, retrying: {:?}", e);
-                    err = Some(e);
-                }
-            }
-        }
-    }
+    let mut cmd_block = CmdBlock::new();
+
+    let mut storage = StorageDevice::new_sd_card(&mut sdmmc, &mut cmd_block, mhz(24))
+        .await
+        .unwrap();
 
-    let card = unwrap!(sdmmc.card());
+    let card = storage.card();
 
-    info!("Card: {:#?}", Debug2Format(card));
-    info!("Clock: {}", sdmmc.clock());
+    info!("Card: {:#?}", Debug2Format(&card));
+    info!("Clock: {}", storage.sdmmc.clock());
 
     // Arbitrary block index
     let block_idx = 16;
 
     // SDMMC uses `DataBlock` instead of `&[u8]` to ensure 4 byte alignment required by the hardware.
-    let mut block = DataBlock([0u8; 512]);
+    let mut block = DataBlock::new();
 
-    sdmmc.read_block(block_idx, &mut block).await.unwrap();
+    storage.read_block(block_idx, &mut block).await.unwrap();
     info!("Read: {=[u8]:X}...{=[u8]:X}", block[..8], block[512 - 8..]);
 
     if !ALLOW_WRITES {
@@ -91,17 +85,17 @@ async fn main(_spawner: Spawner) {
 
     info!("Filling block with 0x55");
     block.fill(0x55);
-    sdmmc.write_block(block_idx, &block).await.unwrap();
+    storage.write_block(block_idx, &block).await.unwrap();
     info!("Write done");
 
-    sdmmc.read_block(block_idx, &mut block).await.unwrap();
+    storage.read_block(block_idx, &mut block).await.unwrap();
     info!("Read: {=[u8]:X}...{=[u8]:X}", block[..8], block[512 - 8..]);
 
     info!("Filling block with 0xAA");
     block.fill(0xAA);
-    sdmmc.write_block(block_idx, &block).await.unwrap();
+    storage.write_block(block_idx, &block).await.unwrap();
     info!("Write done");
 
-    sdmmc.read_block(block_idx, &mut block).await.unwrap();
+    storage.read_block(block_idx, &mut block).await.unwrap();
     info!("Read: {=[u8]:X}...{=[u8]:X}", block[..8], block[512 - 8..]);
 }
diff --git a/examples/stm32f4/src/bin/ws2812_pwm.rs b/examples/stm32f4/src/bin/ws2812_pwm.rs
index ccfd0661e..4e556f0d4 100644
--- a/examples/stm32f4/src/bin/ws2812_pwm.rs
+++ b/examples/stm32f4/src/bin/ws2812_pwm.rs
@@ -61,7 +61,7 @@ async fn main(_spawner: Spawner) {
     // construct ws2812 non-return-to-zero (NRZ) code bit by bit
     // ws2812 only need 24 bits for each LED, but we add one bit more to keep PWM output low
 
-    let max_duty = ws2812_pwm.max_duty_cycle();
+    let max_duty = ws2812_pwm.max_duty_cycle() as u16;
     let n0 = 8 * max_duty / 25; // ws2812 Bit 0 high level timing
     let n1 = 2 * n0; // ws2812 Bit 1 high level timing
 
diff --git a/examples/stm32f7/src/bin/sdmmc.rs b/examples/stm32f7/src/bin/sdmmc.rs
index 8809b5d0c..e5d261d89 100644
--- a/examples/stm32f7/src/bin/sdmmc.rs
+++ b/examples/stm32f7/src/bin/sdmmc.rs
@@ -4,6 +4,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::sdmmc::Sdmmc;
+use embassy_stm32::sdmmc::sd::{CmdBlock, StorageDevice};
 use embassy_stm32::time::{Hertz, mhz};
 use embassy_stm32::{Config, bind_interrupts, peripherals, sdmmc};
 use {defmt_rtt as _, panic_probe as _};
@@ -54,9 +55,13 @@ async fn main(_spawner: Spawner) {
     // Should print 400kHz for initialization
     info!("Configured clock: {}", sdmmc.clock().0);
 
-    unwrap!(sdmmc.init_sd_card(mhz(25)).await);
+    let mut cmd_block = CmdBlock::new();
 
-    let card = unwrap!(sdmmc.card());
+    let storage = StorageDevice::new_sd_card(&mut sdmmc, &mut cmd_block, mhz(25))
+        .await
+        .unwrap();
 
-    info!("Card: {:#?}", Debug2Format(card));
+    let card = storage.card();
+
+    info!("Card: {:#?}", Debug2Format(&card));
 }
diff --git a/examples/stm32h5/src/bin/adc_dma.rs b/examples/stm32h5/src/bin/adc_dma.rs
index 2138257f7..e625e3a34 100644
--- a/examples/stm32h5/src/bin/adc_dma.rs
+++ b/examples/stm32h5/src/bin/adc_dma.rs
@@ -66,7 +66,7 @@ async fn adc2_task(
     adc_task(adc, dma, pin1, pin2).await;
 }
 
-async fn adc_task<'a, T: adc::Instance>(
+async fn adc_task<'a, T: adc::DefaultInstance>(
     adc: Peri<'a, T>,
     mut dma: Peri<'a, impl RxDma<T>>,
     pin1: impl AdcChannel<T>,
diff --git a/examples/stm32h7/src/bin/sai.rs b/examples/stm32h7/src/bin/sai.rs
index 847b70c85..0300f83bf 100644
--- a/examples/stm32h7/src/bin/sai.rs
+++ b/examples/stm32h7/src/bin/sai.rs
@@ -63,7 +63,7 @@ async fn main(_spawner: Spawner) {
     tx_config.tx_rx = TxRx::Transmitter;
     tx_config.sync_output = true;
     tx_config.clock_strobe = ClockStrobe::Falling;
-    tx_config.master_clock_divider = Some(mclk_div);
+    tx_config.master_clock_divider = mclk_div;
     tx_config.stereo_mono = StereoMono::Stereo;
     tx_config.data_size = DataSize::Data24;
     tx_config.bit_order = BitOrder::MsbFirst;
diff --git a/examples/stm32h7/src/bin/sdmmc.rs b/examples/stm32h7/src/bin/sdmmc.rs
index 4977fec79..f2e5bedeb 100644
--- a/examples/stm32h7/src/bin/sdmmc.rs
+++ b/examples/stm32h7/src/bin/sdmmc.rs
@@ -4,6 +4,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::sdmmc::Sdmmc;
+use embassy_stm32::sdmmc::sd::{CmdBlock, StorageDevice};
 use embassy_stm32::time::mhz;
 use embassy_stm32::{Config, bind_interrupts, peripherals, sdmmc};
 use {defmt_rtt as _, panic_probe as _};
@@ -13,7 +14,7 @@ bind_interrupts!(struct Irqs {
 });
 
 #[embassy_executor::main]
-async fn main(_spawner: Spawner) -> ! {
+async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
@@ -53,11 +54,13 @@ async fn main(_spawner: Spawner) -> ! {
     // Should print 400kHz for initialization
     info!("Configured clock: {}", sdmmc.clock().0);
 
-    unwrap!(sdmmc.init_sd_card(mhz(25)).await);
+    let mut cmd_block = CmdBlock::new();
 
-    let card = unwrap!(sdmmc.card());
+    let storage = StorageDevice::new_sd_card(&mut sdmmc, &mut cmd_block, mhz(25))
+        .await
+        .unwrap();
 
-    info!("Card: {:#?}", Debug2Format(card));
+    let card = storage.card();
 
-    loop {}
+    info!("Card: {:#?}", Debug2Format(&card));
 }
diff --git a/examples/stm32h723/src/bin/spdifrx.rs b/examples/stm32h723/src/bin/spdifrx.rs
index 5c29602c6..959e2aa18 100644
--- a/examples/stm32h723/src/bin/spdifrx.rs
+++ b/examples/stm32h723/src/bin/spdifrx.rs
@@ -168,7 +168,6 @@ fn new_sai_transmitter<'d>(
     sai_config.slot_enable = 0xFFFF; // All slots
     sai_config.data_size = sai::DataSize::Data32;
     sai_config.frame_length = (CHANNEL_COUNT * 32) as u16;
-    sai_config.master_clock_divider = None;
 
     let (sub_block_tx, _) = hal::sai::split_subblocks(sai);
     Sai::new_asynchronous(sub_block_tx, sck, sd, fs, dma, buf, sai_config)
diff --git a/examples/stm32n6/Cargo.toml b/examples/stm32n6/Cargo.toml
index 5ed28eed1..5ad5b97ce 100644
--- a/examples/stm32n6/Cargo.toml
+++ b/examples/stm32n6/Cargo.toml
@@ -32,6 +32,8 @@ micromath = "2.0.0"
 stm32-fmc = "0.3.0"
 embedded-storage = "0.3.1"
 static_cell = "2"
+hmac = "0.12.1"
+sha2 = { version = "0.10.9", default-features = false }
 
 
 # cargo build/run
diff --git a/examples/stm32n6/src/bin/crc.rs b/examples/stm32n6/src/bin/crc.rs
new file mode 100644
index 000000000..d1b545d5b
--- /dev/null
+++ b/examples/stm32n6/src/bin/crc.rs
@@ -0,0 +1,31 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::crc::{Config, Crc, InputReverseConfig, PolySize};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = embassy_stm32::init(Default::default());
+    info!("Hello World!");
+
+    // Setup for: https://crccalc.com/?crc=Life, it never dieWomen are my favorite guy&method=crc32&datatype=ascii&outtype=0
+    let mut crc = Crc::new(
+        p.CRC,
+        unwrap!(Config::new(
+            InputReverseConfig::Byte,
+            true,
+            PolySize::Width32,
+            0xFFFFFFFF,
+            0x04C11DB7
+        )),
+    );
+
+    let output = crc.feed_bytes(b"Life, it never die\nWomen are my favorite guy") ^ 0xFFFFFFFF;
+
+    defmt::assert_eq!(output, 0x33F0E26B);
+
+    cortex_m::asm::bkpt();
+}
diff --git a/examples/stm32n6/src/bin/hash.rs b/examples/stm32n6/src/bin/hash.rs
new file mode 100644
index 000000000..9f248318f
--- /dev/null
+++ b/examples/stm32n6/src/bin/hash.rs
@@ -0,0 +1,78 @@
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_stm32::hash::*;
+use embassy_stm32::{Config, bind_interrupts, hash, peripherals};
+use embassy_time::Instant;
+use hmac::{Hmac, Mac};
+use sha2::{Digest, Sha256};
+use {defmt_rtt as _, panic_probe as _};
+
+type HmacSha256 = Hmac<Sha256>;
+
+bind_interrupts!(struct Irqs {
+    HASH => hash::InterruptHandler<peripherals::HASH>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+    let config = Config::default();
+    let p = embassy_stm32::init(config);
+
+    let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh";
+    let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr";
+
+    let mut hw_hasher = Hash::new_blocking(p.HASH, Irqs);
+
+    let hw_start_time = Instant::now();
+
+    // Compute a digest in hardware.
+    let mut context = hw_hasher.start(Algorithm::SHA256, DataType::Width8, None);
+    hw_hasher.update_blocking(&mut context, test_1);
+    hw_hasher.update_blocking(&mut context, test_2);
+    let mut hw_digest: [u8; 32] = [0; 32];
+    hw_hasher.finish_blocking(context, &mut hw_digest);
+
+    let hw_end_time = Instant::now();
+    let hw_execution_time = hw_end_time - hw_start_time;
+
+    let sw_start_time = Instant::now();
+
+    // Compute a digest in software.
+    let mut sw_hasher = Sha256::new();
+    sw_hasher.update(test_1);
+    sw_hasher.update(test_2);
+    let sw_digest = sw_hasher.finalize();
+
+    let sw_end_time = Instant::now();
+    let sw_execution_time = sw_end_time - sw_start_time;
+
+    info!("Hardware Digest: {:?}", hw_digest);
+    info!("Software Digest: {:?}", sw_digest[..]);
+    info!("Hardware Execution Time: {:?}", hw_execution_time);
+    info!("Software Execution Time: {:?}", sw_execution_time);
+    assert_eq!(hw_digest, sw_digest[..]);
+
+    let hmac_key: [u8; 64] = [0x55; 64];
+
+    // Compute HMAC in hardware.
+    let mut sha256hmac_context = hw_hasher.start(Algorithm::SHA256, DataType::Width8, Some(&hmac_key));
+    hw_hasher.update_blocking(&mut sha256hmac_context, test_1);
+    hw_hasher.update_blocking(&mut sha256hmac_context, test_2);
+    let mut hw_hmac: [u8; 32] = [0; 32];
+    hw_hasher.finish_blocking(sha256hmac_context, &mut hw_hmac);
+
+    // Compute HMAC in software.
+    let mut sw_mac = HmacSha256::new_from_slice(&hmac_key).unwrap();
+    sw_mac.update(test_1);
+    sw_mac.update(test_2);
+    let sw_hmac = sw_mac.finalize().into_bytes();
+
+    info!("Hardware HMAC: {:?}", hw_hmac);
+    info!("Software HMAC: {:?}", sw_hmac[..]);
+    assert_eq!(hw_hmac, sw_hmac[..]);
+
+    loop {}
+}
diff --git a/examples/stm32wb/Cargo.toml b/examples/stm32wb/Cargo.toml
index 83119e3a0..83f7cb56b 100644
--- a/examples/stm32wb/Cargo.toml
+++ b/examples/stm32wb/Cargo.toml
@@ -26,8 +26,8 @@ static_cell = "2"
 
 [features]
 default = ["ble", "mac"]
-mac = ["embassy-stm32-wpan/mac", "dep:embassy-net"]
-ble = ["embassy-stm32-wpan/ble"]
+mac = ["embassy-stm32-wpan/wb55_mac", "dep:embassy-net"]
+ble = ["embassy-stm32-wpan/wb55_ble"]
 
 [[bin]] 
 name = "tl_mbox_ble"
diff --git a/examples/stm32wba/Cargo.toml b/examples/stm32wba/Cargo.toml
index 3496b41b0..b10114420 100644
--- a/examples/stm32wba/Cargo.toml
+++ b/examples/stm32wba/Cargo.toml
@@ -6,7 +6,8 @@ license = "MIT OR Apache-2.0"
 publish = false
 
 [dependencies]
-embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "stm32wba55cg", "time-driver-any", "memory-x", "exti"]  }
+embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "stm32wba52cg", "time-driver-any", "memory-x", "exti"]  }
+embassy-stm32-wpan = { version = "0.1.0", path = "../../embassy-stm32-wpan", features = ["defmt", "stm32wba52cg"] }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
@@ -22,6 +23,11 @@ panic-probe = { version = "1.0.0", features = ["print-defmt"] }
 heapless = { version = "0.8", default-features = false }
 static_cell = "2"
 
+[features]
+default = ["ble", "mac"]
+mac = ["embassy-stm32-wpan/wba_mac", "dep:embassy-net"]
+ble = ["embassy-stm32-wpan/wba_ble"]
+
 [profile.release]
 debug = 2
 
diff --git a/examples/stm32wba/src/bin/mac_ffd.rs b/examples/stm32wba/src/bin/mac_ffd.rs
new file mode 100644
index 000000000..b15fb3452
--- /dev/null
+++ b/examples/stm32wba/src/bin/mac_ffd.rs
@@ -0,0 +1,58 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::Config;
+use embassy_stm32::rcc::{Sysclk, mux};
+use embassy_stm32_wpan::bindings::mac::ST_MAC_callbacks_t;
+use {defmt_rtt as _, panic_probe as _};
+
+static _MAC_CALLBACKS: ST_MAC_callbacks_t = ST_MAC_callbacks_t {
+    mlmeAssociateCnfCb: None,       // ST_MAC_MLMEAssociateCnfCbPtr,
+    mlmeAssociateIndCb: None,       // ST_MAC_MLMEAssociateIndCbPtr,
+    mlmeBeaconNotifyIndCb: None,    // ST_MAC_MLMEBeaconNotifyIndCbPtr,
+    mlmeCalibrateCnfCb: None,       // ST_MAC_MLMECalibrateCnfCbPtr,
+    mlmeCommStatusIndCb: None,      // ST_MAC_MLMECommStatusIndCbPtr,
+    mlmeDisassociateCnfCb: None,    // ST_MAC_MLMEDisassociateCnfCbPtr,
+    mlmeDisassociateIndCb: None,    // ST_MAC_MLMEDisassociateIndCbPtr,
+    mlmeDpsCnfCb: None,             // ST_MAC_MLMEDpsCnfCbPtr,
+    mlmeDpsIndCb: None,             // ST_MAC_MLMEDpsIndCbPtr,
+    mlmeGetCnfCb: None,             // ST_MAC_MLMEGetCnfCbPtr,
+    mlmeGtsCnfCb: None,             // ST_MAC_MLMEGtsCnfCbPtr,
+    mlmeGtsIndCb: None,             // ST_MAC_MLMEGtsIndCbPtr,
+    mlmeOrphanIndCb: None,          // ST_MAC_MLMEOrphanIndCbPtr,
+    mlmePollCnfCb: None,            // ST_MAC_MLMEPollCnfCbPtr,
+    mlmeResetCnfCb: None,           // ST_MAC_MLMEResetCnfCbPtr,
+    mlmeRxEnableCnfCb: None,        // ST_MAC_MLMERxEnableCnfCbPtr,
+    mlmeScanCnfCb: None,            // ST_MAC_MLMEScanCnfCbPtr,
+    mlmeSetCnfCb: None,             // ST_MAC_MLMESetCnfCbPtr,
+    mlmeSoundingCnfCb: None,        // ST_MAC_MLMESoundingCnfCbPtr,
+    mlmeStartCnfCb: None,           // ST_MAC_MLMEStartCnfCbPtr,
+    mlmeSyncLossIndCb: None,        // ST_MAC_MLMESyncLossIndCbPtr,
+    mcpsDataIndCb: None,            // ST_MAC_MCPSDataIndCbPtr,
+    mcpsDataCnfCb: None,            // ST_MAC_MCPSDataCnfCbPtr,
+    mcpsPurgeCnfCb: None,           // ST_MAC_MCPSPurgeCnfCbPtr,
+    mlmePollIndCb: None,            // ST_MAC_MLMEPollIndCbPtr,
+    mlmeBeaconReqIndCb: None,       // ST_MAC_MLMEBeaconReqIndCbPtr,
+    mlmeBeaconCnfCb: None,          // ST_MAC_MLMEBeaconCnfCbPtr,
+    mlmeGetPwrInfoTableCnfCb: None, // ST_MAC_MLMEGetPwrInfoTableCnfCbPtr,
+    mlmeSetPwrInfoTableCnfCb: None, // ST_MAC_MLMESetPwrInfoTableCnfCbPtr,
+};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+
+    config.rcc.sys = Sysclk::HSI;
+    config.rcc.mux.rngsel = mux::Rngsel::HSI;
+
+    let _p = embassy_stm32::init(config);
+    info!("Hello World!");
+
+    //    let status = unsafe { ST_MAC_init(&_MAC_CALLBACKS as *const _ as *mut _) };
+    //
+    //    info!("mac init: {}", status);
+
+    cortex_m::asm::bkpt();
+}
diff --git a/examples/stm32wba/src/bin/rtc.rs b/examples/stm32wba/src/bin/rtc.rs
new file mode 100644
index 000000000..cef8501e0
--- /dev/null
+++ b/examples/stm32wba/src/bin/rtc.rs
@@ -0,0 +1,62 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::Config;
+use embassy_stm32::rcc::*;
+use embassy_stm32::rtc::{DateTime, DayOfWeek, Rtc, RtcConfig};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+pub fn pll_init(config: &mut Config) {
+    config.rcc.pll1 = Some(embassy_stm32::rcc::Pll {
+        source: PllSource::HSI,
+        prediv: PllPreDiv::DIV1,  // PLLM = 1 → HSI / 1 = 16 MHz
+        mul: PllMul::MUL30,       // PLLN = 30 → 16 MHz * 30 = 480 MHz VCO
+        divr: Some(PllDiv::DIV5), // PLLR = 5 → 96 MHz (Sysclk)
+        // divq: Some(PllDiv::DIV10), // PLLQ = 10 → 48 MHz (NOT USED)
+        divq: None,
+        divp: Some(PllDiv::DIV30), // PLLP = 30 → 16 MHz (USBOTG)
+        frac: Some(0),             // Fractional part (enabled)
+    });
+
+    config.rcc.ahb_pre = AHBPrescaler::DIV1;
+    config.rcc.apb1_pre = APBPrescaler::DIV1;
+    config.rcc.apb2_pre = APBPrescaler::DIV1;
+    config.rcc.apb7_pre = APBPrescaler::DIV1;
+    config.rcc.ahb5_pre = AHB5Prescaler::DIV4;
+
+    // voltage scale for max performance
+    config.rcc.voltage_scale = VoltageScale::RANGE1;
+    // route PLL1_P into the USB‐OTG‐HS block
+    config.rcc.sys = Sysclk::PLL1_R;
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+
+    pll_init(&mut config);
+
+    let p = embassy_stm32::init(config);
+
+    let mut rtc = Rtc::new(p.RTC, RtcConfig::default());
+
+    // Setting datetime
+    let initial_datetime = DateTime::from(1970, 1, 1, DayOfWeek::Thursday, 0, 00, 00, 0).unwrap();
+    match rtc.0.set_datetime(initial_datetime) {
+        Ok(()) => info!("RTC set successfully."),
+        Err(e) => error!("Failed to set RTC date/time: {:?}", e),
+    }
+
+    // Reading datetime every 1s
+    loop {
+        match rtc.1.now() {
+            Ok(result) => info!("{}", result),
+            Err(e) => error!("Failed to set RTC date/time: {:?}", e),
+        }
+
+        Timer::after_millis(1000).await;
+    }
+}
diff --git a/examples/stm32wba6/src/bin/blinky.rs b/examples/stm32wba6/src/bin/blinky.rs
index 0d803b257..95f3339b7 100644
--- a/examples/stm32wba6/src/bin/blinky.rs
+++ b/examples/stm32wba6/src/bin/blinky.rs
@@ -3,16 +3,45 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
+use embassy_stm32::Config;
 use embassy_stm32::gpio::{Level, Output, Speed};
+use embassy_stm32::rcc::{
+    AHB5Prescaler, AHBPrescaler, APBPrescaler, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk, VoltageScale,
+};
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
-    let p = embassy_stm32::init(Default::default());
+    let mut config = Config::default();
+    // Fine-tune PLL1 dividers/multipliers
+    config.rcc.pll1 = Some(embassy_stm32::rcc::Pll {
+        source: PllSource::HSI,
+        prediv: PllPreDiv::DIV1,  // PLLM = 1 → HSI / 1 = 16 MHz
+        mul: PllMul::MUL30,       // PLLN = 30 → 16 MHz * 30 = 480 MHz VCO
+        divr: Some(PllDiv::DIV5), // PLLR = 5 → 96 MHz (Sysclk)
+        // divq: Some(PllDiv::DIV10), // PLLQ = 10 → 48 MHz (NOT USED)
+        divq: None,
+        divp: Some(PllDiv::DIV30), // PLLP = 30 → 16 MHz (USBOTG)
+        frac: Some(0),             // Fractional part (enabled)
+    });
+
+    config.rcc.ahb_pre = AHBPrescaler::DIV1;
+    config.rcc.apb1_pre = APBPrescaler::DIV1;
+    config.rcc.apb2_pre = APBPrescaler::DIV1;
+    config.rcc.apb7_pre = APBPrescaler::DIV1;
+    config.rcc.ahb5_pre = AHB5Prescaler::DIV4;
+
+    // voltage scale for max performance
+    config.rcc.voltage_scale = VoltageScale::RANGE1;
+    // route PLL1_P into the USB‐OTG‐HS block
+    config.rcc.sys = Sysclk::PLL1_R;
+
+    let p = embassy_stm32::init(config);
     info!("Hello World!");
 
-    let mut led = Output::new(p.PB4, Level::High, Speed::Low);
+    // LD2 - PC4
+    let mut led = Output::new(p.PC4, Level::High, Speed::Low);
 
     loop {
         info!("high");
diff --git a/examples/stm32wba6/src/bin/rtc.rs b/examples/stm32wba6/src/bin/rtc.rs
new file mode 100644
index 000000000..cef8501e0
--- /dev/null
+++ b/examples/stm32wba6/src/bin/rtc.rs
@@ -0,0 +1,62 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::Config;
+use embassy_stm32::rcc::*;
+use embassy_stm32::rtc::{DateTime, DayOfWeek, Rtc, RtcConfig};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+pub fn pll_init(config: &mut Config) {
+    config.rcc.pll1 = Some(embassy_stm32::rcc::Pll {
+        source: PllSource::HSI,
+        prediv: PllPreDiv::DIV1,  // PLLM = 1 → HSI / 1 = 16 MHz
+        mul: PllMul::MUL30,       // PLLN = 30 → 16 MHz * 30 = 480 MHz VCO
+        divr: Some(PllDiv::DIV5), // PLLR = 5 → 96 MHz (Sysclk)
+        // divq: Some(PllDiv::DIV10), // PLLQ = 10 → 48 MHz (NOT USED)
+        divq: None,
+        divp: Some(PllDiv::DIV30), // PLLP = 30 → 16 MHz (USBOTG)
+        frac: Some(0),             // Fractional part (enabled)
+    });
+
+    config.rcc.ahb_pre = AHBPrescaler::DIV1;
+    config.rcc.apb1_pre = APBPrescaler::DIV1;
+    config.rcc.apb2_pre = APBPrescaler::DIV1;
+    config.rcc.apb7_pre = APBPrescaler::DIV1;
+    config.rcc.ahb5_pre = AHB5Prescaler::DIV4;
+
+    // voltage scale for max performance
+    config.rcc.voltage_scale = VoltageScale::RANGE1;
+    // route PLL1_P into the USB‐OTG‐HS block
+    config.rcc.sys = Sysclk::PLL1_R;
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+
+    pll_init(&mut config);
+
+    let p = embassy_stm32::init(config);
+
+    let mut rtc = Rtc::new(p.RTC, RtcConfig::default());
+
+    // Setting datetime
+    let initial_datetime = DateTime::from(1970, 1, 1, DayOfWeek::Thursday, 0, 00, 00, 0).unwrap();
+    match rtc.0.set_datetime(initial_datetime) {
+        Ok(()) => info!("RTC set successfully."),
+        Err(e) => error!("Failed to set RTC date/time: {:?}", e),
+    }
+
+    // Reading datetime every 1s
+    loop {
+        match rtc.1.now() {
+            Ok(result) => info!("{}", result),
+            Err(e) => error!("Failed to set RTC date/time: {:?}", e),
+        }
+
+        Timer::after_millis(1000).await;
+    }
+}
diff --git a/fmtall.sh b/fmtall.sh
new file mode 100755
index 000000000..9cadcdbe9
--- /dev/null
+++ b/fmtall.sh
@@ -0,0 +1,13 @@
+#!/bin/bash
+
+set -euo pipefail
+
+# We need the nightly toolchain for this
+mv rust-toolchain-nightly.toml rust-toolchain.toml
+
+# Similar to the CI workflow, but don't just CHECK, actualy DO the formatting
+find . -name '*.rs' -not -path '*target*' | xargs rustfmt --skip-children --unstable-features --edition 2024
+
+# Put the toolchains back, copy back to nightly and do a clean checkout of rust-toolchain
+mv rust-toolchain.toml rust-toolchain-nightly.toml
+git checkout -- rust-toolchain.toml
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index 496a9de18..6ee7f8e84 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -51,8 +51,8 @@ stop = ["embassy-stm32/low-power", "embassy-stm32/low-power-debug-with-sleep"]
 chrono = ["embassy-stm32/chrono", "dep:chrono"]
 can = []
 fdcan = []
-ble = ["dep:embassy-stm32-wpan", "embassy-stm32-wpan/ble"]
-mac = ["dep:embassy-stm32-wpan", "embassy-stm32-wpan/mac"]
+ble = ["dep:embassy-stm32-wpan", "embassy-stm32-wpan/wb55_ble"]
+mac = ["dep:embassy-stm32-wpan", "embassy-stm32-wpan/wb55_mac"]
 embassy-stm32-wpan = []
 not-gpdma = []
 dac = []
@@ -77,7 +77,7 @@ embassy-executor = { version = "0.9.0", path = "../../embassy-executor", feature
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "tick-hz-131_072", "defmt-timestamp-uptime"] }
 embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "unstable-pac", "memory-x", "time-driver-any", "_allow-disable-rtc"]  }
 embassy-futures = { version = "0.1.2", path = "../../embassy-futures" }
-embassy-stm32-wpan = { version = "0.1.0", path = "../../embassy-stm32-wpan", optional = true, features = ["defmt", "stm32wb55rg", "ble"] }
+embassy-stm32-wpan = { version = "0.1.0", path = "../../embassy-stm32-wpan", optional = true, features = ["defmt", "stm32wb55rg", "wb55_ble"] }
 embassy-net = { version = "0.7.1", path = "../../embassy-net", features = ["defmt",  "tcp", "udp", "dhcpv4", "medium-ethernet"] }
 perf-client = { path = "../perf-client" }
 
diff --git a/tests/stm32/src/bin/sdmmc.rs b/tests/stm32/src/bin/sdmmc.rs
index 9f9c526e1..07422c42e 100644
--- a/tests/stm32/src/bin/sdmmc.rs
+++ b/tests/stm32/src/bin/sdmmc.rs
@@ -7,7 +7,8 @@ mod common;
 use common::*;
 use defmt::assert_eq;
 use embassy_executor::Spawner;
-use embassy_stm32::sdmmc::{DataBlock, Sdmmc};
+use embassy_stm32::sdmmc::Sdmmc;
+use embassy_stm32::sdmmc::sd::{CmdBlock, DataBlock, StorageDevice};
 use embassy_stm32::time::mhz;
 use embassy_stm32::{bind_interrupts, peripherals, sdmmc};
 use {defmt_rtt as _, panic_probe as _};
@@ -28,16 +29,16 @@ async fn main(_spawner: Spawner) {
     // Arbitrary block index
     let block_idx = 16;
 
-    let mut pattern1 = DataBlock([0u8; 512]);
-    let mut pattern2 = DataBlock([0u8; 512]);
+    let mut pattern1 = DataBlock::new();
+    let mut pattern2 = DataBlock::new();
     for i in 0..512 {
         pattern1[i] = i as u8;
         pattern2[i] = !i as u8;
     }
     let patterns = [pattern1.clone(), pattern2.clone()];
 
-    let mut block = DataBlock([0u8; 512]);
-    let mut blocks = [DataBlock([0u8; 512]), DataBlock([0u8; 512])];
+    let mut block = DataBlock::new();
+    let mut blocks = [DataBlock::new(), DataBlock::new()];
 
     // ======== Try 4bit. ==============
     info!("initializing in 4-bit mode...");
@@ -54,43 +55,80 @@ async fn main(_spawner: Spawner) {
         Default::default(),
     );
 
-    let mut err = None;
-    loop {
-        match s.init_sd_card(mhz(24)).await {
-            Ok(_) => break,
-            Err(e) => {
-                if err != Some(e) {
-                    info!("waiting for card: {:?}", e);
-                    err = Some(e);
-                }
-            }
-        }
-    }
+    let mut cmd_block = CmdBlock::new();
 
-    let card = unwrap!(s.card());
-
-    info!("Card: {:#?}", Debug2Format(card));
-    info!("Clock: {}", s.clock());
+    let mut storage = loop {
+        if let Ok(storage) = StorageDevice::new_sd_card(&mut s, &mut cmd_block, mhz(24)).await {
+            break storage;
+        }
+    };
+
+    let card = storage.card();
+
+    info!("Card: {:#?}", Debug2Format(&card));
+    info!("Clock: {}", storage.sdmmc.clock());
+
+    // card_type: HighCapacity,
+    // ocr: OCR: Operation Conditions Register {
+    // Voltage Window (mV): (2700, 3600),
+    // S18A (UHS-I only): true,
+    // Over 2TB flag (SDUC only): false,
+    // UHS-II Card: false,
+    // Card Capacity Status (CSS): \"SDHC/SDXC/SDUC\",
+    // Busy: false },
+    // rca: 43690,
+    // cid: CID: Card Identification { Manufacturer ID: 3,
+    // OEM ID: \"SD\",
+    // Product Name: \"SL08G\",
+    // Product Revision: 128,
+    // Product Serial Number: 701445767,
+    // Manufacturing Date: (9,
+    // 2015) },
+    // csd: CSD: Card Specific Data { Transfer Rate: 50,
+    // Block Count: 15523840,
+    // Card Size (bytes): 7948206080,
+    // Read I (@min VDD): 100 mA,
+    // Write I (@min VDD): 10 mA,
+    // Read I (@max VDD): 5 mA,
+    // Write I (@max VDD): 45 mA,
+    // Erase Size (Blocks): 1 },
+    // scr: SCR: SD CARD Configuration Register { Version: Unknown,
+    // 1-bit width: false,
+    // 4-bit width: true },
+    // status: SD Status { Bus Width: One,
+    // Secured Mode: false,
+    // SD Memory Card Type: 0,
+    // Protected Area Size (B): 0,
+    // Speed Class: 0,
+    // Video Speed Class: 0,
+    // Application Performance Class: 0,
+    // Move Performance (MB/s): 0,
+    // AU Size: 0,
+    // Erase Size (units of AU): 0,
+    // Erase Timeout (s): 0,
+    // Discard Support: false } }
+
+    defmt::assert!(card.scr.bus_width_four());
 
     info!("writing pattern1...");
-    s.write_block(block_idx, &pattern1).await.unwrap();
+    storage.write_block(block_idx, &pattern1).await.unwrap();
 
     info!("reading...");
-    s.read_block(block_idx, &mut block).await.unwrap();
+    storage.read_block(block_idx, &mut block).await.unwrap();
     assert_eq!(block, pattern1);
 
     info!("writing pattern2...");
-    s.write_block(block_idx, &pattern2).await.unwrap();
+    storage.write_block(block_idx, &pattern2).await.unwrap();
 
     info!("reading...");
-    s.read_block(block_idx, &mut block).await.unwrap();
+    storage.read_block(block_idx, &mut block).await.unwrap();
     assert_eq!(block, pattern2);
 
     info!("writing blocks [pattern1, pattern2]...");
-    s.write_blocks(block_idx, &patterns).await.unwrap();
+    storage.write_blocks(block_idx, &patterns).await.unwrap();
 
     info!("reading blocks...");
-    s.read_blocks(block_idx, &mut blocks).await.unwrap();
+    storage.read_blocks(block_idx, &mut blocks).await.unwrap();
     assert_eq!(&blocks, &patterns);
 
     drop(s);
diff --git a/tests/stm32/src/bin/usart.rs b/tests/stm32/src/bin/usart.rs
index 0b98d3eeb..ef7efe96a 100644
--- a/tests/stm32/src/bin/usart.rs
+++ b/tests/stm32/src/bin/usart.rs
@@ -6,6 +6,7 @@ mod common;
 use common::*;
 use defmt::{assert, assert_eq, unreachable};
 use embassy_executor::Spawner;
+use embassy_stm32::mode::Blocking;
 use embassy_stm32::usart::{Config, ConfigError, Error, Uart};
 use embassy_time::{Duration, Instant, block_for};
 
@@ -24,22 +25,41 @@ async fn main(_spawner: Spawner) {
         let config = Config::default();
         let mut usart = Uart::new_blocking(usart.reborrow(), rx.reborrow(), tx.reborrow(), config).unwrap();
 
-        // We can't send too many bytes, they have to fit in the FIFO.
-        // This is because we aren't sending+receiving at the same time.
+        let test_usart = async |usart: &mut Uart<'_, Blocking>| -> Result<(), Error> {
+            // We can't send too many bytes, they have to fit in the FIFO.
+            // This is because we aren't sending+receiving at the same time.
 
-        let data = [0xC0, 0xDE];
-        usart.blocking_write(&data).unwrap();
+            let data = [0xC0, 0xDE];
+            usart.blocking_write(&data)?;
 
-        let mut buf = [0; 2];
-        usart.blocking_read(&mut buf).unwrap();
-        assert_eq!(buf, data);
+            let mut buf = [0; 2];
+            usart.blocking_read(&mut buf)?;
+            assert_eq!(buf, data);
 
-        // Test flush doesn't hang.
-        usart.blocking_write(&data).unwrap();
-        usart.blocking_flush().unwrap();
+            // Test flush doesn't hang.
+            usart.blocking_write(&data)?;
+            usart.blocking_flush()?;
 
-        // Test flush doesn't hang if there's nothing to flush
-        usart.blocking_flush().unwrap();
+            // Test flush doesn't hang if there's nothing to flush
+            usart.blocking_flush()?;
+
+            Ok(())
+        };
+
+        let mut is_ok = false;
+        for _ in 0..3 {
+            match test_usart(&mut usart).await {
+                Ok(()) => is_ok = true,
+                Err(Error::Noise) => is_ok = false,
+                Err(e) => defmt::panic!("{}", e),
+            }
+
+            if is_ok {
+                break;
+            }
+        }
+
+        assert!(is_ok);
     }
 
     // Test error handling with with an overflow error
diff --git a/tests/stm32/src/bin/usart_dma.rs b/tests/stm32/src/bin/usart_dma.rs
index a34498376..9f610739d 100644
--- a/tests/stm32/src/bin/usart_dma.rs
+++ b/tests/stm32/src/bin/usart_dma.rs
@@ -7,7 +7,7 @@ use common::*;
 use defmt::assert_eq;
 use embassy_executor::Spawner;
 use embassy_futures::join::join;
-use embassy_stm32::usart::{Config, Uart};
+use embassy_stm32::usart::{Config, Error, Uart};
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
@@ -32,6 +32,7 @@ async fn main(_spawner: Spawner) {
 
     let (mut tx, mut rx) = usart.split();
 
+    let mut noise_count = 0;
     for n in 0..42 {
         for i in 0..LEN {
             tx_buf[i] = (i ^ n) as u8;
@@ -40,17 +41,30 @@ async fn main(_spawner: Spawner) {
         let tx_fut = async {
             tx.write(&tx_buf).await.unwrap();
         };
+
+        let mut is_noisy = false;
         let rx_fut = async {
-            rx.read(&mut rx_buf).await.unwrap();
+            match rx.read(&mut rx_buf).await {
+                Ok(()) => {}
+                Err(Error::Noise) => is_noisy = true,
+                _ => defmt::panic!(),
+            }
         };
 
         // note: rx needs to be polled first, to workaround this bug:
         // https://github.com/embassy-rs/embassy/issues/1426
         join(rx_fut, tx_fut).await;
 
+        if is_noisy {
+            noise_count += 1;
+            continue;
+        }
+
         assert_eq!(tx_buf, rx_buf);
     }
 
+    defmt::assert!(noise_count < 3);
+
     // Test flush doesn't hang. Check multiple combinations of async+blocking.
     tx.write(&tx_buf).await.unwrap();
     tx.flush().await.unwrap();