diff options
| author | elagil <[email protected]> | 2025-08-25 21:10:59 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2025-09-05 14:43:29 +0200 |
| commit | e9783ee28e9bdd89ffaeffb24bbff207c1ceb837 (patch) | |
| tree | dcf348177241127c07d5739aea33cfff968e2dde /embassy-stm32/src/usart | |
| parent | d3718c6d4e0a8485cdef8ecf6deb05c3eff5af08 (diff) | |
fix: build
Diffstat (limited to 'embassy-stm32/src/usart')
| -rw-r--r-- | embassy-stm32/src/usart/ringbuffered.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs index 8a607a31a..5f4e87834 100644 --- a/embassy-stm32/src/usart/ringbuffered.rs +++ b/embassy-stm32/src/usart/ringbuffered.rs | |||
| @@ -83,7 +83,7 @@ pub struct RingBufferedUartRx<'d> { | |||
| 83 | kernel_clock: Hertz, | 83 | kernel_clock: Hertz, |
| 84 | rx: Option<Peri<'d, AnyPin>>, | 84 | rx: Option<Peri<'d, AnyPin>>, |
| 85 | rts: Option<Peri<'d, AnyPin>>, | 85 | rts: Option<Peri<'d, AnyPin>>, |
| 86 | ring_buf: ReadableRingBuffer<'d, u8, 2>, | 86 | ring_buf: ReadableRingBuffer<'d, u8>, |
| 87 | } | 87 | } |
| 88 | 88 | ||
| 89 | impl<'d> SetConfig for RingBufferedUartRx<'d> { | 89 | impl<'d> SetConfig for RingBufferedUartRx<'d> { |
| @@ -165,7 +165,7 @@ impl<'d> RingBufferedUartRx<'d> { | |||
| 165 | 165 | ||
| 166 | /// Stop DMA backed UART receiver | 166 | /// Stop DMA backed UART receiver |
| 167 | fn stop_uart(&mut self) { | 167 | fn stop_uart(&mut self) { |
| 168 | self.ring_buf.request_suspend(); | 168 | self.ring_buf.request_pause(); |
| 169 | 169 | ||
| 170 | let r = self.info.regs; | 170 | let r = self.info.regs; |
| 171 | // clear all interrupts and DMA Rx Request | 171 | // clear all interrupts and DMA Rx Request |
