Merge branch 'embassy-rs:main' into stm32_adc_v3_hw_oversampling_support

64 files changed, 2829 insertions, 1101 deletions

diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index b6781905e..c4c2cd013 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased
 - Modify BufferedUart initialization to take pins before interrupts ([#3983](https://github.com/embassy-rs/embassy/pull/3983))
 - Added a 'single-bank' and a 'dual-bank' feature so chips with configurable flash bank setups are be supported in embassy ([#4125](https://github.com/embassy-rs/embassy/pull/4125))
+- Add automatic setting of remap bits when using alternate DMA channels on STM32F0 and STM32F3 devices ([#3653](https://github.com/embassy-rs/embassy/pull/3653))
 
 ## 0.2.0 - 2025-01-10
 
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 034f51df9..02e75733e 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -53,11 +53,11 @@ embassy-time = { version = "0.4.0", path = "../embassy-time", optional = true }
 embassy-time-driver = { version = "0.2", path = "../embassy-time-driver", optional = true }
 embassy-time-queue-utils = { version = "0.1", path = "../embassy-time-queue-utils", optional = true }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
-embassy-hal-internal = { version = "0.2.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-4"] }
-embassy-embedded-hal = { version = "0.3.0", path = "../embassy-embedded-hal", default-features = false }
+embassy-hal-internal = { version = "0.3.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-4"] }
+embassy-embedded-hal = { version = "0.3.1", path = "../embassy-embedded-hal", default-features = false }
 embassy-net-driver = { version = "0.2.0", path = "../embassy-net-driver" }
-embassy-usb-driver = { version = "0.1.0", path = "../embassy-usb-driver" }
-embassy-usb-synopsys-otg = { version = "0.2.0", path = "../embassy-usb-synopsys-otg" }
+embassy-usb-driver = { version = "0.2.0", path = "../embassy-usb-driver" }
+embassy-usb-synopsys-otg = { version = "0.3.0", path = "../embassy-usb-synopsys-otg" }
 embassy-executor = { version = "0.7.0", path = "../embassy-executor", optional = true }
 
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
@@ -81,7 +81,7 @@ futures-util = { version = "0.3.30", default-features = false }
 sdio-host = "0.9.0"
 critical-section = "1.1"
 #stm32-metapac = { version = "16" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-27ef8fba3483187e852eaf3796d827259f61e8ec" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9fc86ca7b3a8bc05182bf1ce3045602df1f5dce3" }
 
 vcell = "0.1.3"
 nb = "1.0.0"
@@ -110,7 +110,7 @@ proc-macro2 = "1.0.36"
 quote = "1.0.15"
 
 #stm32-metapac = { version = "16", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-27ef8fba3483187e852eaf3796d827259f61e8ec", default-features = false, features = ["metadata"] }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9fc86ca7b3a8bc05182bf1ce3045602df1f5dce3", default-features = false, features = ["metadata"] }
 
 [features]
 default = ["rt"]
@@ -129,6 +129,7 @@ defmt = [
     "embassy-net-driver/defmt",
     "embassy-time?/defmt",
     "embassy-usb-synopsys-otg/defmt",
+    "stm32-metapac/defmt"
 ]
 
 exti = []
@@ -237,6 +238,47 @@ stm32c031g4 = [ "stm32-metapac/stm32c031g4" ]
 stm32c031g6 = [ "stm32-metapac/stm32c031g6" ]
 stm32c031k4 = [ "stm32-metapac/stm32c031k4" ]
 stm32c031k6 = [ "stm32-metapac/stm32c031k6" ]
+stm32c051c6 = [ "stm32-metapac/stm32c051c6" ]
+stm32c051c8 = [ "stm32-metapac/stm32c051c8" ]
+stm32c051d8 = [ "stm32-metapac/stm32c051d8" ]
+stm32c051f6 = [ "stm32-metapac/stm32c051f6" ]
+stm32c051f8 = [ "stm32-metapac/stm32c051f8" ]
+stm32c051g6 = [ "stm32-metapac/stm32c051g6" ]
+stm32c051g8 = [ "stm32-metapac/stm32c051g8" ]
+stm32c051k6 = [ "stm32-metapac/stm32c051k6" ]
+stm32c051k8 = [ "stm32-metapac/stm32c051k8" ]
+stm32c071c8 = [ "stm32-metapac/stm32c071c8" ]
+stm32c071cb = [ "stm32-metapac/stm32c071cb" ]
+stm32c071f8 = [ "stm32-metapac/stm32c071f8" ]
+stm32c071fb = [ "stm32-metapac/stm32c071fb" ]
+stm32c071g8 = [ "stm32-metapac/stm32c071g8" ]
+stm32c071gb = [ "stm32-metapac/stm32c071gb" ]
+stm32c071k8 = [ "stm32-metapac/stm32c071k8" ]
+stm32c071kb = [ "stm32-metapac/stm32c071kb" ]
+stm32c071r8 = [ "stm32-metapac/stm32c071r8" ]
+stm32c071rb = [ "stm32-metapac/stm32c071rb" ]
+stm32c091cb = [ "stm32-metapac/stm32c091cb" ]
+stm32c091cc = [ "stm32-metapac/stm32c091cc" ]
+stm32c091ec = [ "stm32-metapac/stm32c091ec" ]
+stm32c091fb = [ "stm32-metapac/stm32c091fb" ]
+stm32c091fc = [ "stm32-metapac/stm32c091fc" ]
+stm32c091gb = [ "stm32-metapac/stm32c091gb" ]
+stm32c091gc = [ "stm32-metapac/stm32c091gc" ]
+stm32c091kb = [ "stm32-metapac/stm32c091kb" ]
+stm32c091kc = [ "stm32-metapac/stm32c091kc" ]
+stm32c091rb = [ "stm32-metapac/stm32c091rb" ]
+stm32c091rc = [ "stm32-metapac/stm32c091rc" ]
+stm32c092cb = [ "stm32-metapac/stm32c092cb" ]
+stm32c092cc = [ "stm32-metapac/stm32c092cc" ]
+stm32c092ec = [ "stm32-metapac/stm32c092ec" ]
+stm32c092fb = [ "stm32-metapac/stm32c092fb" ]
+stm32c092fc = [ "stm32-metapac/stm32c092fc" ]
+stm32c092gb = [ "stm32-metapac/stm32c092gb" ]
+stm32c092gc = [ "stm32-metapac/stm32c092gc" ]
+stm32c092kb = [ "stm32-metapac/stm32c092kb" ]
+stm32c092kc = [ "stm32-metapac/stm32c092kc" ]
+stm32c092rb = [ "stm32-metapac/stm32c092rb" ]
+stm32c092rc = [ "stm32-metapac/stm32c092rc" ]
 stm32f030c6 = [ "stm32-metapac/stm32f030c6" ]
 stm32f030c8 = [ "stm32-metapac/stm32f030c8" ]
 stm32f030cc = [ "stm32-metapac/stm32f030cc" ]
@@ -1634,6 +1676,24 @@ stm32wba55he = [ "stm32-metapac/stm32wba55he" ]
 stm32wba55hg = [ "stm32-metapac/stm32wba55hg" ]
 stm32wba55ue = [ "stm32-metapac/stm32wba55ue" ]
 stm32wba55ug = [ "stm32-metapac/stm32wba55ug" ]
+stm32wba62cg = [ "stm32-metapac/stm32wba62cg" ]
+stm32wba62ci = [ "stm32-metapac/stm32wba62ci" ]
+stm32wba62mg = [ "stm32-metapac/stm32wba62mg" ]
+stm32wba62mi = [ "stm32-metapac/stm32wba62mi" ]
+stm32wba62pg = [ "stm32-metapac/stm32wba62pg" ]
+stm32wba62pi = [ "stm32-metapac/stm32wba62pi" ]
+stm32wba63cg = [ "stm32-metapac/stm32wba63cg" ]
+stm32wba63ci = [ "stm32-metapac/stm32wba63ci" ]
+stm32wba64cg = [ "stm32-metapac/stm32wba64cg" ]
+stm32wba64ci = [ "stm32-metapac/stm32wba64ci" ]
+stm32wba65cg = [ "stm32-metapac/stm32wba65cg" ]
+stm32wba65ci = [ "stm32-metapac/stm32wba65ci" ]
+stm32wba65mg = [ "stm32-metapac/stm32wba65mg" ]
+stm32wba65mi = [ "stm32-metapac/stm32wba65mi" ]
+stm32wba65pg = [ "stm32-metapac/stm32wba65pg" ]
+stm32wba65pi = [ "stm32-metapac/stm32wba65pi" ]
+stm32wba65rg = [ "stm32-metapac/stm32wba65rg" ]
+stm32wba65ri = [ "stm32-metapac/stm32wba65ri" ]
 stm32wl54cc-cm4 = [ "stm32-metapac/stm32wl54cc-cm4", "_dual-core", "_core-cm4" ]
 stm32wl54cc-cm0p = [ "stm32-metapac/stm32wl54cc-cm0p", "_dual-core", "_core-cm0p" ]
 stm32wl54jc-cm4 = [ "stm32-metapac/stm32wl54jc-cm4", "_dual-core", "_core-cm4" ]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index bb5ef53d7..73860c64a 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -505,6 +505,13 @@ fn main() {
                 field: "CLK48SEL",
             },
         );
+        clock_gen.chained_muxes.insert(
+            "RFWKP",
+            &PeripheralRccRegister {
+                register: "CSR",
+                field: "RFWKPSEL",
+            },
+        );
     }
     if chip_name.starts_with("stm32f7") {
         clock_gen.chained_muxes.insert(
@@ -1090,21 +1097,21 @@ fn main() {
         (("fmc", "CLK"), quote!(crate::fmc::ClkPin)),
         (("fmc", "BA0"), quote!(crate::fmc::BA0Pin)),
         (("fmc", "BA1"), quote!(crate::fmc::BA1Pin)),
-        (("timer", "CH1"), quote!(crate::timer::Channel1Pin)),
-        (("timer", "CH1N"), quote!(crate::timer::Channel1ComplementaryPin)),
-        (("timer", "CH2"), quote!(crate::timer::Channel2Pin)),
-        (("timer", "CH2N"), quote!(crate::timer::Channel2ComplementaryPin)),
-        (("timer", "CH3"), quote!(crate::timer::Channel3Pin)),
-        (("timer", "CH3N"), quote!(crate::timer::Channel3ComplementaryPin)),
-        (("timer", "CH4"), quote!(crate::timer::Channel4Pin)),
-        (("timer", "CH4N"), quote!(crate::timer::Channel4ComplementaryPin)),
+        (("timer", "CH1"), quote!(crate::timer::TimerPin<Ch1>)),
+        (("timer", "CH1N"), quote!(crate::timer::TimerComplementaryPin<Ch1>)),
+        (("timer", "CH2"), quote!(crate::timer::TimerPin<Ch2>)),
+        (("timer", "CH2N"), quote!(crate::timer::TimerComplementaryPin<Ch2>)),
+        (("timer", "CH3"), quote!(crate::timer::TimerPin<Ch3>)),
+        (("timer", "CH3N"), quote!(crate::timer::TimerComplementaryPin<Ch3>)),
+        (("timer", "CH4"), quote!(crate::timer::TimerPin<Ch4>)),
+        (("timer", "CH4N"), quote!(crate::timer::TimerComplementaryPin<Ch4>)),
         (("timer", "ETR"), quote!(crate::timer::ExternalTriggerPin)),
-        (("timer", "BKIN"), quote!(crate::timer::BreakInputPin)),
-        (("timer", "BKIN_COMP1"), quote!(crate::timer::BreakInputComparator1Pin)),
-        (("timer", "BKIN_COMP2"), quote!(crate::timer::BreakInputComparator2Pin)),
-        (("timer", "BKIN2"), quote!(crate::timer::BreakInput2Pin)),
-        (("timer", "BKIN2_COMP1"), quote!(crate::timer::BreakInput2Comparator1Pin)),
-        (("timer", "BKIN2_COMP2"), quote!(crate::timer::BreakInput2Comparator2Pin)),
+        (("timer", "BKIN"), quote!(crate::timer::BreakInputPin<BkIn1>)),
+        (("timer", "BKIN_COMP1"), quote!(crate::timer::BreakInputComparator1Pin<BkIn1>)),
+        (("timer", "BKIN_COMP2"), quote!(crate::timer::BreakInputComparator2Pin<BkIn1>)),
+        (("timer", "BKIN2"), quote!(crate::timer::BreakInputPin<BkIn2>)),
+        (("timer", "BKIN2_COMP1"), quote!(crate::timer::BreakInputComparator1Pin<BkIn2>)),
+        (("timer", "BKIN2_COMP2"), quote!(crate::timer::BreakInputComparator2Pin<BkIn2>)),
         (("hrtim", "CHA1"), quote!(crate::hrtim::ChannelAPin)),
         (("hrtim", "CHA2"), quote!(crate::hrtim::ChannelAComplementaryPin)),
         (("hrtim", "CHB1"), quote!(crate::hrtim::ChannelBPin)),
@@ -1402,31 +1409,24 @@ fn main() {
                 }
 
                 if regs.kind == "opamp" {
-                    if pin.signal.starts_with("VP") {
-                        // Impl NonInvertingPin for the VP* signals (VP0, VP1, VP2, etc)
-                        let peri = format_ident!("{}", p.name);
-                        let pin_name = format_ident!("{}", pin.pin);
-                        let ch: u8 = pin.signal.strip_prefix("VP").unwrap().parse().unwrap();
-
-                        g.extend(quote! {
-                            impl_opamp_vp_pin!( #peri, #pin_name, #ch);
-                        })
-                    } else if pin.signal.starts_with("VINM") {
-                        // Impl NonInvertingPin for the VINM* signals ( VINM0, VINM1, etc)
-                        // STM32G4
-                        let peri = format_ident!("{}", p.name);
-                        let pin_name = format_ident!("{}", pin.pin);
-                        let ch: Result<u8, _> = pin.signal.strip_prefix("VINM").unwrap().parse();
-
-                        if let Ok(ch) = ch {
+                    let peri = format_ident!("{}", p.name);
+                    let pin_name = format_ident!("{}", pin.pin);
+                    if let Some(ch_str) = pin.signal.strip_prefix("VINP") {
+                        // Impl NonInvertingPin for VINP0, VINP1 etc.
+                        if let Ok(ch) = ch_str.parse::<u8>() {
+                            g.extend(quote! {
+                                impl_opamp_vp_pin!( #peri, #pin_name, #ch );
+                            });
+                        }
+                    } else if let Some(ch_str) = pin.signal.strip_prefix("VINM") {
+                        // Impl InvertingPin for VINM0, VINM1 etc.
+                        if let Ok(ch) = ch_str.parse::<u8>() {
                             g.extend(quote! {
                                 impl_opamp_vn_pin!( #peri, #pin_name, #ch);
-                            })
+                            });
                         }
                     } else if pin.signal == "VOUT" {
                         // Impl OutputPin for the VOUT pin
-                        let peri = format_ident!("{}", p.name);
-                        let pin_name = format_ident!("{}", pin.pin);
                         g.extend(quote! {
                             impl_opamp_vout_pin!( #peri, #pin_name );
                         })
@@ -1482,10 +1482,10 @@ fn main() {
         (("hash", "IN"), quote!(crate::hash::Dma)),
         (("cryp", "IN"), quote!(crate::cryp::DmaIn)),
         (("cryp", "OUT"), quote!(crate::cryp::DmaOut)),
-        (("timer", "CH1"), quote!(crate::timer::Ch1Dma)),
-        (("timer", "CH2"), quote!(crate::timer::Ch2Dma)),
-        (("timer", "CH3"), quote!(crate::timer::Ch3Dma)),
-        (("timer", "CH4"), quote!(crate::timer::Ch4Dma)),
+        (("timer", "CH1"), quote!(crate::timer::Dma<Ch1>)),
+        (("timer", "CH2"), quote!(crate::timer::Dma<Ch2>)),
+        (("timer", "CH3"), quote!(crate::timer::Dma<Ch3>)),
+        (("timer", "CH4"), quote!(crate::timer::Dma<Ch4>)),
         (("cordic", "WRITE"), quote!(crate::cordic::WriteDma)), // FIXME: stm32u5a crash on Cordic driver
         (("cordic", "READ"), quote!(crate::cordic::ReadDma)),   // FIXME: stm32u5a crash on Cordic driver
     ]
@@ -1497,6 +1497,10 @@ fn main() {
         signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma));
     }
 
+    if chip_name.starts_with("stm32wba") {
+        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma4));
+    }
+
     if chip_name.starts_with("stm32g4") {
         let line_number = chip_name.chars().skip(8).next().unwrap();
         if line_number == '3' || line_number == '4' {
@@ -1554,9 +1558,35 @@ fn main() {
                             quote!(())
                         };
 
+                        let mut remap = quote!();
+                        for remap_info in ch.remap {
+                            let register = format_ident!("{}", remap_info.register.to_lowercase());
+                            let setter = format_ident!("set_{}", remap_info.field.to_lowercase());
+
+                            let field_metadata = METADATA
+                                .peripherals
+                                .iter()
+                                .filter(|p| p.name == "SYSCFG")
+                                .flat_map(|p| p.registers.as_ref().unwrap().ir.fieldsets.iter())
+                                .filter(|f| f.name.eq_ignore_ascii_case(remap_info.register))
+                                .flat_map(|f| f.fields.iter())
+                                .find(|f| f.name.eq_ignore_ascii_case(remap_info.field))
+                                .unwrap();
+
+                            let value = if field_metadata.bit_size == 1 {
+                                let bool_value = format_ident!("{}", remap_info.value > 0);
+                                quote!(#bool_value)
+                            } else {
+                                let value = remap_info.value;
+                                quote!(#value.into())
+                            };
+
+                            remap.extend(quote!(crate::pac::SYSCFG.#register().modify(|w| w.#setter(#value));));
+                        }
+
                         let channel = format_ident!("{}", channel);
                         g.extend(quote! {
-                            dma_trait_impl!(#tr, #peri, #channel, #request);
+                            dma_trait_impl!(#tr, #peri, #channel, #request, {#remap});
                         });
                     }
                 }
@@ -1888,9 +1918,9 @@ fn main() {
     }
 
     g.extend(quote!(
-        pub fn gpio_block(n: usize) -> crate::pac::gpio::Gpio {{
-            unsafe {{ crate::pac::gpio::Gpio::from_ptr((#gpio_base + #gpio_stride*n) as _) }}
-        }}
+        pub fn gpio_block(n: usize) -> crate::pac::gpio::Gpio {
+            unsafe { crate::pac::gpio::Gpio::from_ptr((#gpio_base + #gpio_stride*n) as _) }
+        }
     ));
 
     // ========
diff --git a/embassy-stm32/src/adc/u5_adc4.rs b/embassy-stm32/src/adc/adc4.rs
index 1dd664366..31cbdc0d7 100644
--- a/embassy-stm32/src/adc/u5_adc4.rs
+++ b/embassy-stm32/src/adc/adc4.rs
@@ -1,10 +1,19 @@
+#[cfg(stm32u5)]
+use pac::adc::vals::{Adc4Dmacfg as Dmacfg, Adc4Exten as Exten, Adc4OversamplingRatio as OversamplingRatio};
 #[allow(unused)]
-use pac::adc::vals::{Adc4Dmacfg, Adc4Exten, Adc4OversamplingRatio};
+#[cfg(stm32wba)]
+use pac::adc::vals::{Chselrmod, Cont, Dmacfg, Exten, OversamplingRatio, Ovss, Smpsel};
 
 use super::{blocking_delay_us, AdcChannel, AnyAdcChannel, RxDma4, SealedAdcChannel};
 use crate::dma::Transfer;
-pub use crate::pac::adc::regs::Adc4Chselrmod0;
+#[cfg(stm32u5)]
+pub use crate::pac::adc::regs::Adc4Chselrmod0 as Chselr;
+#[cfg(stm32wba)]
+pub use crate::pac::adc::regs::Chselr;
+#[cfg(stm32u5)]
 pub use crate::pac::adc::vals::{Adc4Presc as Presc, Adc4Res as Resolution, Adc4SampleTime as SampleTime};
+#[cfg(stm32wba)]
+pub use crate::pac::adc::vals::{Presc, Res as Resolution, SampleTime};
 use crate::time::Hertz;
 use crate::{pac, rcc, Peri};
 
@@ -67,12 +76,14 @@ impl<T: Instance> SealedAdcChannel<T> for Vcore {
     }
 }
 
+#[derive(Copy, Clone)]
 pub enum DacChannel {
     OUT1,
     OUT2,
 }
 
 /// Number of samples used for averaging.
+#[derive(Copy, Clone)]
 pub enum Averaging {
     Disabled,
     Samples2,
@@ -178,7 +189,7 @@ pub struct Adc4<'d, T: Instance> {
     adc: crate::Peri<'d, T>,
 }
 
-#[derive(Debug)]
+#[derive(Copy, Clone, Debug)]
 pub enum Adc4Error {
     InvalidSequence,
     DMAError,
@@ -242,17 +253,28 @@ impl<'d, T: Instance> Adc4<'d, T> {
     fn configure(&mut self) {
         // single conversion mode, software trigger
         T::regs().cfgr1().modify(|w| {
+            #[cfg(stm32u5)]
             w.set_cont(false);
+            #[cfg(stm32wba)]
+            w.set_cont(Cont::SINGLE);
             w.set_discen(false);
-            w.set_exten(Adc4Exten::DISABLED);
+            w.set_exten(Exten::DISABLED);
+            #[cfg(stm32u5)]
             w.set_chselrmod(false);
+            #[cfg(stm32wba)]
+            w.set_chselrmod(Chselrmod::ENABLE_INPUT);
         });
 
         // only use one channel at the moment
         T::regs().smpr().modify(|w| {
+            #[cfg(stm32u5)]
             for i in 0..24 {
                 w.set_smpsel(i, false);
             }
+            #[cfg(stm32wba)]
+            for i in 0..14 {
+                w.set_smpsel(i, Smpsel::SMP1);
+            }
         });
     }
 
@@ -275,6 +297,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
     }
 
     /// Enable reading the vbat internal channel.
+    #[cfg(stm32u5)]
     pub fn enable_vbat(&self) -> Vbat {
         T::regs().ccr().modify(|w| {
             w.set_vbaten(true);
@@ -289,6 +312,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
     }
 
     /// Enable reading the vbat internal channel.
+    #[cfg(stm32u5)]
     pub fn enable_dac_channel(&self, dac: DacChannel) -> Dac {
         let mux;
         match dac {
@@ -317,17 +341,38 @@ impl<'d, T: Instance> Adc4<'d, T> {
     }
 
     /// Set hardware averaging.
+    #[cfg(stm32u5)]
+    pub fn set_averaging(&mut self, averaging: Averaging) {
+        let (enable, samples, right_shift) = match averaging {
+            Averaging::Disabled => (false, OversamplingRatio::OVERSAMPLE2X, 0),
+            Averaging::Samples2 => (true, OversamplingRatio::OVERSAMPLE2X, 1),
+            Averaging::Samples4 => (true, OversamplingRatio::OVERSAMPLE4X, 2),
+            Averaging::Samples8 => (true, OversamplingRatio::OVERSAMPLE8X, 3),
+            Averaging::Samples16 => (true, OversamplingRatio::OVERSAMPLE16X, 4),
+            Averaging::Samples32 => (true, OversamplingRatio::OVERSAMPLE32X, 5),
+            Averaging::Samples64 => (true, OversamplingRatio::OVERSAMPLE64X, 6),
+            Averaging::Samples128 => (true, OversamplingRatio::OVERSAMPLE128X, 7),
+            Averaging::Samples256 => (true, OversamplingRatio::OVERSAMPLE256X, 8),
+        };
+
+        T::regs().cfgr2().modify(|w| {
+            w.set_ovsr(samples);
+            w.set_ovss(right_shift);
+            w.set_ovse(enable)
+        })
+    }
+    #[cfg(stm32wba)]
     pub fn set_averaging(&mut self, averaging: Averaging) {
         let (enable, samples, right_shift) = match averaging {
-            Averaging::Disabled => (false, Adc4OversamplingRatio::OVERSAMPLE2X, 0),
-            Averaging::Samples2 => (true, Adc4OversamplingRatio::OVERSAMPLE2X, 1),
-            Averaging::Samples4 => (true, Adc4OversamplingRatio::OVERSAMPLE4X, 2),
-            Averaging::Samples8 => (true, Adc4OversamplingRatio::OVERSAMPLE8X, 3),
-            Averaging::Samples16 => (true, Adc4OversamplingRatio::OVERSAMPLE16X, 4),
-            Averaging::Samples32 => (true, Adc4OversamplingRatio::OVERSAMPLE32X, 5),
-            Averaging::Samples64 => (true, Adc4OversamplingRatio::OVERSAMPLE64X, 6),
-            Averaging::Samples128 => (true, Adc4OversamplingRatio::OVERSAMPLE128X, 7),
-            Averaging::Samples256 => (true, Adc4OversamplingRatio::OVERSAMPLE256X, 8),
+            Averaging::Disabled => (false, OversamplingRatio::OVERSAMPLE2X, Ovss::SHIFT0),
+            Averaging::Samples2 => (true, OversamplingRatio::OVERSAMPLE2X, Ovss::SHIFT1),
+            Averaging::Samples4 => (true, OversamplingRatio::OVERSAMPLE4X, Ovss::SHIFT2),
+            Averaging::Samples8 => (true, OversamplingRatio::OVERSAMPLE8X, Ovss::SHIFT3),
+            Averaging::Samples16 => (true, OversamplingRatio::OVERSAMPLE16X, Ovss::SHIFT4),
+            Averaging::Samples32 => (true, OversamplingRatio::OVERSAMPLE32X, Ovss::SHIFT5),
+            Averaging::Samples64 => (true, OversamplingRatio::OVERSAMPLE64X, Ovss::SHIFT6),
+            Averaging::Samples128 => (true, OversamplingRatio::OVERSAMPLE128X, Ovss::SHIFT7),
+            Averaging::Samples256 => (true, OversamplingRatio::OVERSAMPLE256X, Ovss::SHIFT8),
         };
 
         T::regs().cfgr2().modify(|w| {
@@ -342,10 +387,20 @@ impl<'d, T: Instance> Adc4<'d, T> {
         channel.setup();
 
         // Select channel
-        T::regs().chselrmod0().write_value(Adc4Chselrmod0(0_u32));
-        T::regs().chselrmod0().modify(|w| {
-            w.set_chsel(channel.channel() as usize, true);
-        });
+        #[cfg(stm32wba)]
+        {
+            T::regs().chselr().write_value(Chselr(0_u32));
+            T::regs().chselr().modify(|w| {
+                w.set_chsel0(channel.channel() as usize, true);
+            });
+        }
+        #[cfg(stm32u5)]
+        {
+            T::regs().chselrmod0().write_value(Chselr(0_u32));
+            T::regs().chselrmod0().modify(|w| {
+                w.set_chsel(channel.channel() as usize, true);
+            });
+        }
 
         // Reset interrupts
         T::regs().isr().modify(|reg| {
@@ -415,13 +470,19 @@ impl<'d, T: Instance> Adc4<'d, T> {
 
         T::regs().cfgr1().modify(|reg| {
             reg.set_dmaen(true);
-            reg.set_dmacfg(Adc4Dmacfg::ONE_SHOT);
+            reg.set_dmacfg(Dmacfg::ONE_SHOT);
+            #[cfg(stm32u5)]
             reg.set_chselrmod(false);
+            #[cfg(stm32wba)]
+            reg.set_chselrmod(Chselrmod::ENABLE_INPUT)
         });
 
         // Verify and activate sequence
         let mut prev_channel: i16 = -1;
-        T::regs().chselrmod0().write_value(Adc4Chselrmod0(0_u32));
+        #[cfg(stm32wba)]
+        T::regs().chselr().write_value(Chselr(0_u32));
+        #[cfg(stm32u5)]
+        T::regs().chselrmod0().write_value(Chselr(0_u32));
         for channel in sequence {
             let channel_num = channel.channel;
             if channel_num as i16 <= prev_channel {
@@ -429,6 +490,11 @@ impl<'d, T: Instance> Adc4<'d, T> {
             };
             prev_channel = channel_num as i16;
 
+            #[cfg(stm32wba)]
+            T::regs().chselr().modify(|w| {
+                w.set_chsel0(channel.channel as usize, true);
+            });
+            #[cfg(stm32u5)]
             T::regs().chselrmod0().modify(|w| {
                 w.set_chsel(channel.channel as usize, true);
             });
diff --git a/embassy-stm32/src/adc/c0.rs b/embassy-stm32/src/adc/c0.rs
index 936ad7413..f5870801e 100644
--- a/embassy-stm32/src/adc/c0.rs
+++ b/embassy-stm32/src/adc/c0.rs
@@ -48,7 +48,7 @@ impl<T: Instance> SealedAdcChannel<T> for Temperature {
     }
 }
 
-#[derive(Debug)]
+#[derive(Copy, Clone, Debug)]
 pub enum Prescaler {
     NotDivided,
     DividedBy2,
@@ -138,6 +138,7 @@ impl<'a> defmt::Format for Prescaler {
 /// Number of samples used for averaging.
 /// TODO: Implement hardware averaging setting.
 #[allow(unused)]
+#[derive(Copy, Clone)]
 pub enum Averaging {
     Disabled,
     Samples2,
diff --git a/embassy-stm32/src/adc/f3_v1_1.rs b/embassy-stm32/src/adc/f3_v1_1.rs
index 944e971bb..84613078c 100644
--- a/embassy-stm32/src/adc/f3_v1_1.rs
+++ b/embassy-stm32/src/adc/f3_v1_1.rs
@@ -17,6 +17,7 @@ pub const VDDA_CALIB_MV: u32 = 3300;
 pub const ADC_MAX: u32 = (1 << 12) - 1;
 pub const VREF_INT: u32 = 1230;
 
+#[derive(Copy, Clone)]
 pub enum AdcPowerMode {
     AlwaysOn,
     DelayOff,
@@ -24,6 +25,7 @@ pub enum AdcPowerMode {
     DelayIdleOff,
 }
 
+#[derive(Copy, Clone)]
 pub enum Prescaler {
     Div1,
     Div2,
diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index 1fce3085a..43498966f 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -24,44 +24,31 @@ const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(60);
 #[cfg(stm32h7)]
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(50);
 
-#[cfg(stm32g4)]
-const VREF_CHANNEL: u8 = 18;
-#[cfg(stm32g4)]
-const TEMP_CHANNEL: u8 = 16;
-
-#[cfg(stm32h7)]
-const VREF_CHANNEL: u8 = 19;
-#[cfg(stm32h7)]
-const TEMP_CHANNEL: u8 = 18;
-
-// TODO this should be 14 for H7a/b/35
-const VBAT_CHANNEL: u8 = 17;
-
 // NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
 /// Internal voltage reference channel.
 pub struct VrefInt;
-impl<T: Instance> AdcChannel<T> for VrefInt {}
-impl<T: Instance> super::SealedAdcChannel<T> for VrefInt {
+impl<T: Instance + VrefChannel> AdcChannel<T> for VrefInt {}
+impl<T: Instance + VrefChannel> super::SealedAdcChannel<T> for VrefInt {
     fn channel(&self) -> u8 {
-        VREF_CHANNEL
+        T::CHANNEL
     }
 }
 
 /// Internal temperature channel.
 pub struct Temperature;
-impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> super::SealedAdcChannel<T> for Temperature {
+impl<T: Instance + TemperatureChannel> AdcChannel<T> for Temperature {}
+impl<T: Instance + TemperatureChannel> super::SealedAdcChannel<T> for Temperature {
     fn channel(&self) -> u8 {
-        TEMP_CHANNEL
+        T::CHANNEL
     }
 }
 
 /// Internal battery voltage channel.
 pub struct Vbat;
-impl<T: Instance> AdcChannel<T> for Vbat {}
-impl<T: Instance> super::SealedAdcChannel<T> for Vbat {
+impl<T: Instance + VBatChannel> AdcChannel<T> for Vbat {}
+impl<T: Instance + VBatChannel> super::SealedAdcChannel<T> for Vbat {
     fn channel(&self) -> u8 {
-        VBAT_CHANNEL
+        T::CHANNEL
     }
 }
 
@@ -234,7 +221,10 @@ impl<'d, T: Instance> Adc<'d, T> {
     }
 
     /// Enable reading the voltage reference internal channel.
-    pub fn enable_vrefint(&self) -> VrefInt {
+    pub fn enable_vrefint(&self) -> VrefInt
+    where
+        T: VrefChannel,
+    {
         T::common_regs().ccr().modify(|reg| {
             reg.set_vrefen(true);
         });
@@ -243,7 +233,10 @@ impl<'d, T: Instance> Adc<'d, T> {
     }
 
     /// Enable reading the temperature internal channel.
-    pub fn enable_temperature(&self) -> Temperature {
+    pub fn enable_temperature(&self) -> Temperature
+    where
+        T: TemperatureChannel,
+    {
         T::common_regs().ccr().modify(|reg| {
             reg.set_vsenseen(true);
         });
@@ -252,7 +245,10 @@ impl<'d, T: Instance> Adc<'d, T> {
     }
 
     /// Enable reading the vbat internal channel.
-    pub fn enable_vbat(&self) -> Vbat {
+    pub fn enable_vbat(&self) -> Vbat
+    where
+        T: VBatChannel,
+    {
         T::common_regs().ccr().modify(|reg| {
             reg.set_vbaten(true);
         });
@@ -519,3 +515,78 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
     }
 }
+
+/// Implemented for ADCs that have a Temperature channel
+pub trait TemperatureChannel {
+    const CHANNEL: u8;
+}
+/// Implemented for ADCs that have a Vref channel
+pub trait VrefChannel {
+    const CHANNEL: u8;
+}
+/// Implemented for ADCs that have a VBat channel
+pub trait VBatChannel {
+    const CHANNEL: u8;
+}
+
+#[cfg(stm32g4)]
+mod g4 {
+    pub use super::*;
+
+    impl TemperatureChannel for crate::peripherals::ADC1 {
+        const CHANNEL: u8 = 16;
+    }
+
+    impl VrefChannel for crate::peripherals::ADC1 {
+        const CHANNEL: u8 = 18;
+    }
+
+    impl VBatChannel for crate::peripherals::ADC1 {
+        const CHANNEL: u8 = 17;
+    }
+
+    #[cfg(peri_adc3_common)]
+    impl VrefChannel for crate::peripherals::ADC3 {
+        const CHANNEL: u8 = 18;
+    }
+
+    #[cfg(peri_adc3_common)]
+    impl VBatChannel for crate::peripherals::ADC3 {
+        const CHANNEL: u8 = 17;
+    }
+
+    #[cfg(not(stm32g4x1))]
+    impl VrefChannel for crate::peripherals::ADC4 {
+        const CHANNEL: u8 = 18;
+    }
+
+    #[cfg(not(stm32g4x1))]
+    impl TemperatureChannel for crate::peripherals::ADC5 {
+        const CHANNEL: u8 = 4;
+    }
+
+    #[cfg(not(stm32g4x1))]
+    impl VrefChannel for crate::peripherals::ADC5 {
+        const CHANNEL: u8 = 18;
+    }
+
+    #[cfg(not(stm32g4x1))]
+    impl VBatChannel for crate::peripherals::ADC5 {
+        const CHANNEL: u8 = 17;
+    }
+}
+
+// TODO this should look at each ADC individually and impl the correct channels
+#[cfg(stm32h7)]
+mod h7 {
+    impl<T: Instance> TemperatureChannel for T {
+        const CHANNEL: u8 = 18;
+    }
+    impl<T: Instance> VrefChannel for T {
+        const CHANNEL: u8 = 19;
+    }
+    impl<T: Instance> VBatChannel for T {
+        // TODO this should be 14 for H7a/b/35
+        const CHANNEL: u8 = 17;
+    }
+}
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index f46e87f38..778edc6f6 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -4,7 +4,7 @@
 #![allow(missing_docs)] // TODO
 #![cfg_attr(adc_f3_v2, allow(unused))]
 
-#[cfg(not(any(adc_f3_v2)))]
+#[cfg(not(any(adc_f3_v2, adc_wba)))]
 #[cfg_attr(adc_f1, path = "f1.rs")]
 #[cfg_attr(adc_f3, path = "f3.rs")]
 #[cfg_attr(adc_f3_v1_1, path = "f3_v1_1.rs")]
@@ -20,14 +20,14 @@ mod _version;
 use core::marker::PhantomData;
 
 #[allow(unused)]
-#[cfg(not(any(adc_f3_v2)))]
+#[cfg(not(any(adc_f3_v2, adc_wba)))]
 pub use _version::*;
 use embassy_hal_internal::{impl_peripheral, PeripheralType};
 #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
 use embassy_sync::waitqueue::AtomicWaker;
 
-#[cfg(adc_u5)]
-#[path = "u5_adc4.rs"]
+#[cfg(any(adc_u5, adc_wba))]
+#[path = "adc4.rs"]
 pub mod adc4;
 
 pub use crate::pac::adc::vals;
@@ -36,15 +36,18 @@ pub use crate::pac::adc::vals::Res as Resolution;
 pub use crate::pac::adc::vals::SampleTime;
 use crate::peripherals;
 
+#[cfg(not(adc_wba))]
 dma_trait!(RxDma, Instance);
 #[cfg(adc_u5)]
 dma_trait!(RxDma4, adc4::Instance);
+#[cfg(adc_wba)]
+dma_trait!(RxDma4, adc4::Instance);
 
 /// Analog to Digital driver.
 pub struct Adc<'d, T: Instance> {
     #[allow(unused)]
     adc: crate::Peri<'d, T>,
-    #[cfg(not(any(adc_f3_v2, adc_f3_v1_1)))]
+    #[cfg(not(any(adc_f3_v2, adc_f3_v1_1, adc_wba)))]
     sample_time: SampleTime,
 }
 
@@ -63,6 +66,7 @@ impl State {
 }
 
 trait SealedInstance {
+    #[cfg(not(adc_wba))]
     #[allow(unused)]
     fn regs() -> crate::pac::adc::Adc;
     #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
@@ -73,7 +77,7 @@ trait SealedInstance {
 }
 
 pub(crate) trait SealedAdcChannel<T> {
-    #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
+    #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
     fn setup(&mut self) {}
 
     #[allow(unused)]
@@ -110,7 +114,8 @@ pub(crate) fn blocking_delay_us(us: u32) {
     adc_h5,
     adc_h7rs,
     adc_u5,
-    adc_c0
+    adc_c0,
+    adc_wba,
 )))]
 #[allow(private_bounds)]
 pub trait Instance: SealedInstance + crate::PeripheralType {
@@ -132,7 +137,8 @@ pub trait Instance: SealedInstance + crate::PeripheralType {
     adc_h5,
     adc_h7rs,
     adc_u5,
-    adc_c0
+    adc_c0,
+    adc_wba,
 ))]
 #[allow(private_bounds)]
 pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeripheral {
@@ -144,7 +150,7 @@ pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeri
 pub trait AdcChannel<T>: SealedAdcChannel<T> + Sized {
     #[allow(unused_mut)]
     fn degrade_adc(mut self) -> AnyAdcChannel<T> {
-        #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
+        #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
         self.setup();
 
         AnyAdcChannel {
@@ -176,6 +182,36 @@ impl<T> AnyAdcChannel<T> {
         self.channel
     }
 }
+#[cfg(adc_wba)]
+foreach_adc!(
+    (ADC4, $common_inst:ident, $clock:ident) => {
+        impl crate::adc::adc4::SealedInstance for peripherals::ADC4 {
+            fn regs() -> crate::pac::adc::Adc4 {
+                crate::pac::ADC4
+            }
+        }
+
+        impl crate::adc::adc4::Instance for peripherals::ADC4 {
+            type Interrupt = crate::_generated::peripheral_interrupts::ADC4::GLOBAL;
+        }
+    };
+
+    ($inst:ident, $common_inst:ident, $clock:ident) => {
+        impl crate::adc::SealedInstance for peripherals::$inst {
+            fn regs() -> crate::pac::adc::Adc {
+                crate::pac::$inst
+            }
+
+            fn common_regs() -> crate::pac::adccommon::AdcCommon {
+                return crate::pac::$common_inst
+            }
+        }
+
+        impl crate::adc::Instance for peripherals::$inst {
+            type Interrupt = crate::_generated::peripheral_interrupts::$inst::GLOBAL;
+        }
+    };
+);
 
 #[cfg(adc_u5)]
 foreach_adc!(
@@ -208,15 +244,21 @@ foreach_adc!(
     };
 );
 
-#[cfg(not(adc_u5))]
+#[cfg(not(any(adc_u5, adc_wba)))]
 foreach_adc!(
     ($inst:ident, $common_inst:ident, $clock:ident) => {
         impl crate::adc::SealedInstance for peripherals::$inst {
+            #[cfg(not(adc_wba))]
             fn regs() -> crate::pac::adc::Adc {
                 crate::pac::$inst
             }
 
-            #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
+            #[cfg(adc_wba)]
+            fn regs() -> crate::pac::adc::Adc4 {
+                crate::pac::$inst
+            }
+
+            #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0, adc_u5, adc_wba)))]
             fn common_regs() -> crate::pac::adccommon::AdcCommon {
                 return crate::pac::$common_inst
             }
@@ -238,7 +280,7 @@ macro_rules! impl_adc_pin {
     ($inst:ident, $pin:ident, $ch:expr) => {
         impl crate::adc::AdcChannel<peripherals::$inst> for crate::Peri<'_, crate::peripherals::$pin> {}
         impl crate::adc::SealedAdcChannel<peripherals::$inst> for crate::Peri<'_, crate::peripherals::$pin> {
-            #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
+            #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
             fn setup(&mut self) {
                 <crate::peripherals::$pin as crate::gpio::SealedPin>::set_as_analog(self);
             }
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index fb6f5b7d0..7fe502da0 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -11,6 +11,9 @@ use crate::interrupt::typelevel::Interrupt;
 use crate::peripherals::ADC1;
 use crate::{interrupt, rcc, Peri};
 
+mod watchdog_v1;
+pub use watchdog_v1::WatchdogChannels;
+
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const VREF_INT: u32 = 1230;
 
@@ -21,8 +24,15 @@ pub struct InterruptHandler<T: Instance> {
 
 impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
     unsafe fn on_interrupt() {
-        if T::regs().isr().read().eoc() {
+        let isr = T::regs().isr().read();
+        let ier = T::regs().ier().read();
+        if ier.eocie() && isr.eoc() {
+            // eocie is set during adc.read()
             T::regs().ier().modify(|w| w.set_eocie(false));
+        } else if ier.awdie() && isr.awd() {
+            // awdie is set during adc.monitor_watchdog()
+            T::regs().cr().read().set_adstp(true);
+            T::regs().ier().modify(|w| w.set_awdie(false));
         } else {
             return;
         }
@@ -186,16 +196,21 @@ impl<'d, T: Instance> Adc<'d, T> {
 
         T::regs().dr().read().data()
     }
-}
 
-impl<'d, T: Instance> Drop for Adc<'d, T> {
-    fn drop(&mut self) {
+    fn teardown_adc() {
         // A.7.3 ADC disable code example
         T::regs().cr().modify(|reg| reg.set_adstp(true));
         while T::regs().cr().read().adstp() {}
 
         T::regs().cr().modify(|reg| reg.set_addis(true));
         while T::regs().cr().read().aden() {}
+    }
+}
+
+impl<'d, T: Instance> Drop for Adc<'d, T> {
+    fn drop(&mut self) {
+        Self::teardown_adc();
+        Self::teardown_awd();
 
         rcc::disable::<T>();
     }
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 7b5df80b8..805dae564 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -1,5 +1,7 @@
 use cfg_if::cfg_if;
 use pac::adc::vals::Dmacfg;
+#[cfg(adc_v3)]
+use pac::adc::vals::{OversamplingRatio, OversamplingShift, Rovsm, Trovs};
 
 use super::{
     blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
@@ -506,6 +508,23 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().cfgr2().modify(|reg| reg.set_ovse(enable));
     }
 
+    #[cfg(adc_v3)]
+    pub fn enable_regular_oversampling_mode(&mut self, mode: Rovsm, trig_mode: Trovs, enable: bool) {
+        T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
+        T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
+        T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+    }
+
+    #[cfg(adc_v3)]
+    pub fn set_oversampling_ratio(&mut self, ratio: OversamplingRatio) {
+        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+    }
+
+    #[cfg(adc_v3)]
+    pub fn set_oversampling_shift(&mut self, shift: OversamplingShift) {
+        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
+    }
+
     fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
         cfg_if! {
             if #[cfg(any(adc_g0, adc_u0))] {
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index 39e0d51b9..b0871019a 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -142,6 +142,7 @@ impl Prescaler {
 }
 
 /// Number of samples used for averaging.
+#[derive(Copy, Clone)]
 pub enum Averaging {
     Disabled,
     Samples2,
diff --git a/embassy-stm32/src/adc/watchdog_v1.rs b/embassy-stm32/src/adc/watchdog_v1.rs
new file mode 100644
index 000000000..bbe8e1971
--- /dev/null
+++ b/embassy-stm32/src/adc/watchdog_v1.rs
@@ -0,0 +1,188 @@
+use core::future::poll_fn;
+use core::task::Poll;
+
+use stm32_metapac::adc::vals::{Align, Awdsgl, Res};
+
+use crate::adc::{Adc, AdcChannel, Instance};
+
+/// This enum is passed into `Adc::init_watchdog` to specify the channels for the watchdog to monitor
+pub enum WatchdogChannels {
+    // Single channel identified by index
+    Single(u8),
+    // Multiple channels identified by mask
+    Multiple(u16),
+}
+
+impl WatchdogChannels {
+    pub fn from_channel<T>(channel: &impl AdcChannel<T>) -> Self {
+        Self::Single(channel.channel())
+    }
+
+    pub fn add_channel<T>(self, channel: &impl AdcChannel<T>) -> Self {
+        WatchdogChannels::Multiple(
+            (match self {
+                WatchdogChannels::Single(ch) => 1 << ch,
+                WatchdogChannels::Multiple(ch) => ch,
+            }) | 1 << channel.channel(),
+        )
+    }
+}
+
+impl<'d, T: Instance> Adc<'d, T> {
+    /// Configure the analog window watchdog to monitor one or more ADC channels
+    ///
+    /// `high_threshold` and `low_threshold` are expressed in the same way as ADC results. The format
+    /// depends on the values of CFGR1.ALIGN and CFGR1.RES.
+    pub fn init_watchdog(&mut self, channels: WatchdogChannels, low_threshold: u16, high_threshold: u16) {
+        Self::stop_awd();
+
+        match channels {
+            WatchdogChannels::Single(ch) => {
+                T::regs().chselr().modify(|w| {
+                    w.set_chsel_x(ch.into(), true);
+                });
+                T::regs().cfgr1().modify(|w| {
+                    w.set_awdch(ch);
+                    w.set_awdsgl(Awdsgl::SINGLE_CHANNEL)
+                });
+            }
+            WatchdogChannels::Multiple(ch) => {
+                T::regs().chselr().modify(|w| w.0 = ch.into());
+                T::regs().cfgr1().modify(|w| {
+                    w.set_awdch(0);
+                    w.set_awdsgl(Awdsgl::ALL_CHANNELS)
+                });
+            }
+        }
+
+        Self::set_watchdog_thresholds(low_threshold, high_threshold);
+        Self::setup_awd();
+    }
+
+    /// Monitor the voltage on the selected channels; return when it crosses the thresholds.
+    ///
+    /// ```rust,ignore
+    /// // Wait for pin to go high
+    /// adc.init_watchdog(WatchdogChannels::from_channel(&pin), 0, 0x07F);
+    /// let v_high = adc.monitor_watchdog().await;
+    /// info!("ADC sample is high {}", v_high);
+    /// ```
+    pub async fn monitor_watchdog(&mut self) -> u16 {
+        assert!(
+            match T::regs().cfgr1().read().awdsgl() {
+                Awdsgl::SINGLE_CHANNEL => T::regs().cfgr1().read().awdch() != 0,
+                Awdsgl::ALL_CHANNELS => T::regs().cfgr1().read().awdch() == 0,
+            },
+            "`set_channel` should be called before `monitor`",
+        );
+        assert!(T::regs().chselr().read().0 != 0);
+        T::regs().smpr().modify(|reg| reg.set_smp(self.sample_time.into()));
+        Self::start_awd();
+
+        let sample = poll_fn(|cx| {
+            T::state().waker.register(cx.waker());
+
+            if T::regs().isr().read().awd() {
+                Poll::Ready(T::regs().dr().read().data())
+            } else {
+                Poll::Pending
+            }
+        })
+        .await;
+
+        self.stop_watchdog();
+        sample
+    }
+
+    /// Stop monitoring the selected channels
+    pub fn stop_watchdog(&mut self) {
+        Self::stop_awd();
+    }
+
+    fn set_watchdog_thresholds(low_threshold: u16, high_threshold: u16) {
+        // This function takes `high_threshold` and `low_threshold` in the same alignment and resolution
+        // as ADC results, and programs them into ADC_DR. Because ADC_DR is always right-aligned on 12 bits,
+        // some bit-shifting may be necessary. See more in table 47 §13.7.1 Analog Watchdog Comparison
+
+        // Verify that the thresholds are in the correct bit positions according to alignment and resolution
+        let threshold_mask = match (T::regs().cfgr1().read().align(), T::regs().cfgr1().read().res()) {
+            (Align::LEFT, Res::BITS6) => 0x00FC,
+            (Align::LEFT, Res::BITS8) => 0xFF00,
+            (Align::LEFT, Res::BITS10) => 0xFFC0,
+            (Align::LEFT, Res::BITS12) => 0xFFF0,
+            (Align::RIGHT, Res::BITS6) => 0x003F,
+            (Align::RIGHT, Res::BITS8) => 0x00FF,
+            (Align::RIGHT, Res::BITS10) => 0x03FF,
+            (Align::RIGHT, Res::BITS12) => 0x0FFF,
+        };
+        assert!(
+            high_threshold & !threshold_mask == 0,
+            "High threshold {:x} is invalid — only bits {:x} are allowed",
+            high_threshold,
+            threshold_mask
+        );
+        assert!(
+            low_threshold & !threshold_mask == 0,
+            "Low threshold {:x} is invalid — only bits {:x} are allowed",
+            low_threshold,
+            threshold_mask
+        );
+
+        T::regs().tr().modify(|w| {
+            w.set_lt(low_threshold << threshold_mask.leading_zeros() >> 4);
+            w.set_ht(high_threshold << threshold_mask.leading_zeros() >> 4);
+        })
+    }
+
+    fn setup_awd() {
+        // Configure AWD
+        assert!(!T::regs().cr().read().adstart());
+        T::regs().cfgr1().modify(|w| w.set_awden(true));
+    }
+
+    fn start_awd() {
+        // Clear AWD interrupt flag
+        while T::regs().isr().read().awd() {
+            T::regs().isr().modify(|regs| {
+                regs.set_awd(true);
+            })
+        }
+
+        // Enable AWD interrupt
+        assert!(!T::regs().cr().read().adstart());
+        T::regs().ier().modify(|w| {
+            w.set_eocie(false);
+            w.set_awdie(true)
+        });
+
+        // Start conversion
+        T::regs().cfgr1().modify(|w| w.set_cont(true));
+        T::regs().cr().modify(|w| w.set_adstart(true));
+    }
+
+    fn stop_awd() {
+        // Stop conversion
+        while T::regs().cr().read().addis() {}
+        if T::regs().cr().read().adstart() {
+            T::regs().cr().write(|x| x.set_adstp(true));
+            while T::regs().cr().read().adstp() {}
+        }
+        T::regs().cfgr1().modify(|w| w.set_cont(false));
+
+        // Disable AWD interrupt
+        assert!(!T::regs().cr().read().adstart());
+        T::regs().ier().modify(|w| w.set_awdie(false));
+
+        // Clear AWD interrupt flag
+        while T::regs().isr().read().awd() {
+            T::regs().isr().modify(|regs| {
+                regs.set_awd(true);
+            })
+        }
+    }
+
+    pub(crate) fn teardown_awd() {
+        Self::stop_awd();
+        T::regs().cfgr1().modify(|w| w.set_awden(false));
+    }
+}
diff --git a/embassy-stm32/src/can/bxcan/mod.rs b/embassy-stm32/src/can/bxcan/mod.rs
index 305666d5b..4c0795a2a 100644
--- a/embassy-stm32/src/can/bxcan/mod.rs
+++ b/embassy-stm32/src/can/bxcan/mod.rs
@@ -15,9 +15,10 @@ pub use embedded_can::{ExtendedId, Id, StandardId};
 use self::filter::MasterFilters;
 use self::registers::{Registers, RxFifo};
 pub use super::common::{BufferedCanReceiver, BufferedCanSender};
+use super::common::{InfoRef, RxInfoRef, TxInfoRef};
 use super::frame::{Envelope, Frame};
 use super::util;
-use crate::can::enums::{BusError, InternalOperation, TryReadError};
+use crate::can::enums::{BusError, RefCountOp, TryReadError};
 use crate::gpio::{AfType, OutputType, Pull, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
@@ -35,7 +36,9 @@ impl<T: Instance> interrupt::typelevel::Handler<T::TXInterrupt> for TxInterruptH
             v.set_rqcp(1, true);
             v.set_rqcp(2, true);
         });
-        T::state().tx_mode.on_interrupt::<T>();
+        T::info().state.lock(|state| {
+            state.borrow().tx_mode.on_interrupt::<T>();
+        });
     }
 }
 
@@ -46,7 +49,9 @@ pub struct Rx0InterruptHandler<T: Instance> {
 
 impl<T: Instance> interrupt::typelevel::Handler<T::RX0Interrupt> for Rx0InterruptHandler<T> {
     unsafe fn on_interrupt() {
-        T::state().rx_mode.on_interrupt::<T>(RxFifo::Fifo0);
+        T::info().state.lock(|state| {
+            state.borrow().rx_mode.on_interrupt::<T>(RxFifo::Fifo0);
+        });
     }
 }
 
@@ -57,7 +62,9 @@ pub struct Rx1InterruptHandler<T: Instance> {
 
 impl<T: Instance> interrupt::typelevel::Handler<T::RX1Interrupt> for Rx1InterruptHandler<T> {
     unsafe fn on_interrupt() {
-        T::state().rx_mode.on_interrupt::<T>(RxFifo::Fifo1);
+        T::info().state.lock(|state| {
+            state.borrow().rx_mode.on_interrupt::<T>(RxFifo::Fifo1);
+        });
     }
 }
 
@@ -73,7 +80,9 @@ impl<T: Instance> interrupt::typelevel::Handler<T::SCEInterrupt> for SceInterrup
 
         if msr_val.slaki() {
             msr.modify(|m| m.set_slaki(true));
-            T::state().err_waker.wake();
+            T::info().state.lock(|state| {
+                state.borrow().err_waker.wake();
+            });
         } else if msr_val.erri() {
             // Disable the interrupt, but don't acknowledge the error, so that it can be
             // forwarded off the bus message consumer. If we don't provide some way for
@@ -82,8 +91,9 @@ impl<T: Instance> interrupt::typelevel::Handler<T::SCEInterrupt> for SceInterrup
             // an indefinite amount of time.
             let ier = T::regs().ier();
             ier.modify(|i| i.set_errie(false));
-
-            T::state().err_waker.wake();
+            T::info().state.lock(|state| {
+                state.borrow().err_waker.wake();
+            });
         }
     }
 }
@@ -91,7 +101,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::SCEInterrupt> for SceInterrup
 /// Configuration proxy returned by [`Can::modify_config`].
 pub struct CanConfig<'a> {
     phantom: PhantomData<&'a ()>,
-    info: &'static Info,
+    info: InfoRef,
     periph_clock: crate::time::Hertz,
 }
 
@@ -156,8 +166,7 @@ impl Drop for CanConfig<'_> {
 /// CAN driver
 pub struct Can<'d> {
     phantom: PhantomData<&'d ()>,
-    info: &'static Info,
-    state: &'static State,
+    info: InfoRef,
     periph_clock: crate::time::Hertz,
 }
 
@@ -227,8 +236,7 @@ impl<'d> Can<'d> {
 
         Self {
             phantom: PhantomData,
-            info: T::info(),
-            state: T::state(),
+            info: InfoRef::new(T::info()),
             periph_clock: T::frequency(),
         }
     }
@@ -248,7 +256,7 @@ impl<'d> Can<'d> {
 
         CanConfig {
             phantom: self.phantom,
-            info: self.info,
+            info: InfoRef::new(&self.info),
             periph_clock: self.periph_clock,
         }
     }
@@ -297,7 +305,9 @@ impl<'d> Can<'d> {
         self.info.regs.0.mcr().modify(|m| m.set_sleep(true));
 
         poll_fn(|cx| {
-            self.state.err_waker.register(cx.waker());
+            self.info.state.lock(|s| {
+                s.borrow().err_waker.register(cx.waker());
+            });
             if self.is_sleeping() {
                 Poll::Ready(())
             } else {
@@ -350,8 +360,7 @@ impl<'d> Can<'d> {
     pub async fn flush(&self, mb: Mailbox) {
         CanTx {
             _phantom: PhantomData,
-            info: self.info,
-            state: self.state,
+            info: TxInfoRef::new(&self.info),
         }
         .flush_inner(mb)
         .await;
@@ -366,8 +375,7 @@ impl<'d> Can<'d> {
     pub async fn flush_any(&self) {
         CanTx {
             _phantom: PhantomData,
-            info: self.info,
-            state: self.state,
+            info: TxInfoRef::new(&self.info),
         }
         .flush_any_inner()
         .await
@@ -377,8 +385,7 @@ impl<'d> Can<'d> {
     pub async fn flush_all(&self) {
         CanTx {
             _phantom: PhantomData,
-            info: self.info,
-            state: self.state,
+            info: TxInfoRef::new(&self.info),
         }
         .flush_all_inner()
         .await
@@ -406,19 +413,19 @@ impl<'d> Can<'d> {
     ///
     /// Returns a tuple of the time the message was received and the message frame
     pub async fn read(&mut self) -> Result<Envelope, BusError> {
-        self.state.rx_mode.read(self.info, self.state).await
+        RxMode::read(&self.info).await
     }
 
     /// Attempts to read a CAN frame without blocking.
     ///
     /// Returns [Err(TryReadError::Empty)] if there are no frames in the rx queue.
     pub fn try_read(&mut self) -> Result<Envelope, TryReadError> {
-        self.state.rx_mode.try_read(self.info)
+        RxMode::try_read(&self.info)
     }
 
     /// Waits while receive queue is empty.
     pub async fn wait_not_empty(&mut self) {
-        self.state.rx_mode.wait_not_empty(self.info, self.state).await
+        RxMode::wait_not_empty(&self.info).await
     }
 
     /// Split the CAN driver into transmit and receive halves.
@@ -428,13 +435,11 @@ impl<'d> Can<'d> {
         (
             CanTx {
                 _phantom: PhantomData,
-                info: self.info,
-                state: self.state,
+                info: TxInfoRef::new(&self.info),
             },
             CanRx {
                 _phantom: PhantomData,
-                info: self.info,
-                state: self.state,
+                info: RxInfoRef::new(&self.info),
             },
         )
     }
@@ -459,7 +464,7 @@ impl<'d> Can<'d> {
     /// To modify filters of a slave peripheral, `modify_filters` has to be called on the master
     /// peripheral instead.
     pub fn modify_filters(&mut self) -> MasterFilters<'_> {
-        unsafe { MasterFilters::new(self.info) }
+        unsafe { MasterFilters::new(&self.info) }
     }
 }
 
@@ -514,8 +519,7 @@ impl<'d, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d, TX_
 /// CAN driver, transmit half.
 pub struct CanTx<'d> {
     _phantom: PhantomData<&'d ()>,
-    info: &'static Info,
-    state: &'static State,
+    info: TxInfoRef,
 }
 
 impl<'d> CanTx<'d> {
@@ -524,7 +528,9 @@ impl<'d> CanTx<'d> {
     /// If the TX queue is full, this will wait until there is space, therefore exerting backpressure.
     pub async fn write(&mut self, frame: &Frame) -> TransmitStatus {
         poll_fn(|cx| {
-            self.state.tx_mode.register(cx.waker());
+            self.info.state.lock(|s| {
+                s.borrow().tx_mode.register(cx.waker());
+            });
             if let Ok(status) = self.info.regs.transmit(frame) {
                 return Poll::Ready(status);
             }
@@ -549,7 +555,9 @@ impl<'d> CanTx<'d> {
 
     async fn flush_inner(&self, mb: Mailbox) {
         poll_fn(|cx| {
-            self.state.tx_mode.register(cx.waker());
+            self.info.state.lock(|s| {
+                s.borrow().tx_mode.register(cx.waker());
+            });
             if self.info.regs.0.tsr().read().tme(mb.index()) {
                 return Poll::Ready(());
             }
@@ -566,7 +574,9 @@ impl<'d> CanTx<'d> {
 
     async fn flush_any_inner(&self) {
         poll_fn(|cx| {
-            self.state.tx_mode.register(cx.waker());
+            self.info.state.lock(|s| {
+                s.borrow().tx_mode.register(cx.waker());
+            });
 
             let tsr = self.info.regs.0.tsr().read();
             if tsr.tme(Mailbox::Mailbox0.index())
@@ -593,7 +603,9 @@ impl<'d> CanTx<'d> {
 
     async fn flush_all_inner(&self) {
         poll_fn(|cx| {
-            self.state.tx_mode.register(cx.waker());
+            self.info.state.lock(|s| {
+                s.borrow().tx_mode.register(cx.waker());
+            });
 
             let tsr = self.info.regs.0.tsr().read();
             if tsr.tme(Mailbox::Mailbox0.index())
@@ -634,7 +646,7 @@ impl<'d> CanTx<'d> {
         self,
         txb: &'static mut TxBuf<TX_BUF_SIZE>,
     ) -> BufferedCanTx<'d, TX_BUF_SIZE> {
-        BufferedCanTx::new(self.info, self.state, self, txb)
+        BufferedCanTx::new(&self.info, self, txb)
     }
 }
 
@@ -643,17 +655,15 @@ pub type TxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, Frame,
 
 /// Buffered CAN driver, transmit half.
 pub struct BufferedCanTx<'d, const TX_BUF_SIZE: usize> {
-    info: &'static Info,
-    state: &'static State,
+    info: TxInfoRef,
     _tx: CanTx<'d>,
     tx_buf: &'static TxBuf<TX_BUF_SIZE>,
 }
 
 impl<'d, const TX_BUF_SIZE: usize> BufferedCanTx<'d, TX_BUF_SIZE> {
-    fn new(info: &'static Info, state: &'static State, _tx: CanTx<'d>, tx_buf: &'static TxBuf<TX_BUF_SIZE>) -> Self {
+    fn new(info: &'static Info, _tx: CanTx<'d>, tx_buf: &'static TxBuf<TX_BUF_SIZE>) -> Self {
         Self {
-            info,
-            state,
+            info: TxInfoRef::new(info),
             _tx,
             tx_buf,
         }
@@ -666,11 +676,9 @@ impl<'d, const TX_BUF_SIZE: usize> BufferedCanTx<'d, TX_BUF_SIZE> {
             let tx_inner = super::common::ClassicBufferedTxInner {
                 tx_receiver: self.tx_buf.receiver().into(),
             };
-            let state = self.state as *const State;
-            unsafe {
-                let mut_state = state as *mut State;
-                (*mut_state).tx_mode = TxMode::Buffered(tx_inner);
-            }
+            self.info.state.lock(|s| {
+                s.borrow_mut().tx_mode = TxMode::Buffered(tx_inner);
+            });
         });
         self
     }
@@ -684,27 +692,18 @@ impl<'d, const TX_BUF_SIZE: usize> BufferedCanTx<'d, TX_BUF_SIZE> {
 
     /// Returns a sender that can be used for sending CAN frames.
     pub fn writer(&self) -> BufferedCanSender {
-        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
         BufferedCanSender {
             tx_buf: self.tx_buf.sender().into(),
-            waker: self.info.tx_waker,
-            internal_operation: self.info.internal_operation,
+            info: TxInfoRef::new(&self.info),
         }
     }
 }
 
-impl<'d, const TX_BUF_SIZE: usize> Drop for BufferedCanTx<'d, TX_BUF_SIZE> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-    }
-}
-
 /// CAN driver, receive half.
 #[allow(dead_code)]
 pub struct CanRx<'d> {
     _phantom: PhantomData<&'d ()>,
-    info: &'static Info,
-    state: &'static State,
+    info: RxInfoRef,
 }
 
 impl<'d> CanRx<'d> {
@@ -714,19 +713,19 @@ impl<'d> CanRx<'d> {
     ///
     /// Returns a tuple of the time the message was received and the message frame
     pub async fn read(&mut self) -> Result<Envelope, BusError> {
-        self.state.rx_mode.read(self.info, self.state).await
+        RxMode::read(&self.info).await
     }
 
     /// Attempts to read a CAN frame without blocking.
     ///
     /// Returns [Err(TryReadError::Empty)] if there are no frames in the rx queue.
     pub fn try_read(&mut self) -> Result<Envelope, TryReadError> {
-        self.state.rx_mode.try_read(self.info)
+        RxMode::try_read(&self.info)
     }
 
     /// Waits while receive queue is empty.
     pub async fn wait_not_empty(&mut self) {
-        self.state.rx_mode.wait_not_empty(self.info, self.state).await
+        RxMode::wait_not_empty(&self.info).await
     }
 
     /// Return a buffered instance of driver. User must supply Buffers
@@ -734,7 +733,7 @@ impl<'d> CanRx<'d> {
         self,
         rxb: &'static mut RxBuf<RX_BUF_SIZE>,
     ) -> BufferedCanRx<'d, RX_BUF_SIZE> {
-        BufferedCanRx::new(self.info, self.state, self, rxb)
+        BufferedCanRx::new(&self.info, self, rxb)
     }
 
     /// Accesses the filter banks owned by this CAN peripheral.
@@ -742,7 +741,7 @@ impl<'d> CanRx<'d> {
     /// To modify filters of a slave peripheral, `modify_filters` has to be called on the master
     /// peripheral instead.
     pub fn modify_filters(&mut self) -> MasterFilters<'_> {
-        unsafe { MasterFilters::new(self.info) }
+        unsafe { MasterFilters::new(&self.info) }
     }
 }
 
@@ -751,17 +750,15 @@ pub type RxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, Result<
 
 /// CAN driver, receive half in Buffered mode.
 pub struct BufferedCanRx<'d, const RX_BUF_SIZE: usize> {
-    info: &'static Info,
-    state: &'static State,
+    info: RxInfoRef,
     rx: CanRx<'d>,
     rx_buf: &'static RxBuf<RX_BUF_SIZE>,
 }
 
 impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
-    fn new(info: &'static Info, state: &'static State, rx: CanRx<'d>, rx_buf: &'static RxBuf<RX_BUF_SIZE>) -> Self {
+    fn new(info: &'static Info, rx: CanRx<'d>, rx_buf: &'static RxBuf<RX_BUF_SIZE>) -> Self {
         BufferedCanRx {
-            info,
-            state,
+            info: RxInfoRef::new(info),
             rx,
             rx_buf,
         }
@@ -774,11 +771,9 @@ impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
             let rx_inner = super::common::ClassicBufferedRxInner {
                 rx_sender: self.rx_buf.sender().into(),
             };
-            let state = self.state as *const State;
-            unsafe {
-                let mut_state = state as *mut State;
-                (*mut_state).rx_mode = RxMode::Buffered(rx_inner);
-            }
+            self.info.state.lock(|s| {
+                s.borrow_mut().rx_mode = RxMode::Buffered(rx_inner);
+            });
         });
         self
     }
@@ -792,7 +787,7 @@ impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
     ///
     /// Returns [Err(TryReadError::Empty)] if there are no frames in the rx queue.
     pub fn try_read(&mut self) -> Result<Envelope, TryReadError> {
-        match &self.state.rx_mode {
+        self.info.state.lock(|s| match &s.borrow().rx_mode {
             RxMode::Buffered(_) => {
                 if let Ok(result) = self.rx_buf.try_receive() {
                     match result {
@@ -810,7 +805,7 @@ impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
             _ => {
                 panic!("Bad Mode")
             }
-        }
+        })
     }
 
     /// Waits while receive queue is empty.
@@ -820,10 +815,9 @@ impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
 
     /// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
     pub fn reader(&self) -> BufferedCanReceiver {
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         BufferedCanReceiver {
             rx_buf: self.rx_buf.receiver().into(),
-            internal_operation: self.info.internal_operation,
+            info: RxInfoRef::new(&self.info),
         }
     }
 
@@ -836,12 +830,6 @@ impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
     }
 }
 
-impl<'d, const RX_BUF_SIZE: usize> Drop for BufferedCanRx<'d, RX_BUF_SIZE> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-    }
-}
-
 impl Drop for Can<'_> {
     fn drop(&mut self) {
         // Cannot call `free()` because it moves the instance.
@@ -929,27 +917,30 @@ impl RxMode {
         }
     }
 
-    pub(crate) async fn read(&self, info: &Info, state: &State) -> Result<Envelope, BusError> {
-        match self {
-            Self::NonBuffered(waker) => {
-                poll_fn(|cx| {
-                    state.err_waker.register(cx.waker());
-                    waker.register(cx.waker());
-                    match self.try_read(info) {
-                        Ok(result) => Poll::Ready(Ok(result)),
-                        Err(TryReadError::Empty) => Poll::Pending,
-                        Err(TryReadError::BusError(be)) => Poll::Ready(Err(be)),
+    pub(crate) async fn read(info: &Info) -> Result<Envelope, BusError> {
+        poll_fn(|cx| {
+            info.state.lock(|state| {
+                let state = state.borrow();
+                state.err_waker.register(cx.waker());
+                match &state.rx_mode {
+                    Self::NonBuffered(waker) => {
+                        waker.register(cx.waker());
                     }
-                })
-                .await
-            }
-            _ => {
-                panic!("Bad Mode")
+                    _ => {
+                        panic!("Bad Mode")
+                    }
+                }
+            });
+            match RxMode::try_read(info) {
+                Ok(result) => Poll::Ready(Ok(result)),
+                Err(TryReadError::Empty) => Poll::Pending,
+                Err(TryReadError::BusError(be)) => Poll::Ready(Err(be)),
             }
-        }
+        })
+        .await
     }
-    pub(crate) fn try_read(&self, info: &Info) -> Result<Envelope, TryReadError> {
-        match self {
+    pub(crate) fn try_read(info: &Info) -> Result<Envelope, TryReadError> {
+        info.state.lock(|state| match state.borrow().rx_mode {
             Self::NonBuffered(_) => {
                 let registers = &info.regs;
                 if let Some(msg) = registers.receive_fifo(RxFifo::Fifo0) {
@@ -975,25 +966,28 @@ impl RxMode {
             _ => {
                 panic!("Bad Mode")
             }
-        }
+        })
     }
-    pub(crate) async fn wait_not_empty(&self, info: &Info, state: &State) {
-        match &state.rx_mode {
-            Self::NonBuffered(waker) => {
-                poll_fn(|cx| {
-                    waker.register(cx.waker());
-                    if info.regs.receive_frame_available() {
-                        Poll::Ready(())
-                    } else {
-                        Poll::Pending
+    pub(crate) async fn wait_not_empty(info: &Info) {
+        poll_fn(|cx| {
+            info.state.lock(|s| {
+                let state = s.borrow();
+                match &state.rx_mode {
+                    Self::NonBuffered(waker) => {
+                        waker.register(cx.waker());
                     }
-                })
-                .await
-            }
-            _ => {
-                panic!("Bad Mode")
+                    _ => {
+                        panic!("Bad Mode")
+                    }
+                }
+            });
+            if info.regs.receive_frame_available() {
+                Poll::Ready(())
+            } else {
+                Poll::Pending
             }
-        }
+        })
+        .await
     }
 }
 
@@ -1008,21 +1002,25 @@ impl TxMode {
         tsr.tme(Mailbox::Mailbox0.index()) || tsr.tme(Mailbox::Mailbox1.index()) || tsr.tme(Mailbox::Mailbox2.index())
     }
     pub fn on_interrupt<T: Instance>(&self) {
-        match &T::state().tx_mode {
-            TxMode::NonBuffered(waker) => waker.wake(),
-            TxMode::Buffered(buf) => {
-                while self.buffer_free::<T>() {
-                    match buf.tx_receiver.try_receive() {
-                        Ok(frame) => {
-                            _ = Registers(T::regs()).transmit(&frame);
-                        }
-                        Err(_) => {
-                            break;
+        T::info().state.lock(|state| {
+            let tx_mode = &state.borrow().tx_mode;
+
+            match tx_mode {
+                TxMode::NonBuffered(waker) => waker.wake(),
+                TxMode::Buffered(buf) => {
+                    while self.buffer_free::<T>() {
+                        match buf.tx_receiver.try_receive() {
+                            Ok(frame) => {
+                                _ = Registers(T::regs()).transmit(&frame);
+                            }
+                            Err(_) => {
+                                break;
+                            }
                         }
                     }
                 }
             }
-        }
+        });
     }
 
     fn register(&self, arg: &core::task::Waker) {
@@ -1057,14 +1055,15 @@ impl State {
     }
 }
 
+type SharedState = embassy_sync::blocking_mutex::Mutex<CriticalSectionRawMutex, core::cell::RefCell<State>>;
 pub(crate) struct Info {
     regs: Registers,
     tx_interrupt: crate::interrupt::Interrupt,
     rx0_interrupt: crate::interrupt::Interrupt,
     rx1_interrupt: crate::interrupt::Interrupt,
     sce_interrupt: crate::interrupt::Interrupt,
-    tx_waker: fn(),
-    internal_operation: fn(InternalOperation),
+    pub(crate) tx_waker: fn(),
+    state: SharedState,
 
     /// The total number of filter banks available to the instance.
     ///
@@ -1072,12 +1071,37 @@ pub(crate) struct Info {
     num_filter_banks: u8,
 }
 
+impl Info {
+    pub(crate) fn adjust_reference_counter(&self, val: RefCountOp) {
+        self.state.lock(|s| {
+            let mut mut_state = s.borrow_mut();
+            match val {
+                RefCountOp::NotifySenderCreated => {
+                    mut_state.sender_instance_count += 1;
+                }
+                RefCountOp::NotifySenderDestroyed => {
+                    mut_state.sender_instance_count -= 1;
+                    if 0 == mut_state.sender_instance_count {
+                        (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+                    }
+                }
+                RefCountOp::NotifyReceiverCreated => {
+                    mut_state.receiver_instance_count += 1;
+                }
+                RefCountOp::NotifyReceiverDestroyed => {
+                    mut_state.receiver_instance_count -= 1;
+                    if 0 == mut_state.receiver_instance_count {
+                        (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+                    }
+                }
+            }
+        });
+    }
+}
+
 trait SealedInstance {
     fn info() -> &'static Info;
     fn regs() -> crate::pac::can::Can;
-    fn state() -> &'static State;
-    unsafe fn mut_state() -> &'static mut State;
-    fn internal_operation(val: InternalOperation);
 }
 
 /// CAN instance trait.
@@ -1135,53 +1159,14 @@ foreach_peripheral!(
                     rx1_interrupt: crate::_generated::peripheral_interrupts::$inst::RX1::IRQ,
                     sce_interrupt: crate::_generated::peripheral_interrupts::$inst::SCE::IRQ,
                     tx_waker: crate::_generated::peripheral_interrupts::$inst::TX::pend,
-                    internal_operation: peripherals::$inst::internal_operation,
                     num_filter_banks: peripherals::$inst::NUM_FILTER_BANKS,
+                    state: embassy_sync::blocking_mutex::Mutex::new(core::cell::RefCell::new(State::new())),
                 };
                 &INFO
             }
             fn regs() -> crate::pac::can::Can {
                 crate::pac::$inst
             }
-
-            unsafe fn mut_state() -> & 'static mut State {
-                static mut STATE: State = State::new();
-                &mut *core::ptr::addr_of_mut!(STATE)
-            }
-            fn state() -> &'static State {
-                unsafe { peripherals::$inst::mut_state() }
-            }
-
-
-            fn internal_operation(val: InternalOperation) {
-                critical_section::with(|_| {
-                    //let state = self.state as *const State;
-                    unsafe {
-                        //let mut_state = state as *mut State;
-                        let mut_state = peripherals::$inst::mut_state();
-                        match val {
-                            InternalOperation::NotifySenderCreated => {
-                                mut_state.sender_instance_count += 1;
-                            }
-                            InternalOperation::NotifySenderDestroyed => {
-                                mut_state.sender_instance_count -= 1;
-                                if ( 0 == mut_state.sender_instance_count) {
-                                    (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-                                }
-                            }
-                            InternalOperation::NotifyReceiverCreated => {
-                                mut_state.receiver_instance_count += 1;
-                            }
-                            InternalOperation::NotifyReceiverDestroyed => {
-                                mut_state.receiver_instance_count -= 1;
-                                if ( 0 == mut_state.receiver_instance_count) {
-                                    (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-                                }
-                            }
-                        }
-                    }
-                });
-            }
         }
 
         impl Instance for peripherals::$inst {
diff --git a/embassy-stm32/src/can/common.rs b/embassy-stm32/src/can/common.rs
index 386d4467c..980f33a04 100644
--- a/embassy-stm32/src/can/common.rs
+++ b/embassy-stm32/src/can/common.rs
@@ -24,22 +24,21 @@ pub(crate) struct FdBufferedTxInner {
 /// Sender that can be used for sending CAN frames.
 pub struct BufferedSender<'ch, FRAME> {
     pub(crate) tx_buf: embassy_sync::channel::SendDynamicSender<'ch, FRAME>,
-    pub(crate) waker: fn(),
-    pub(crate) internal_operation: fn(InternalOperation),
+    pub(crate) info: TxInfoRef,
 }
 
 impl<'ch, FRAME> BufferedSender<'ch, FRAME> {
     /// Async write frame to TX buffer.
     pub fn try_write(&mut self, frame: FRAME) -> Result<(), embassy_sync::channel::TrySendError<FRAME>> {
         self.tx_buf.try_send(frame)?;
-        (self.waker)();
+        (self.info.tx_waker)();
         Ok(())
     }
 
     /// Async write frame to TX buffer.
     pub async fn write(&mut self, frame: FRAME) {
         self.tx_buf.send(frame).await;
-        (self.waker)();
+        (self.info.tx_waker)();
     }
 
     /// Allows a poll_fn to poll until the channel is ready to write
@@ -50,28 +49,20 @@ impl<'ch, FRAME> BufferedSender<'ch, FRAME> {
 
 impl<'ch, FRAME> Clone for BufferedSender<'ch, FRAME> {
     fn clone(&self) -> Self {
-        (self.internal_operation)(InternalOperation::NotifySenderCreated);
         Self {
             tx_buf: self.tx_buf,
-            waker: self.waker,
-            internal_operation: self.internal_operation,
+            info: TxInfoRef::new(&self.info),
         }
     }
 }
 
-impl<'ch, FRAME> Drop for BufferedSender<'ch, FRAME> {
-    fn drop(&mut self) {
-        (self.internal_operation)(InternalOperation::NotifySenderDestroyed);
-    }
-}
-
 /// Sender that can be used for sending Classic CAN frames.
 pub type BufferedCanSender = BufferedSender<'static, Frame>;
 
 /// Receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
 pub struct BufferedReceiver<'ch, ENVELOPE> {
     pub(crate) rx_buf: embassy_sync::channel::SendDynamicReceiver<'ch, Result<ENVELOPE, BusError>>,
-    pub(crate) internal_operation: fn(InternalOperation),
+    pub(crate) info: RxInfoRef,
 }
 
 impl<'ch, ENVELOPE> BufferedReceiver<'ch, ENVELOPE> {
@@ -106,19 +97,99 @@ impl<'ch, ENVELOPE> BufferedReceiver<'ch, ENVELOPE> {
 
 impl<'ch, ENVELOPE> Clone for BufferedReceiver<'ch, ENVELOPE> {
     fn clone(&self) -> Self {
-        (self.internal_operation)(InternalOperation::NotifyReceiverCreated);
         Self {
             rx_buf: self.rx_buf,
-            internal_operation: self.internal_operation,
+            info: RxInfoRef::new(&self.info),
         }
     }
 }
 
-impl<'ch, ENVELOPE> Drop for BufferedReceiver<'ch, ENVELOPE> {
+/// A BufferedCanReceiver for Classic CAN frames.
+pub type BufferedCanReceiver = BufferedReceiver<'static, Envelope>;
+
+/// Provides a reference to the driver internals and implements RAII for the internal reference
+/// counting. Each type that can operate on the driver should contain either InfoRef
+/// or the similar TxInfoRef or RxInfoRef. The new method and the Drop impl will automatically
+/// call the reference counting function. Like this, the reference counting function does not
+/// need to be called manually for each type.
+pub(crate) struct InfoRef {
+    info: &'static super::Info,
+}
+impl InfoRef {
+    pub(crate) fn new(info: &'static super::Info) -> Self {
+        info.adjust_reference_counter(RefCountOp::NotifyReceiverCreated);
+        info.adjust_reference_counter(RefCountOp::NotifySenderCreated);
+        Self { info }
+    }
+}
+
+impl Drop for InfoRef {
     fn drop(&mut self) {
-        (self.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
+        self.info.adjust_reference_counter(RefCountOp::NotifyReceiverDestroyed);
+        self.info.adjust_reference_counter(RefCountOp::NotifySenderDestroyed);
     }
 }
 
-/// A BufferedCanReceiver for Classic CAN frames.
-pub type BufferedCanReceiver = BufferedReceiver<'static, Envelope>;
+impl core::ops::Deref for InfoRef {
+    type Target = &'static super::Info;
+
+    fn deref(&self) -> &Self::Target {
+        &self.info
+    }
+}
+
+/// Provides a reference to the driver internals and implements RAII for the internal reference
+/// counting for Tx only types.
+/// See InfoRef for further doc.
+pub(crate) struct TxInfoRef {
+    info: &'static super::Info,
+}
+
+impl TxInfoRef {
+    pub(crate) fn new(info: &'static super::Info) -> Self {
+        info.adjust_reference_counter(RefCountOp::NotifySenderCreated);
+        Self { info }
+    }
+}
+
+impl Drop for TxInfoRef {
+    fn drop(&mut self) {
+        self.info.adjust_reference_counter(RefCountOp::NotifySenderDestroyed);
+    }
+}
+
+impl core::ops::Deref for TxInfoRef {
+    type Target = &'static super::Info;
+
+    fn deref(&self) -> &Self::Target {
+        &self.info
+    }
+}
+
+/// Provides a reference to the driver internals and implements RAII for the internal reference
+/// counting for Rx only types.
+/// See InfoRef for further doc.
+pub(crate) struct RxInfoRef {
+    info: &'static super::Info,
+}
+
+impl RxInfoRef {
+    pub(crate) fn new(info: &'static super::Info) -> Self {
+        info.adjust_reference_counter(RefCountOp::NotifyReceiverCreated);
+        Self { info }
+    }
+}
+
+impl Drop for RxInfoRef {
+    fn drop(&mut self) {
+        self.info.adjust_reference_counter(RefCountOp::NotifyReceiverDestroyed);
+    }
+}
+
+impl core::ops::Deref for RxInfoRef {
+    type Target = &'static super::Info;
+
+    fn deref(&self) -> &Self::Target {
+        &self.info
+    }
+}
diff --git a/embassy-stm32/src/can/enums.rs b/embassy-stm32/src/can/enums.rs
index 97cb47640..6d91020fc 100644
--- a/embassy-stm32/src/can/enums.rs
+++ b/embassy-stm32/src/can/enums.rs
@@ -72,7 +72,7 @@ pub enum TryReadError {
 /// Internal Operation
 #[derive(Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum InternalOperation {
+pub enum RefCountOp {
     /// Notify receiver created
     NotifyReceiverCreated,
     /// Notify receiver destroyed
diff --git a/embassy-stm32/src/can/fd/message_ram/extended_filter.rs b/embassy-stm32/src/can/fd/message_ram/extended_filter.rs
index 453e9056e..ac47901a8 100644
--- a/embassy-stm32/src/can/fd/message_ram/extended_filter.rs
+++ b/embassy-stm32/src/can/fd/message_ram/extended_filter.rs
@@ -115,22 +115,22 @@ impl R {
 impl W {
     #[doc = "Byte 0 - Bits 0:28 - EFID1"]
     #[inline(always)]
-    pub fn efid1(&mut self) -> EFID1_W {
+    pub fn efid1(&mut self) -> EFID1_W<'_> {
         EFID1_W { w: self }
     }
     #[doc = "Byte 0 - Bits 29:31 - EFEC"]
     #[inline(always)]
-    pub fn efec(&mut self) -> EFEC_W {
+    pub fn efec(&mut self) -> EFEC_W<'_> {
         EFEC_W { w: self }
     }
     #[doc = "Byte 1 - Bits 0:28 - EFID2"]
     #[inline(always)]
-    pub fn efid2(&mut self) -> EFID2_W {
+    pub fn efid2(&mut self) -> EFID2_W<'_> {
         EFID2_W { w: self }
     }
     #[doc = "Byte 1 - Bits 30:31 - EFT"]
     #[inline(always)]
-    pub fn eft(&mut self) -> EFT_W {
+    pub fn eft(&mut self) -> EFT_W<'_> {
         EFT_W { w: self }
     }
 }
diff --git a/embassy-stm32/src/can/fd/message_ram/standard_filter.rs b/embassy-stm32/src/can/fd/message_ram/standard_filter.rs
index 3a3bbcf12..f52646bfe 100644
--- a/embassy-stm32/src/can/fd/message_ram/standard_filter.rs
+++ b/embassy-stm32/src/can/fd/message_ram/standard_filter.rs
@@ -115,22 +115,22 @@ impl R {
 impl W {
     #[doc = "Bits 0:10 - SFID2"]
     #[inline(always)]
-    pub fn sfid2(&mut self) -> SFID2_W {
+    pub fn sfid2(&mut self) -> SFID2_W<'_> {
         SFID2_W { w: self }
     }
     #[doc = "Bits 16:26 - SFID1"]
     #[inline(always)]
-    pub fn sfid1(&mut self) -> SFID1_W {
+    pub fn sfid1(&mut self) -> SFID1_W<'_> {
         SFID1_W { w: self }
     }
     #[doc = "Bits 27:29 - SFEC"]
     #[inline(always)]
-    pub fn sfec(&mut self) -> SFEC_W {
+    pub fn sfec(&mut self) -> SFEC_W<'_> {
         SFEC_W { w: self }
     }
     #[doc = "Bits 30:31 - SFT"]
     #[inline(always)]
-    pub fn sft(&mut self) -> SFT_W {
+    pub fn sft(&mut self) -> SFT_W<'_> {
         SFT_W { w: self }
     }
 }
diff --git a/embassy-stm32/src/can/fd/message_ram/txbuffer_element.rs b/embassy-stm32/src/can/fd/message_ram/txbuffer_element.rs
index 455406a1c..6d65a86cb 100644
--- a/embassy-stm32/src/can/fd/message_ram/txbuffer_element.rs
+++ b/embassy-stm32/src/can/fd/message_ram/txbuffer_element.rs
@@ -376,47 +376,47 @@ impl R {
 impl W {
     #[doc = "Byte 0 - Bits 0:28 - ID"]
     #[inline(always)]
-    pub fn id(&mut self) -> ID_W {
+    pub fn id(&mut self) -> ID_W<'_> {
         ID_W { w: self }
     }
     #[doc = "Byte 0 - Bit 29 - RTR"]
     #[inline(always)]
-    pub fn rtr(&mut self) -> RTR_W {
+    pub fn rtr(&mut self) -> RTR_W<'_> {
         RTR_W { w: self }
     }
     #[doc = "Byte 0 - Bit 30 - XTD"]
     #[inline(always)]
-    pub fn xtd(&mut self) -> XTD_W {
+    pub fn xtd(&mut self) -> XTD_W<'_> {
         XTD_W { w: self }
     }
     #[doc = "Byte 0 - Bit 31 - ESI"]
     #[inline(always)]
-    pub fn esi(&mut self) -> ESI_W {
+    pub fn esi(&mut self) -> ESI_W<'_> {
         ESI_W { w: self }
     }
     #[doc = "Byte 1 - Bit 16:19 - DLC"]
     #[inline(always)]
-    pub fn dlc(&mut self) -> DLC_W {
+    pub fn dlc(&mut self) -> DLC_W<'_> {
         DLC_W { w: self }
     }
     #[doc = "Byte 1 - Bit 20 - BRS"]
     #[inline(always)]
-    pub fn brs(&mut self) -> BRS_W {
+    pub fn brs(&mut self) -> BRS_W<'_> {
         BRS_W { w: self }
     }
     #[doc = "Byte 1 - Bit 21 - FDF"]
     #[inline(always)]
-    pub fn fdf(&mut self) -> FDF_W {
+    pub fn fdf(&mut self) -> FDF_W<'_> {
         FDF_W { w: self }
     }
     #[doc = "Byte 1 - Bit 23 - EFC"]
     #[inline(always)]
-    pub fn efc(&mut self) -> EFC_W {
+    pub fn efc(&mut self) -> EFC_W<'_> {
         EFC_W { w: self }
     }
     #[doc = "Byte 1 - Bit 24:31 - MM"]
     #[inline(always)]
-    pub fn mm(&mut self) -> MM_W {
+    pub fn mm(&mut self) -> MM_W<'_> {
         MM_W { w: self }
     }
     #[doc = "Convenience function for setting the data length and frame format"]
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 97d22315a..99e40ba62 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -21,6 +21,7 @@ use self::fd::config::*;
 use self::fd::filter::*;
 pub use self::fd::{config, filter};
 pub use super::common::{BufferedCanReceiver, BufferedCanSender};
+use super::common::{InfoRef, RxInfoRef, TxInfoRef};
 use super::enums::*;
 use super::frame::*;
 use super::util;
@@ -167,10 +168,10 @@ fn calc_ns_per_timer_tick(
 pub struct CanConfigurator<'d> {
     _phantom: PhantomData<&'d ()>,
     config: crate::can::fd::config::FdCanConfig,
-    info: &'static Info,
     /// Reference to internals.
     properties: Properties,
     periph_clock: crate::time::Hertz,
+    info: InfoRef,
 }
 
 impl<'d> CanConfigurator<'d> {
@@ -194,8 +195,6 @@ impl<'d> CanConfigurator<'d> {
             s.borrow_mut().tx_pin_port = Some(tx.pin_port());
             s.borrow_mut().rx_pin_port = Some(rx.pin_port());
         });
-        (info.internal_operation)(InternalOperation::NotifySenderCreated);
-        (info.internal_operation)(InternalOperation::NotifyReceiverCreated);
 
         let mut config = crate::can::fd::config::FdCanConfig::default();
         config.timestamp_source = TimestampSource::Prescaler(TimestampPrescaler::_1);
@@ -211,9 +210,9 @@ impl<'d> CanConfigurator<'d> {
         Self {
             _phantom: PhantomData,
             config,
-            info,
             properties: Properties::new(T::info()),
             periph_clock: T::frequency(),
+            info: InfoRef::new(info),
         }
     }
 
@@ -262,19 +261,17 @@ impl<'d> CanConfigurator<'d> {
 
     /// Start in mode.
     pub fn start(self, mode: OperatingMode) -> Can<'d> {
-        let ns_per_timer_tick = calc_ns_per_timer_tick(self.info, self.periph_clock, self.config.frame_transmit);
+        let ns_per_timer_tick = calc_ns_per_timer_tick(&self.info, self.periph_clock, self.config.frame_transmit);
         self.info.state.lock(|s| {
             s.borrow_mut().ns_per_timer_tick = ns_per_timer_tick;
         });
         self.info.regs.into_mode(self.config, mode);
-        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         Can {
             _phantom: PhantomData,
             config: self.config,
-            info: self.info,
             _mode: mode,
-            properties: Properties::new(self.info),
+            properties: Properties::new(&self.info),
+            info: InfoRef::new(&self.info),
         }
     }
 
@@ -294,20 +291,13 @@ impl<'d> CanConfigurator<'d> {
     }
 }
 
-impl<'d> Drop for CanConfigurator<'d> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-    }
-}
-
 /// FDCAN Instance
 pub struct Can<'d> {
     _phantom: PhantomData<&'d ()>,
     config: crate::can::fd::config::FdCanConfig,
-    info: &'static Info,
     _mode: OperatingMode,
     properties: Properties,
+    info: InfoRef,
 }
 
 impl<'d> Can<'d> {
@@ -341,12 +331,12 @@ impl<'d> Can<'d> {
     /// can be replaced, this call asynchronously waits for a frame to be successfully
     /// transmitted, then tries again.
     pub async fn write(&mut self, frame: &Frame) -> Option<Frame> {
-        TxMode::write(self.info, frame).await
+        TxMode::write(&self.info, frame).await
     }
 
     /// Returns the next received message frame
     pub async fn read(&mut self) -> Result<Envelope, BusError> {
-        RxMode::read_classic(self.info).await
+        RxMode::read_classic(&self.info).await
     }
 
     /// Queues the message to be sent but exerts backpressure.  If a lower-priority
@@ -354,29 +344,27 @@ impl<'d> Can<'d> {
     /// can be replaced, this call asynchronously waits for a frame to be successfully
     /// transmitted, then tries again.
     pub async fn write_fd(&mut self, frame: &FdFrame) -> Option<FdFrame> {
-        TxMode::write_fd(self.info, frame).await
+        TxMode::write_fd(&self.info, frame).await
     }
 
     /// Returns the next received message frame
     pub async fn read_fd(&mut self) -> Result<FdEnvelope, BusError> {
-        RxMode::read_fd(self.info).await
+        RxMode::read_fd(&self.info).await
     }
 
     /// Split instance into separate portions: Tx(write), Rx(read), common properties
     pub fn split(self) -> (CanTx<'d>, CanRx<'d>, Properties) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         (
             CanTx {
                 _phantom: PhantomData,
-                info: self.info,
                 config: self.config,
                 _mode: self._mode,
+                info: TxInfoRef::new(&self.info),
             },
             CanRx {
                 _phantom: PhantomData,
-                info: self.info,
                 _mode: self._mode,
+                info: RxInfoRef::new(&self.info),
             },
             Properties {
                 info: self.properties.info,
@@ -385,14 +373,12 @@ impl<'d> Can<'d> {
     }
     /// Join split rx and tx portions back together
     pub fn join(tx: CanTx<'d>, rx: CanRx<'d>) -> Self {
-        (tx.info.internal_operation)(InternalOperation::NotifySenderCreated);
-        (tx.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         Can {
             _phantom: PhantomData,
             config: tx.config,
-            info: tx.info,
             _mode: rx._mode,
-            properties: Properties::new(tx.info),
+            properties: Properties::new(&tx.info),
+            info: InfoRef::new(&tx.info),
         }
     }
 
@@ -402,7 +388,7 @@ impl<'d> Can<'d> {
         tx_buf: &'static mut TxBuf<TX_BUF_SIZE>,
         rxb: &'static mut RxBuf<RX_BUF_SIZE>,
     ) -> BufferedCan<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
-        BufferedCan::new(self.info, self._mode, tx_buf, rxb)
+        BufferedCan::new(&self.info, self._mode, tx_buf, rxb)
     }
 
     /// Return a buffered instance of driver with CAN FD support. User must supply Buffers
@@ -411,14 +397,7 @@ impl<'d> Can<'d> {
         tx_buf: &'static mut TxFdBuf<TX_BUF_SIZE>,
         rxb: &'static mut RxFdBuf<RX_BUF_SIZE>,
     ) -> BufferedCanFd<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
-        BufferedCanFd::new(self.info, self._mode, tx_buf, rxb)
-    }
-}
-
-impl<'d> Drop for Can<'d> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
+        BufferedCanFd::new(&self.info, self._mode, tx_buf, rxb)
     }
 }
 
@@ -431,11 +410,11 @@ pub type TxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, Frame,
 /// Buffered FDCAN Instance
 pub struct BufferedCan<'d, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
     _phantom: PhantomData<&'d ()>,
-    info: &'static Info,
     _mode: OperatingMode,
     tx_buf: &'static TxBuf<TX_BUF_SIZE>,
     rx_buf: &'static RxBuf<RX_BUF_SIZE>,
     properties: Properties,
+    info: InfoRef,
 }
 
 impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
@@ -445,15 +424,13 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d,
         tx_buf: &'static TxBuf<TX_BUF_SIZE>,
         rx_buf: &'static RxBuf<RX_BUF_SIZE>,
     ) -> Self {
-        (info.internal_operation)(InternalOperation::NotifySenderCreated);
-        (info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         BufferedCan {
             _phantom: PhantomData,
-            info,
             _mode,
             tx_buf,
             rx_buf,
             properties: Properties::new(info),
+            info: InfoRef::new(info),
         }
         .setup()
     }
@@ -492,31 +469,21 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d,
 
     /// Returns a sender that can be used for sending CAN frames.
     pub fn writer(&self) -> BufferedCanSender {
-        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
         BufferedCanSender {
             tx_buf: self.tx_buf.sender().into(),
-            waker: self.info.tx_waker,
-            internal_operation: self.info.internal_operation,
+            info: TxInfoRef::new(&self.info),
         }
     }
 
     /// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
     pub fn reader(&self) -> BufferedCanReceiver {
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         BufferedCanReceiver {
             rx_buf: self.rx_buf.receiver().into(),
-            internal_operation: self.info.internal_operation,
+            info: RxInfoRef::new(&self.info),
         }
     }
 }
 
-impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop for BufferedCan<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-    }
-}
-
 /// User supplied buffer for RX Buffering
 pub type RxFdBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, Result<FdEnvelope, BusError>, BUF_SIZE>;
 
@@ -532,11 +499,11 @@ pub type BufferedFdCanReceiver = super::common::BufferedReceiver<'static, FdEnve
 /// Buffered FDCAN Instance
 pub struct BufferedCanFd<'d, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
     _phantom: PhantomData<&'d ()>,
-    info: &'static Info,
     _mode: OperatingMode,
     tx_buf: &'static TxFdBuf<TX_BUF_SIZE>,
     rx_buf: &'static RxFdBuf<RX_BUF_SIZE>,
     properties: Properties,
+    info: InfoRef,
 }
 
 impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCanFd<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
@@ -546,15 +513,13 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCanFd<'
         tx_buf: &'static TxFdBuf<TX_BUF_SIZE>,
         rx_buf: &'static RxFdBuf<RX_BUF_SIZE>,
     ) -> Self {
-        (info.internal_operation)(InternalOperation::NotifySenderCreated);
-        (info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         BufferedCanFd {
             _phantom: PhantomData,
-            info,
             _mode,
             tx_buf,
             rx_buf,
             properties: Properties::new(info),
+            info: InfoRef::new(info),
         }
         .setup()
     }
@@ -593,36 +558,26 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCanFd<'
 
     /// Returns a sender that can be used for sending CAN frames.
     pub fn writer(&self) -> BufferedFdCanSender {
-        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
         BufferedFdCanSender {
             tx_buf: self.tx_buf.sender().into(),
-            waker: self.info.tx_waker,
-            internal_operation: self.info.internal_operation,
+            info: TxInfoRef::new(&self.info),
         }
     }
 
     /// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
     pub fn reader(&self) -> BufferedFdCanReceiver {
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
         BufferedFdCanReceiver {
             rx_buf: self.rx_buf.receiver().into(),
-            internal_operation: self.info.internal_operation,
+            info: RxInfoRef::new(&self.info),
         }
     }
 }
 
-impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop for BufferedCanFd<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-    }
-}
-
 /// FDCAN Rx only Instance
 pub struct CanRx<'d> {
     _phantom: PhantomData<&'d ()>,
-    info: &'static Info,
     _mode: OperatingMode,
+    info: RxInfoRef,
 }
 
 impl<'d> CanRx<'d> {
@@ -637,18 +592,12 @@ impl<'d> CanRx<'d> {
     }
 }
 
-impl<'d> Drop for CanRx<'d> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-    }
-}
-
 /// FDCAN Tx only Instance
 pub struct CanTx<'d> {
     _phantom: PhantomData<&'d ()>,
-    info: &'static Info,
     config: crate::can::fd::config::FdCanConfig,
     _mode: OperatingMode,
+    info: TxInfoRef,
 }
 
 impl<'c, 'd> CanTx<'d> {
@@ -657,7 +606,7 @@ impl<'c, 'd> CanTx<'d> {
     /// can be replaced, this call asynchronously waits for a frame to be successfully
     /// transmitted, then tries again.
     pub async fn write(&mut self, frame: &Frame) -> Option<Frame> {
-        TxMode::write(self.info, frame).await
+        TxMode::write(&self.info, frame).await
     }
 
     /// Queues the message to be sent but exerts backpressure.  If a lower-priority
@@ -665,13 +614,7 @@ impl<'c, 'd> CanTx<'d> {
     /// can be replaced, this call asynchronously waits for a frame to be successfully
     /// transmitted, then tries again.
     pub async fn write_fd(&mut self, frame: &FdFrame) -> Option<FdFrame> {
-        TxMode::write_fd(self.info, frame).await
-    }
-}
-
-impl<'d> Drop for CanTx<'d> {
-    fn drop(&mut self) {
-        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
+        TxMode::write_fd(&self.info, frame).await
     }
 }
 
@@ -938,21 +881,56 @@ impl State {
 }
 
 type SharedState = embassy_sync::blocking_mutex::Mutex<CriticalSectionRawMutex, core::cell::RefCell<State>>;
-struct Info {
+pub(crate) struct Info {
     regs: Registers,
     interrupt0: crate::interrupt::Interrupt,
     _interrupt1: crate::interrupt::Interrupt,
-    tx_waker: fn(),
-    internal_operation: fn(InternalOperation),
+    pub(crate) tx_waker: fn(),
     state: SharedState,
 }
 
+impl Info {
+    pub(crate) fn adjust_reference_counter(&self, val: RefCountOp) {
+        self.state.lock(|s| {
+            let mut mut_state = s.borrow_mut();
+            match val {
+                RefCountOp::NotifySenderCreated => {
+                    mut_state.sender_instance_count += 1;
+                }
+                RefCountOp::NotifySenderDestroyed => {
+                    mut_state.sender_instance_count -= 1;
+                    if 0 == mut_state.sender_instance_count {
+                        (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+                    }
+                }
+                RefCountOp::NotifyReceiverCreated => {
+                    mut_state.receiver_instance_count += 1;
+                }
+                RefCountOp::NotifyReceiverDestroyed => {
+                    mut_state.receiver_instance_count -= 1;
+                    if 0 == mut_state.receiver_instance_count {
+                        (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+                    }
+                }
+            }
+            if mut_state.sender_instance_count == 0 && mut_state.receiver_instance_count == 0 {
+                unsafe {
+                    let tx_pin = crate::gpio::AnyPin::steal(mut_state.tx_pin_port.unwrap());
+                    tx_pin.set_as_disconnected();
+                    let rx_pin = crate::gpio::AnyPin::steal(mut_state.rx_pin_port.unwrap());
+                    rx_pin.set_as_disconnected();
+                    self.interrupt0.disable();
+                }
+            }
+        });
+    }
+}
+
 trait SealedInstance {
     const MSG_RAM_OFFSET: usize;
 
     fn info() -> &'static Info;
     fn registers() -> crate::can::fd::peripheral::Registers;
-    fn internal_operation(val: InternalOperation);
 }
 
 /// Instance trait
@@ -974,41 +952,6 @@ macro_rules! impl_fdcan {
         impl SealedInstance for peripherals::$inst {
             const MSG_RAM_OFFSET: usize = $msg_ram_offset;
 
-            fn internal_operation(val: InternalOperation) {
-                peripherals::$inst::info().state.lock(|s| {
-                    let mut mut_state = s.borrow_mut();
-                    match val {
-                        InternalOperation::NotifySenderCreated => {
-                            mut_state.sender_instance_count += 1;
-                        }
-                        InternalOperation::NotifySenderDestroyed => {
-                            mut_state.sender_instance_count -= 1;
-                            if ( 0 == mut_state.sender_instance_count) {
-                                (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-                            }
-                        }
-                        InternalOperation::NotifyReceiverCreated => {
-                            mut_state.receiver_instance_count += 1;
-                        }
-                        InternalOperation::NotifyReceiverDestroyed => {
-                            mut_state.receiver_instance_count -= 1;
-                            if ( 0 == mut_state.receiver_instance_count) {
-                                (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-                            }
-                        }
-                    }
-                    if mut_state.sender_instance_count == 0 && mut_state.receiver_instance_count == 0 {
-                        unsafe {
-                            let tx_pin = crate::gpio::AnyPin::steal(mut_state.tx_pin_port.unwrap());
-                            tx_pin.set_as_disconnected();
-                            let rx_pin = crate::gpio::AnyPin::steal(mut_state.rx_pin_port.unwrap());
-                            rx_pin.set_as_disconnected();
-                            rcc::disable::<peripherals::$inst>();
-                        }
-                    }
-                });
-            }
-
             fn info() -> &'static Info {
 
                 static INFO: Info = Info {
@@ -1016,7 +959,6 @@ macro_rules! impl_fdcan {
                     interrupt0: crate::_generated::peripheral_interrupts::$inst::IT0::IRQ,
                     _interrupt1: crate::_generated::peripheral_interrupts::$inst::IT1::IRQ,
                     tx_waker: crate::_generated::peripheral_interrupts::$inst::IT0::pend,
-                    internal_operation: peripherals::$inst::internal_operation,
                     state: embassy_sync::blocking_mutex::Mutex::new(core::cell::RefCell::new(State::new())),
                 };
                 &INFO
diff --git a/embassy-stm32/src/cordic/utils.rs b/embassy-stm32/src/cordic/utils.rs
index 008f50270..9afa8ef53 100644
--- a/embassy-stm32/src/cordic/utils.rs
+++ b/embassy-stm32/src/cordic/utils.rs
@@ -5,7 +5,7 @@ macro_rules! floating_fixed_convert {
     ($f_to_q:ident, $q_to_f:ident, $unsigned_bin_typ:ty, $signed_bin_typ:ty, $float_ty:ty, $offset:literal, $min_positive:literal) => {
         /// convert float point to fixed point format
         pub fn $f_to_q(value: $float_ty) -> Result<$unsigned_bin_typ, NumberOutOfRange> {
-            const MIN_POSITIVE: $float_ty = unsafe { core::mem::transmute($min_positive) };
+            const MIN_POSITIVE: $float_ty = <$float_ty>::from_bits($min_positive);
 
             if value < -1.0 {
                 return Err(NumberOutOfRange::BelowLowerBound)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index fba3c0fd7..35d9f8cce 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -2,7 +2,6 @@
 #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 use core::cmp::min;
 use core::marker::PhantomData;
-use core::ptr;
 
 use embassy_hal_internal::{Peri, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
@@ -1814,14 +1813,12 @@ impl<'d, T: Instance> Cryp<'d, T, Async> {
         assert_eq!(blocks.len() % block_size, 0);
         // Configure DMA to transfer input to crypto core.
         let dst_ptr: *mut u32 = T::regs().din().as_ptr();
-        let num_words = blocks.len() / 4;
-        let src_ptr: *const [u8] = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words);
         let options = TransferOptions {
             #[cfg(not(gpdma))]
             priority: crate::dma::Priority::High,
             ..Default::default()
         };
-        let dma_transfer = unsafe { dma.write_raw(src_ptr, dst_ptr, options) };
+        let dma_transfer = unsafe { dma.write_raw(blocks, dst_ptr, options) };
         T::regs().dmacr().modify(|w| w.set_dien(true));
         // Wait for the transfer to complete.
         dma_transfer.await;
@@ -1836,14 +1833,12 @@ impl<'d, T: Instance> Cryp<'d, T, Async> {
         assert_eq!((blocks.len() * 4) % block_size, 0);
         // Configure DMA to transfer input to crypto core.
         let dst_ptr: *mut u32 = T::regs().din().as_ptr();
-        let num_words = blocks.len();
-        let src_ptr: *const [u32] = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words);
         let options = TransferOptions {
             #[cfg(not(gpdma))]
             priority: crate::dma::Priority::High,
             ..Default::default()
         };
-        let dma_transfer = unsafe { dma.write_raw(src_ptr, dst_ptr, options) };
+        let dma_transfer = unsafe { dma.write_raw(blocks, dst_ptr, options) };
         T::regs().dmacr().modify(|w| w.set_dien(true));
         // Wait for the transfer to complete.
         dma_transfer.await;
@@ -1857,14 +1852,12 @@ impl<'d, T: Instance> Cryp<'d, T, Async> {
         assert_eq!(blocks.len() % block_size, 0);
         // Configure DMA to get output from crypto core.
         let src_ptr = T::regs().dout().as_ptr();
-        let num_words = blocks.len() / 4;
-        let dst_ptr = ptr::slice_from_raw_parts_mut(blocks.as_mut_ptr().cast(), num_words);
         let options = TransferOptions {
             #[cfg(not(gpdma))]
             priority: crate::dma::Priority::VeryHigh,
             ..Default::default()
         };
-        let dma_transfer = unsafe { dma.read_raw(src_ptr, dst_ptr, options) };
+        let dma_transfer = unsafe { dma.read_raw(src_ptr, blocks, options) };
         T::regs().dmacr().modify(|w| w.set_doen(true));
         // Wait for the transfer to complete.
         dma_transfer.await;
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 30046849b..d8f1f96f2 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -403,6 +403,46 @@ impl<'d, T: Instance> Dac<'d, T, Async> {
             Mode::NormalExternalBuffered,
         )
     }
+    /// Create a new `Dac` instance with external output pins and unbuffered mode.
+    ///
+    /// This function consumes the underlying DAC peripheral and allows access to both channels.
+    /// The channels are configured for external output with the buffer disabled.
+    ///
+    /// The channels are enabled on creation and begin to drive their output pins.
+    /// Note that some methods, such as `set_trigger()` and `set_mode()`, will
+    /// disable the channel; you must re-enable them with `enable()`.
+    ///
+    /// By default, triggering is disabled, but it can be enabled using the `set_trigger()`
+    /// method on the underlying channels.
+    ///
+    /// # Arguments
+    ///
+    /// * `peri` - The DAC peripheral instance.
+    /// * `dma_ch1` - The DMA channel for DAC channel 1.
+    /// * `dma_ch2` - The DMA channel for DAC channel 2.
+    /// * `pin_ch1` - The GPIO pin for DAC channel 1 output.
+    /// * `pin_ch2` - The GPIO pin for DAC channel 2 output.
+    ///
+    /// # Returns
+    ///
+    /// A new `Dac` instance in unbuffered mode.
+    pub fn new_unbuffered(
+        peri: Peri<'d, T>,
+        dma_ch1: Peri<'d, impl Dma<T, Ch1>>,
+        dma_ch2: Peri<'d, impl Dma<T, Ch2>>,
+        pin_ch1: Peri<'d, impl DacPin<T, Ch1> + crate::gpio::Pin>,
+        pin_ch2: Peri<'d, impl DacPin<T, Ch2> + crate::gpio::Pin>,
+    ) -> Self {
+        pin_ch1.set_as_analog();
+        pin_ch2.set_as_analog();
+        Self::new_inner(
+            peri,
+            new_dma!(dma_ch1),
+            new_dma!(dma_ch2),
+            #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
+            Mode::NormalExternalUnbuffered,
+        )
+    }
 
     /// Create a new `Dac` instance where the external output pins are not used,
     /// so the DAC can only be used to generate internal signals but the GPIO
diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs
index 7dbbe7b72..464823bfc 100644
--- a/embassy-stm32/src/dma/dma_bdma.rs
+++ b/embassy-stm32/src/dma/dma_bdma.rs
@@ -341,9 +341,12 @@ impl AnyChannel {
         mem_len: usize,
         incr_mem: bool,
         mem_size: WordSize,
-        peripheral_size: WordSize,
+        peri_size: WordSize,
         options: TransferOptions,
     ) {
+        // "Preceding reads and writes cannot be moved past subsequent writes."
+        fence(Ordering::SeqCst);
+
         let info = self.info();
         #[cfg(feature = "_dual-core")]
         {
@@ -354,28 +357,48 @@ impl AnyChannel {
         #[cfg(dmamux)]
         super::dmamux::configure_dmamux(&info.dmamux, _request);
 
-        assert!(mem_len > 0 && mem_len <= 0xFFFF);
-
         match self.info().dma {
             #[cfg(dma)]
             DmaInfo::Dma(r) => {
                 let state: &ChannelState = &STATE[self.id as usize];
                 let ch = r.st(info.num);
 
-                // "Preceding reads and writes cannot be moved past subsequent writes."
-                fence(Ordering::SeqCst);
-
                 state.complete_count.store(0, Ordering::Release);
                 self.clear_irqs();
 
+                // NDTR is the number of transfers in the *peripheral* word size.
+                // ex: if mem_size=1, peri_size=4 and ndtr=3 it'll do 12 mem transfers, 3 peri transfers.
+                let ndtr = match (mem_size, peri_size) {
+                    (WordSize::FourBytes, WordSize::OneByte) => mem_len * 4,
+                    (WordSize::FourBytes, WordSize::TwoBytes) | (WordSize::TwoBytes, WordSize::OneByte) => mem_len * 2,
+                    (WordSize::FourBytes, WordSize::FourBytes)
+                    | (WordSize::TwoBytes, WordSize::TwoBytes)
+                    | (WordSize::OneByte, WordSize::OneByte) => mem_len,
+                    (WordSize::TwoBytes, WordSize::FourBytes) | (WordSize::OneByte, WordSize::TwoBytes) => {
+                        assert!(mem_len % 2 == 0);
+                        mem_len / 2
+                    }
+                    (WordSize::OneByte, WordSize::FourBytes) => {
+                        assert!(mem_len % 4 == 0);
+                        mem_len / 4
+                    }
+                };
+
+                assert!(ndtr > 0 && ndtr <= 0xFFFF);
+
                 ch.par().write_value(peri_addr as u32);
                 ch.m0ar().write_value(mem_addr as u32);
-                ch.ndtr().write_value(pac::dma::regs::Ndtr(mem_len as _));
+                ch.ndtr().write_value(pac::dma::regs::Ndtr(ndtr as _));
                 ch.fcr().write(|w| {
                     if let Some(fth) = options.fifo_threshold {
                         // FIFO mode
                         w.set_dmdis(pac::dma::vals::Dmdis::DISABLED);
                         w.set_fth(fth.into());
+                    } else if mem_size != peri_size {
+                        // force FIFO mode if msize != psize
+                        // packing/unpacking doesn't work in direct mode.
+                        w.set_dmdis(pac::dma::vals::Dmdis::DISABLED);
+                        w.set_fth(FifoThreshold::Half.into());
                     } else {
                         // Direct mode
                         w.set_dmdis(pac::dma::vals::Dmdis::ENABLED);
@@ -384,7 +407,7 @@ impl AnyChannel {
                 ch.cr().write(|w| {
                     w.set_dir(dir.into());
                     w.set_msize(mem_size.into());
-                    w.set_psize(peripheral_size.into());
+                    w.set_psize(peri_size.into());
                     w.set_pl(options.priority.into());
                     w.set_minc(incr_mem);
                     w.set_pinc(false);
@@ -404,6 +427,8 @@ impl AnyChannel {
             }
             #[cfg(bdma)]
             DmaInfo::Bdma(r) => {
+                assert!(mem_len > 0 && mem_len <= 0xFFFF);
+
                 #[cfg(bdma_v2)]
                 critical_section::with(|_| r.cselr().modify(|w| w.set_cs(info.num, _request)));
 
@@ -417,7 +442,7 @@ impl AnyChannel {
                 ch.mar().write_value(mem_addr as u32);
                 ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
                 ch.cr().write(|w| {
-                    w.set_psize(peripheral_size.into());
+                    w.set_psize(peri_size.into());
                     w.set_msize(mem_size.into());
                     w.set_minc(incr_mem);
                     w.set_dir(dir.into());
@@ -587,11 +612,11 @@ impl<'a> Transfer<'a> {
     }
 
     /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
-    pub unsafe fn new_read_raw<W: Word>(
+    pub unsafe fn new_read_raw<MW: Word, PW: Word>(
         channel: Peri<'a, impl Channel>,
         request: Request,
-        peri_addr: *mut W,
-        buf: *mut [W],
+        peri_addr: *mut PW,
+        buf: *mut [MW],
         options: TransferOptions,
     ) -> Self {
         Self::new_inner(
@@ -599,11 +624,11 @@ impl<'a> Transfer<'a> {
             request,
             Dir::PeripheralToMemory,
             peri_addr as *const u32,
-            buf as *mut W as *mut u32,
+            buf as *mut MW as *mut u32,
             buf.len(),
             true,
-            W::size(),
-            W::size(),
+            MW::size(),
+            PW::size(),
             options,
         )
     }
@@ -672,22 +697,14 @@ impl<'a> Transfer<'a> {
         mem_addr: *mut u32,
         mem_len: usize,
         incr_mem: bool,
-        data_size: WordSize,
-        peripheral_size: WordSize,
+        mem_size: WordSize,
+        peri_size: WordSize,
         options: TransferOptions,
     ) -> Self {
         assert!(mem_len > 0 && mem_len <= 0xFFFF);
 
         channel.configure(
-            _request,
-            dir,
-            peri_addr,
-            mem_addr,
-            mem_len,
-            incr_mem,
-            data_size,
-            peripheral_size,
-            options,
+            _request, dir, peri_addr, mem_addr, mem_len, incr_mem, mem_size, peri_size, options,
         );
         channel.start();
         Self { channel }
diff --git a/embassy-stm32/src/dma/gpdma.rs b/embassy-stm32/src/dma/gpdma.rs
index ade70fb55..151e4ab9f 100644
--- a/embassy-stm32/src/dma/gpdma.rs
+++ b/embassy-stm32/src/dma/gpdma.rs
@@ -125,11 +125,11 @@ impl<'a> Transfer<'a> {
     }
 
     /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
-    pub unsafe fn new_read_raw<W: Word>(
+    pub unsafe fn new_read_raw<MW: Word, PW: Word>(
         channel: Peri<'a, impl Channel>,
         request: Request,
-        peri_addr: *mut W,
-        buf: *mut [W],
+        peri_addr: *mut PW,
+        buf: *mut [MW],
         options: TransferOptions,
     ) -> Self {
         Self::new_inner(
@@ -137,11 +137,11 @@ impl<'a> Transfer<'a> {
             request,
             Dir::PeripheralToMemory,
             peri_addr as *const u32,
-            buf as *mut W as *mut u32,
+            buf as *mut MW as *mut u32,
             buf.len(),
             true,
-            W::size(),
-            W::size(),
+            PW::size(),
+            MW::size(),
             options,
         )
     }
diff --git a/embassy-stm32/src/dma/util.rs b/embassy-stm32/src/dma/util.rs
index 8bf89e2fe..3245887c1 100644
--- a/embassy-stm32/src/dma/util.rs
+++ b/embassy-stm32/src/dma/util.rs
@@ -20,10 +20,10 @@ impl<'d> ChannelAndRequest<'d> {
         Transfer::new_read(self.channel.reborrow(), self.request, peri_addr, buf, options)
     }
 
-    pub unsafe fn read_raw<'a, W: Word>(
+    pub unsafe fn read_raw<'a, MW: Word, PW: Word>(
         &'a mut self,
-        peri_addr: *mut W,
-        buf: *mut [W],
+        peri_addr: *mut PW,
+        buf: *mut [MW],
         options: TransferOptions,
     ) -> Transfer<'a> {
         Transfer::new_read_raw(self.channel.reborrow(), self.request, peri_addr, buf, options)
diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs
index 01e321bce..b9746231f 100644
--- a/embassy-stm32/src/eth/v1/mod.rs
+++ b/embassy-stm32/src/eth/v1/mod.rs
@@ -122,7 +122,10 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
 
             // Select RMII (Reduced Media Independent Interface)
             // Must be done prior to enabling peripheral clock
-            AFIO.mapr().modify(|w| w.set_mii_rmii_sel(true));
+            AFIO.mapr().modify(|w| {
+                w.set_mii_rmii_sel(true);
+                w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
+            });
 
             RCC.ahbenr().modify(|w| {
                 w.set_ethen(true);
@@ -316,7 +319,10 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
 
             // Select MII (Media Independent Interface)
             // Must be done prior to enabling peripheral clock
-            AFIO.mapr().modify(|w| w.set_mii_rmii_sel(false));
+            AFIO.mapr().modify(|w| {
+                w.set_mii_rmii_sel(false);
+                w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
+            });
 
             RCC.ahbenr().modify(|w| {
                 w.set_ethen(true);
diff --git a/embassy-stm32/src/flash/u5.rs b/embassy-stm32/src/flash/u5.rs
index 131caa195..6c3d4b422 100644
--- a/embassy-stm32/src/flash/u5.rs
+++ b/embassy-stm32/src/flash/u5.rs
@@ -30,19 +30,19 @@ pub(crate) unsafe fn enable_blocking_write() {
 
     #[cfg(feature = "trustzone-secure")]
     pac::FLASH.seccr().write(|w| {
-        w.set_pg(pac::flash::vals::SeccrPg::B_0X1);
+        w.set_pg(true);
     });
     #[cfg(not(feature = "trustzone-secure"))]
     pac::FLASH.nscr().write(|w| {
-        w.set_pg(pac::flash::vals::NscrPg::B_0X1);
+        w.set_pg(true);
     });
 }
 
 pub(crate) unsafe fn disable_blocking_write() {
     #[cfg(feature = "trustzone-secure")]
-    pac::FLASH.seccr().write(|w| w.set_pg(pac::flash::vals::SeccrPg::B_0X0));
+    pac::FLASH.seccr().write(|w| w.set_pg(false));
     #[cfg(not(feature = "trustzone-secure"))]
-    pac::FLASH.nscr().write(|w| w.set_pg(pac::flash::vals::NscrPg::B_0X0));
+    pac::FLASH.nscr().write(|w| w.set_pg(false));
 }
 
 pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
@@ -65,19 +65,19 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
         w.set_pnb(sector.index_in_bank);
         // TODO: add check for bank swap
         w.set_bker(match sector.bank {
-            FlashBank::Bank1 => pac::flash::vals::SeccrBker::B_0X0,
-            FlashBank::Bank2 => pac::flash::vals::SeccrBker::B_0X1,
+            FlashBank::Bank1 => false,
+            FlashBank::Bank2 => true,
             _ => unreachable!(),
         });
     });
     #[cfg(not(feature = "trustzone-secure"))]
     pac::FLASH.nscr().modify(|w| {
-        w.set_per(pac::flash::vals::NscrPer::B_0X1);
+        w.set_per(true);
         w.set_pnb(sector.index_in_bank);
         // TODO: add check for bank swap
         w.set_bker(match sector.bank {
-            FlashBank::Bank1 => pac::flash::vals::NscrBker::B_0X0,
-            FlashBank::Bank2 => pac::flash::vals::NscrBker::B_0X1,
+            FlashBank::Bank1 => false,
+            FlashBank::Bank2 => true,
             _ => unreachable!(),
         });
     });
@@ -93,13 +93,9 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
 
     let ret: Result<(), Error> = blocking_wait_ready();
     #[cfg(feature = "trustzone-secure")]
-    pac::FLASH
-        .seccr()
-        .modify(|w| w.set_per(pac::flash::vals::SeccrPer::B_0X0));
+    pac::FLASH.seccr().modify(|w| w.set_per(false));
     #[cfg(not(feature = "trustzone-secure"))]
-    pac::FLASH
-        .nscr()
-        .modify(|w| w.set_per(pac::flash::vals::NscrPer::B_0X0));
+    pac::FLASH.nscr().modify(|w| w.set_per(false));
     clear_all_err();
     ret
 }
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs
index 31527bcdb..573a1851d 100644
--- a/embassy-stm32/src/hsem/mod.rs
+++ b/embassy-stm32/src/hsem/mod.rs
@@ -3,7 +3,7 @@
 use embassy_hal_internal::PeripheralType;
 
 use crate::pac;
-use crate::rcc::RccPeripheral;
+use crate::rcc::{self, RccPeripheral};
 // TODO: This code works for all HSEM implemenations except for the STM32WBA52/4/5xx MCUs.
 // Those MCUs have a different HSEM implementation (Secure semaphore lock support,
 // Privileged / unprivileged semaphore lock support, Semaphore lock protection via semaphore attribute),
@@ -46,7 +46,7 @@ pub enum CoreId {
 #[inline(always)]
 pub fn get_current_coreid() -> CoreId {
     let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() };
-    match cpuid & 0x000000F0 {
+    match (cpuid & 0x000000F0) >> 4 {
         #[cfg(any(stm32wb, stm32wl))]
         0x0 => CoreId::Core1,
 
@@ -80,6 +80,8 @@ pub struct HardwareSemaphore<'d, T: Instance> {
 impl<'d, T: Instance> HardwareSemaphore<'d, T> {
     /// Creates a new HardwareSemaphore instance.
     pub fn new(peripheral: Peri<'d, T>) -> Self {
+        rcc::enable_and_reset::<T>();
+
         HardwareSemaphore { _peri: peripheral }
     }
 
diff --git a/embassy-stm32/src/i2c/config.rs b/embassy-stm32/src/i2c/config.rs
new file mode 100644
index 000000000..daae43bcd
--- /dev/null
+++ b/embassy-stm32/src/i2c/config.rs
@@ -0,0 +1,170 @@
+#[cfg(gpio_v2)]
+use crate::gpio::Pull;
+use crate::gpio::{AfType, OutputType, Speed};
+
+#[repr(u8)]
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Bits of the I2C OA2 register to mask out.
+pub enum AddrMask {
+    /// No mask
+    NOMASK,
+    /// OA2\[1\] is masked and don’t care. Only OA2\[7:2\] are compared.
+    MASK1,
+    /// OA2\[2:1\] are masked and don’t care. Only OA2\[7:3\] are compared.
+    MASK2,
+    /// OA2\[3:1\] are masked and don’t care. Only OA2\[7:4\] are compared.
+    MASK3,
+    /// OA2\[4:1\] are masked and don’t care. Only OA2\[7:5\] are compared.
+    MASK4,
+    /// OA2\[5:1\] are masked and don’t care. Only OA2\[7:6\] are compared.
+    MASK5,
+    /// OA2\[6:1\] are masked and don’t care. Only OA2\[7:6\] are compared.
+    MASK6,
+    /// OA2\[7:1\] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
+    MASK7,
+}
+
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// An I2C address. Either 7 or 10 bit.
+pub enum Address {
+    /// A 7 bit address
+    SevenBit(u8),
+    /// A 10 bit address.
+    ///
+    /// When using an address to configure the Own Address, only the OA1 register can be set to a 10-bit address.
+    TenBit(u16),
+}
+impl From<u8> for Address {
+    fn from(value: u8) -> Self {
+        Address::SevenBit(value)
+    }
+}
+impl From<u16> for Address {
+    fn from(value: u16) -> Self {
+        assert!(value < 0x400, "Ten bit address must be less than 0x400");
+        Address::TenBit(value)
+    }
+}
+impl Address {
+    /// Get the inner address as a u16.
+    ///
+    /// For 7 bit addresses, the u8 that was used to store the address is returned as a u16.
+    pub fn addr(&self) -> u16 {
+        match self {
+            Address::SevenBit(addr) => *addr as u16,
+            Address::TenBit(addr) => *addr,
+        }
+    }
+}
+
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// The second Own Address register.
+pub struct OA2 {
+    /// The address.
+    pub addr: u8,
+    /// The bit mask that will affect how the own address 2 register is compared.
+    pub mask: AddrMask,
+}
+
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// The Own Address(es) of the I2C peripheral.
+pub enum OwnAddresses {
+    /// Configuration for only the OA1 register.
+    OA1(Address),
+    /// Configuration for only the OA2 register.
+    OA2(OA2),
+    /// Configuration for both the OA1 and OA2 registers.
+    Both {
+        /// The [Address] for the OA1 register.
+        oa1: Address,
+        /// The [OA2] configuration.
+        oa2: OA2,
+    },
+}
+
+/// Slave Configuration
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct SlaveAddrConfig {
+    /// Target Address(es)
+    pub addr: OwnAddresses,
+    /// Control if the peripheral should respond to the general call address
+    pub general_call: bool,
+}
+impl SlaveAddrConfig {
+    /// Create a new slave address configuration with only the OA1 register set in 7 bit mode and the general call disabled.
+    pub fn basic(addr: u8) -> Self {
+        Self {
+            addr: OwnAddresses::OA1(Address::SevenBit(addr)),
+            general_call: false,
+        }
+    }
+}
+
+/// I2C config
+#[non_exhaustive]
+#[derive(Copy, Clone)]
+pub struct Config {
+    /// Enable internal pullup on SDA.
+    ///
+    /// Using external pullup resistors is recommended for I2C. If you do
+    /// have external pullups you should not enable this.
+    #[cfg(gpio_v2)]
+    pub sda_pullup: bool,
+    /// Enable internal pullup on SCL.
+    ///
+    /// Using external pullup resistors is recommended for I2C. If you do
+    /// have external pullups you should not enable this.
+    #[cfg(gpio_v2)]
+    pub scl_pullup: bool,
+    /// Timeout.
+    #[cfg(feature = "time")]
+    pub timeout: embassy_time::Duration,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            #[cfg(gpio_v2)]
+            sda_pullup: false,
+            #[cfg(gpio_v2)]
+            scl_pullup: false,
+            #[cfg(feature = "time")]
+            timeout: embassy_time::Duration::from_millis(1000),
+        }
+    }
+}
+
+impl Config {
+    pub(super) fn scl_af(&self) -> AfType {
+        #[cfg(gpio_v1)]
+        return AfType::output(OutputType::OpenDrain, Speed::Medium);
+        #[cfg(gpio_v2)]
+        return AfType::output_pull(
+            OutputType::OpenDrain,
+            Speed::Medium,
+            match self.scl_pullup {
+                true => Pull::Up,
+                false => Pull::Down,
+            },
+        );
+    }
+
+    pub(super) fn sda_af(&self) -> AfType {
+        #[cfg(gpio_v1)]
+        return AfType::output(OutputType::OpenDrain, Speed::Medium);
+        #[cfg(gpio_v2)]
+        return AfType::output_pull(
+            OutputType::OpenDrain,
+            Speed::Medium,
+            match self.sda_pullup {
+                true => Pull::Up,
+                false => Pull::Down,
+            },
+        );
+    }
+}
diff --git a/embassy-stm32/src/i2c/mod.rs b/embassy-stm32/src/i2c/mod.rs
index 1689fdb84..825dd240c 100644
--- a/embassy-stm32/src/i2c/mod.rs
+++ b/embassy-stm32/src/i2c/mod.rs
@@ -5,19 +5,22 @@
 #[cfg_attr(any(i2c_v2, i2c_v3), path = "v2.rs")]
 mod _version;
 
+mod config;
+
 use core::future::Future;
 use core::iter;
 use core::marker::PhantomData;
 
+pub use config::*;
 use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
 #[cfg(feature = "time")]
 use embassy_time::{Duration, Instant};
+use mode::MasterMode;
+pub use mode::{Master, MultiMaster};
 
 use crate::dma::ChannelAndRequest;
-#[cfg(gpio_v2)]
-use crate::gpio::Pull;
-use crate::gpio::{AfType, AnyPin, OutputType, SealedPin as _, Speed};
+use crate::gpio::{AnyPin, SealedPin as _};
 use crate::interrupt::typelevel::Interrupt;
 use crate::mode::{Async, Blocking, Mode};
 use crate::rcc::{RccInfo, SealedRccPeripheral};
@@ -62,85 +65,89 @@ impl core::fmt::Display for Error {
 
 impl core::error::Error for Error {}
 
-/// I2C config
-#[non_exhaustive]
-#[derive(Copy, Clone)]
-pub struct Config {
-    /// Enable internal pullup on SDA.
-    ///
-    /// Using external pullup resistors is recommended for I2C. If you do
-    /// have external pullups you should not enable this.
-    #[cfg(gpio_v2)]
-    pub sda_pullup: bool,
-    /// Enable internal pullup on SCL.
-    ///
-    /// Using external pullup resistors is recommended for I2C. If you do
-    /// have external pullups you should not enable this.
-    #[cfg(gpio_v2)]
-    pub scl_pullup: bool,
-    /// Timeout.
-    #[cfg(feature = "time")]
-    pub timeout: embassy_time::Duration,
+/// I2C modes
+pub mod mode {
+    trait SealedMode {}
+
+    /// Trait for I2C master operations.
+    #[allow(private_bounds)]
+    pub trait MasterMode: SealedMode {}
+
+    /// Mode allowing for I2C master operations.
+    pub struct Master;
+    /// Mode allowing for I2C master and slave operations.
+    pub struct MultiMaster;
+
+    impl SealedMode for Master {}
+    impl MasterMode for Master {}
+
+    impl SealedMode for MultiMaster {}
+    impl MasterMode for MultiMaster {}
 }
 
-impl Default for Config {
-    fn default() -> Self {
-        Self {
-            #[cfg(gpio_v2)]
-            sda_pullup: false,
-            #[cfg(gpio_v2)]
-            scl_pullup: false,
-            #[cfg(feature = "time")]
-            timeout: embassy_time::Duration::from_millis(1000),
-        }
-    }
+#[derive(Debug, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// The command kind to the slave from the master
+pub enum SlaveCommandKind {
+    /// Write to the slave
+    Write,
+    /// Read from the slave
+    Read,
 }
 
-impl Config {
-    fn scl_af(&self) -> AfType {
-        #[cfg(gpio_v1)]
-        return AfType::output(OutputType::OpenDrain, Speed::Medium);
-        #[cfg(gpio_v2)]
-        return AfType::output_pull(
-            OutputType::OpenDrain,
-            Speed::Medium,
-            match self.scl_pullup {
-                true => Pull::Up,
-                false => Pull::None,
-            },
-        );
-    }
+#[derive(Debug, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// The command kind to the slave from the master and the address that the slave matched
+pub struct SlaveCommand {
+    /// The kind of command
+    pub kind: SlaveCommandKind,
+    /// The address that the slave matched
+    pub address: Address,
+}
 
-    fn sda_af(&self) -> AfType {
-        #[cfg(gpio_v1)]
-        return AfType::output(OutputType::OpenDrain, Speed::Medium);
-        #[cfg(gpio_v2)]
-        return AfType::output_pull(
-            OutputType::OpenDrain,
-            Speed::Medium,
-            match self.sda_pullup {
-                true => Pull::Up,
-                false => Pull::None,
-            },
-        );
+#[derive(Debug, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// The status of the slave send operation
+pub enum SendStatus {
+    /// The slave send operation is done, all bytes have been sent and the master is not requesting more
+    Done,
+    /// The slave send operation is done, but there are leftover bytes that the master did not read
+    LeftoverBytes(usize),
+}
+
+struct I2CDropGuard<'d> {
+    info: &'static Info,
+    scl: Option<Peri<'d, AnyPin>>,
+    sda: Option<Peri<'d, AnyPin>>,
+}
+impl<'d> Drop for I2CDropGuard<'d> {
+    fn drop(&mut self) {
+        if let Some(x) = self.scl.as_ref() {
+            x.set_as_disconnected()
+        }
+        if let Some(x) = self.sda.as_ref() {
+            x.set_as_disconnected()
+        }
+
+        self.info.rcc.disable();
     }
 }
 
 /// I2C driver.
-pub struct I2c<'d, M: Mode> {
+pub struct I2c<'d, M: Mode, IM: MasterMode> {
     info: &'static Info,
     state: &'static State,
     kernel_clock: Hertz,
-    scl: Option<Peri<'d, AnyPin>>,
-    sda: Option<Peri<'d, AnyPin>>,
     tx_dma: Option<ChannelAndRequest<'d>>,
     rx_dma: Option<ChannelAndRequest<'d>>,
     #[cfg(feature = "time")]
     timeout: Duration,
     _phantom: PhantomData<M>,
+    _phantom2: PhantomData<IM>,
+    _drop_guard: I2CDropGuard<'d>,
 }
 
-impl<'d> I2c<'d, Async> {
+impl<'d> I2c<'d, Async, Master> {
     /// Create a new I2C driver.
     pub fn new<T: Instance>(
         peri: Peri<'d, T>,
@@ -166,7 +173,7 @@ impl<'d> I2c<'d, Async> {
     }
 }
 
-impl<'d> I2c<'d, Blocking> {
+impl<'d> I2c<'d, Blocking, Master> {
     /// Create a new blocking I2C driver.
     pub fn new_blocking<T: Instance>(
         peri: Peri<'d, T>,
@@ -187,7 +194,7 @@ impl<'d> I2c<'d, Blocking> {
     }
 }
 
-impl<'d, M: Mode> I2c<'d, M> {
+impl<'d, M: Mode> I2c<'d, M, Master> {
     /// Create a new I2C driver.
     fn new_inner<T: Instance>(
         _peri: Peri<'d, T>,
@@ -205,15 +212,20 @@ impl<'d, M: Mode> I2c<'d, M> {
             info: T::info(),
             state: T::state(),
             kernel_clock: T::frequency(),
-            scl,
-            sda,
             tx_dma,
             rx_dma,
             #[cfg(feature = "time")]
             timeout: config.timeout,
             _phantom: PhantomData,
+            _phantom2: PhantomData,
+            _drop_guard: I2CDropGuard {
+                info: T::info(),
+                scl,
+                sda,
+            },
         };
         this.enable_and_init(freq, config);
+
         this
     }
 
@@ -221,7 +233,9 @@ impl<'d, M: Mode> I2c<'d, M> {
         self.info.rcc.enable_and_reset();
         self.init(freq, config);
     }
+}
 
+impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
     fn timeout(&self) -> Timeout {
         Timeout {
             #[cfg(feature = "time")]
@@ -230,15 +244,6 @@ impl<'d, M: Mode> I2c<'d, M> {
     }
 }
 
-impl<'d, M: Mode> Drop for I2c<'d, M> {
-    fn drop(&mut self) {
-        self.scl.as_ref().map(|x| x.set_as_disconnected());
-        self.sda.as_ref().map(|x| x.set_as_disconnected());
-
-        self.info.rcc.disable()
-    }
-}
-
 #[derive(Copy, Clone)]
 struct Timeout {
     #[cfg(feature = "time")]
@@ -347,7 +352,7 @@ foreach_peripheral!(
     };
 );
 
-impl<'d, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, M> {
+impl<'d, M: Mode, IM: MasterMode> embedded_hal_02::blocking::i2c::Read for I2c<'d, M, IM> {
     type Error = Error;
 
     fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
@@ -355,7 +360,7 @@ impl<'d, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, M> {
     }
 }
 
-impl<'d, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, M> {
+impl<'d, M: Mode, IM: MasterMode> embedded_hal_02::blocking::i2c::Write for I2c<'d, M, IM> {
     type Error = Error;
 
     fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
@@ -363,7 +368,7 @@ impl<'d, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, M> {
     }
 }
 
-impl<'d, M: Mode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, M> {
+impl<'d, M: Mode, IM: MasterMode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, M, IM> {
     type Error = Error;
 
     fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
@@ -387,11 +392,11 @@ impl embedded_hal_1::i2c::Error for Error {
     }
 }
 
-impl<'d, M: Mode> embedded_hal_1::i2c::ErrorType for I2c<'d, M> {
+impl<'d, M: Mode, IM: MasterMode> embedded_hal_1::i2c::ErrorType for I2c<'d, M, IM> {
     type Error = Error;
 }
 
-impl<'d, M: Mode> embedded_hal_1::i2c::I2c for I2c<'d, M> {
+impl<'d, M: Mode, IM: MasterMode> embedded_hal_1::i2c::I2c for I2c<'d, M, IM> {
     fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
         self.blocking_read(address, read)
     }
@@ -413,7 +418,7 @@ impl<'d, M: Mode> embedded_hal_1::i2c::I2c for I2c<'d, M> {
     }
 }
 
-impl<'d> embedded_hal_async::i2c::I2c for I2c<'d, Async> {
+impl<'d, IM: MasterMode> embedded_hal_async::i2c::I2c for I2c<'d, Async, IM> {
     async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
         self.read(address, read).await
     }
@@ -529,9 +534,7 @@ fn operation_frames<'a, 'b: 'a>(
     let mut next_first_frame = true;
 
     Ok(iter::from_fn(move || {
-        let Some(op) = operations.next() else {
-            return None;
-        };
+        let op = operations.next()?;
 
         // Is `op` first frame of its type?
         let first_frame = next_first_frame;
diff --git a/embassy-stm32/src/i2c/v1.rs b/embassy-stm32/src/i2c/v1.rs
index 28026f83c..35f13ab46 100644
--- a/embassy-stm32/src/i2c/v1.rs
+++ b/embassy-stm32/src/i2c/v1.rs
@@ -11,6 +11,7 @@ use embassy_embedded_hal::SetConfig;
 use embassy_futures::select::{select, Either};
 use embassy_hal_internal::drop::OnDrop;
 use embedded_hal_1::i2c::Operation;
+use mode::Master;
 
 use super::*;
 use crate::mode::Mode as PeriMode;
@@ -41,7 +42,7 @@ pub unsafe fn on_interrupt<T: Instance>() {
     });
 }
 
-impl<'d, M: PeriMode> I2c<'d, M> {
+impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
     pub(crate) fn init(&mut self, freq: Hertz, _config: Config) {
         self.info.regs.cr1().modify(|reg| {
             reg.set_pe(false);
@@ -354,7 +355,7 @@ impl<'d, M: PeriMode> I2c<'d, M> {
     }
 }
 
-impl<'d> I2c<'d, Async> {
+impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     async fn write_frame(&mut self, address: u8, write: &[u8], frame: FrameOptions) -> Result<(), Error> {
         self.info.regs.cr2().modify(|w| {
             // Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for
@@ -800,7 +801,7 @@ impl Timings {
     }
 }
 
-impl<'d, M: PeriMode> SetConfig for I2c<'d, M> {
+impl<'d, M: PeriMode> SetConfig for I2c<'d, M, Master> {
     type Config = Hertz;
     type ConfigError = ();
     fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 50a25754e..e24cce5c6 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -2,22 +2,87 @@ use core::cmp;
 use core::future::poll_fn;
 use core::task::Poll;
 
+use config::{Address, OwnAddresses, OA2};
 use embassy_embedded_hal::SetConfig;
 use embassy_hal_internal::drop::OnDrop;
 use embedded_hal_1::i2c::Operation;
+use mode::{Master, MultiMaster};
+use stm32_metapac::i2c::vals::{Addmode, Oamsk};
 
 use super::*;
 use crate::pac::i2c;
 
+impl From<AddrMask> for Oamsk {
+    fn from(value: AddrMask) -> Self {
+        match value {
+            AddrMask::NOMASK => Oamsk::NO_MASK,
+            AddrMask::MASK1 => Oamsk::MASK1,
+            AddrMask::MASK2 => Oamsk::MASK2,
+            AddrMask::MASK3 => Oamsk::MASK3,
+            AddrMask::MASK4 => Oamsk::MASK4,
+            AddrMask::MASK5 => Oamsk::MASK5,
+            AddrMask::MASK6 => Oamsk::MASK6,
+            AddrMask::MASK7 => Oamsk::MASK7,
+        }
+    }
+}
+
+impl Address {
+    pub(super) fn add_mode(&self) -> stm32_metapac::i2c::vals::Addmode {
+        match self {
+            Address::SevenBit(_) => stm32_metapac::i2c::vals::Addmode::BIT7,
+            Address::TenBit(_) => stm32_metapac::i2c::vals::Addmode::BIT10,
+        }
+    }
+}
+
+enum ReceiveResult {
+    DataAvailable,
+    StopReceived,
+    NewStart,
+}
+
+fn debug_print_interrupts(isr: stm32_metapac::i2c::regs::Isr) {
+    if isr.tcr() {
+        trace!("interrupt: tcr");
+    }
+    if isr.tc() {
+        trace!("interrupt: tc");
+    }
+    if isr.addr() {
+        trace!("interrupt: addr");
+    }
+    if isr.stopf() {
+        trace!("interrupt: stopf");
+    }
+    if isr.nackf() {
+        trace!("interrupt: nackf");
+    }
+    if isr.berr() {
+        trace!("interrupt: berr");
+    }
+    if isr.arlo() {
+        trace!("interrupt: arlo");
+    }
+    if isr.ovr() {
+        trace!("interrupt: ovr");
+    }
+}
+
 pub(crate) unsafe fn on_interrupt<T: Instance>() {
     let regs = T::info().regs;
     let isr = regs.isr().read();
 
-    if isr.tcr() || isr.tc() || isr.nackf() || isr.berr() || isr.arlo() || isr.ovr() {
+    if isr.tcr() || isr.tc() || isr.addr() || isr.stopf() || isr.nackf() || isr.berr() || isr.arlo() || isr.ovr() {
+        debug_print_interrupts(isr);
+
         T::state().waker.wake();
     }
+
     critical_section::with(|_| {
         regs.cr1().modify(|w| {
+            w.set_addrie(false);
+            w.set_stopie(false);
             // The flag can only be cleared by writting to nbytes, we won't do that here
             w.set_tcie(false);
             // Error flags are to be read in the routines, so we also don't clear them here
@@ -27,7 +92,7 @@ pub(crate) unsafe fn on_interrupt<T: Instance>() {
     });
 }
 
-impl<'d, M: Mode> I2c<'d, M> {
+impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
     pub(crate) fn init(&mut self, freq: Hertz, _config: Config) {
         self.info.regs.cr1().modify(|reg| {
             reg.set_pe(false);
@@ -55,7 +120,7 @@ impl<'d, M: Mode> I2c<'d, M> {
 
     fn master_read(
         info: &'static Info,
-        address: u8,
+        address: Address,
         length: usize,
         stop: Stop,
         reload: bool,
@@ -84,8 +149,8 @@ impl<'d, M: Mode> I2c<'d, M> {
         };
 
         info.regs.cr2().modify(|w| {
-            w.set_sadd((address << 1 | 0) as u16);
-            w.set_add10(i2c::vals::Addmode::BIT7);
+            w.set_sadd(address.addr() << 1);
+            w.set_add10(address.add_mode());
             w.set_dir(i2c::vals::Dir::READ);
             w.set_nbytes(length as u8);
             w.set_start(true);
@@ -98,7 +163,7 @@ impl<'d, M: Mode> I2c<'d, M> {
 
     fn master_write(
         info: &'static Info,
-        address: u8,
+        address: Address,
         length: usize,
         stop: Stop,
         reload: bool,
@@ -128,8 +193,8 @@ impl<'d, M: Mode> I2c<'d, M> {
         // START bit can be set even if the bus is BUSY or
         // I2C is in slave mode.
         info.regs.cr2().modify(|w| {
-            w.set_sadd((address << 1 | 0) as u16);
-            w.set_add10(i2c::vals::Addmode::BIT7);
+            w.set_sadd(address.addr() << 1);
+            w.set_add10(address.add_mode());
             w.set_dir(i2c::vals::Dir::WRITE);
             w.set_nbytes(length as u8);
             w.set_start(true);
@@ -140,14 +205,14 @@ impl<'d, M: Mode> I2c<'d, M> {
         Ok(())
     }
 
-    fn master_continue(info: &'static Info, length: usize, reload: bool, timeout: Timeout) -> Result<(), Error> {
+    fn reload(info: &'static Info, length: usize, will_reload: bool, timeout: Timeout) -> Result<(), Error> {
         assert!(length < 256 && length > 0);
 
         while !info.regs.isr().read().tcr() {
             timeout.check()?;
         }
 
-        let reload = if reload {
+        let will_reload = if will_reload {
             i2c::vals::Reload::NOT_COMPLETED
         } else {
             i2c::vals::Reload::COMPLETED
@@ -155,7 +220,7 @@ impl<'d, M: Mode> I2c<'d, M> {
 
         info.regs.cr2().modify(|w| {
             w.set_nbytes(length as u8);
-            w.set_reload(reload);
+            w.set_reload(will_reload);
         });
 
         Ok(())
@@ -163,49 +228,132 @@ impl<'d, M: Mode> I2c<'d, M> {
 
     fn flush_txdr(&self) {
         if self.info.regs.isr().read().txis() {
-            self.info.regs.txdr().write(|w| w.set_txdata(0));
+            trace!("Flush TXDATA with zeroes");
+            self.info.regs.txdr().modify(|w| w.set_txdata(0));
         }
         if !self.info.regs.isr().read().txe() {
+            trace!("Flush TXDR");
             self.info.regs.isr().modify(|w| w.set_txe(true))
         }
     }
 
-    fn wait_txe(&self, timeout: Timeout) -> Result<(), Error> {
+    fn error_occurred(&self, isr: &i2c::regs::Isr, timeout: Timeout) -> Result<(), Error> {
+        if isr.nackf() {
+            trace!("NACK triggered.");
+            self.info.regs.icr().modify(|reg| reg.set_nackcf(true));
+            // NACK should be followed by STOP
+            if let Ok(()) = self.wait_stop(timeout) {
+                trace!("Got STOP after NACK, clearing flag.");
+                self.info.regs.icr().modify(|reg| reg.set_stopcf(true));
+            }
+            self.flush_txdr();
+            return Err(Error::Nack);
+        } else if isr.berr() {
+            trace!("BERR triggered.");
+            self.info.regs.icr().modify(|reg| reg.set_berrcf(true));
+            self.flush_txdr();
+            return Err(Error::Bus);
+        } else if isr.arlo() {
+            trace!("ARLO triggered.");
+            self.info.regs.icr().modify(|reg| reg.set_arlocf(true));
+            self.flush_txdr();
+            return Err(Error::Arbitration);
+        } else if isr.ovr() {
+            trace!("OVR triggered.");
+            self.info.regs.icr().modify(|reg| reg.set_ovrcf(true));
+            return Err(Error::Overrun);
+        }
+        return Ok(());
+    }
+
+    fn wait_txis(&self, timeout: Timeout) -> Result<(), Error> {
+        let mut first_loop = true;
+
         loop {
             let isr = self.info.regs.isr().read();
-            if isr.txe() {
+            self.error_occurred(&isr, timeout)?;
+            if isr.txis() {
+                trace!("TXIS");
                 return Ok(());
-            } else if isr.berr() {
-                self.info.regs.icr().write(|reg| reg.set_berrcf(true));
-                return Err(Error::Bus);
-            } else if isr.arlo() {
-                self.info.regs.icr().write(|reg| reg.set_arlocf(true));
-                return Err(Error::Arbitration);
-            } else if isr.nackf() {
-                self.info.regs.icr().write(|reg| reg.set_nackcf(true));
-                self.flush_txdr();
-                return Err(Error::Nack);
             }
 
+            {
+                if first_loop {
+                    trace!("Waiting for TXIS...");
+                    first_loop = false;
+                }
+            }
+            timeout.check()?;
+        }
+    }
+
+    fn wait_stop_or_err(&self, timeout: Timeout) -> Result<(), Error> {
+        loop {
+            let isr = self.info.regs.isr().read();
+            self.error_occurred(&isr, timeout)?;
+            if isr.stopf() {
+                trace!("STOP triggered.");
+                self.info.regs.icr().modify(|reg| reg.set_stopcf(true));
+                return Ok(());
+            }
+            timeout.check()?;
+        }
+    }
+    fn wait_stop(&self, timeout: Timeout) -> Result<(), Error> {
+        loop {
+            let isr = self.info.regs.isr().read();
+            if isr.stopf() {
+                trace!("STOP triggered.");
+                self.info.regs.icr().modify(|reg| reg.set_stopcf(true));
+                return Ok(());
+            }
             timeout.check()?;
         }
     }
 
-    fn wait_rxne(&self, timeout: Timeout) -> Result<(), Error> {
+    fn wait_af(&self, timeout: Timeout) -> Result<(), Error> {
         loop {
             let isr = self.info.regs.isr().read();
-            if isr.rxne() {
+            if isr.nackf() {
+                trace!("AF triggered.");
+                self.info.regs.icr().modify(|reg| reg.set_nackcf(true));
                 return Ok(());
-            } else if isr.berr() {
-                self.info.regs.icr().write(|reg| reg.set_berrcf(true));
-                return Err(Error::Bus);
-            } else if isr.arlo() {
-                self.info.regs.icr().write(|reg| reg.set_arlocf(true));
-                return Err(Error::Arbitration);
-            } else if isr.nackf() {
-                self.info.regs.icr().write(|reg| reg.set_nackcf(true));
-                self.flush_txdr();
-                return Err(Error::Nack);
+            }
+            timeout.check()?;
+        }
+    }
+
+    fn wait_rxne(&self, timeout: Timeout) -> Result<ReceiveResult, Error> {
+        let mut first_loop = true;
+
+        loop {
+            let isr = self.info.regs.isr().read();
+            self.error_occurred(&isr, timeout)?;
+            if isr.stopf() {
+                trace!("STOP when waiting for RXNE.");
+                if self.info.regs.isr().read().rxne() {
+                    trace!("Data received with STOP.");
+                    return Ok(ReceiveResult::DataAvailable);
+                }
+                trace!("STOP triggered without data.");
+                return Ok(ReceiveResult::StopReceived);
+            } else if isr.rxne() {
+                trace!("RXNE.");
+                return Ok(ReceiveResult::DataAvailable);
+            } else if isr.addr() {
+                // Another addr event received, which means START was sent again
+                // which happens when accessing memory registers (common i2c interface design)
+                // e.g. master sends: START, write 1 byte (register index), START, read N bytes (until NACK)
+                // Possible to receive this flag at the same time as rxne, so check rxne first
+                trace!("START when waiting for RXNE. Ending receive loop.");
+                // Return without clearing ADDR so `listen` can catch it
+                return Ok(ReceiveResult::NewStart);
+            }
+            {
+                if first_loop {
+                    trace!("Waiting for RXNE...");
+                    first_loop = false;
+                }
             }
 
             timeout.check()?;
@@ -215,25 +363,21 @@ impl<'d, M: Mode> I2c<'d, M> {
     fn wait_tc(&self, timeout: Timeout) -> Result<(), Error> {
         loop {
             let isr = self.info.regs.isr().read();
+            self.error_occurred(&isr, timeout)?;
             if isr.tc() {
                 return Ok(());
-            } else if isr.berr() {
-                self.info.regs.icr().write(|reg| reg.set_berrcf(true));
-                return Err(Error::Bus);
-            } else if isr.arlo() {
-                self.info.regs.icr().write(|reg| reg.set_arlocf(true));
-                return Err(Error::Arbitration);
-            } else if isr.nackf() {
-                self.info.regs.icr().write(|reg| reg.set_nackcf(true));
-                self.flush_txdr();
-                return Err(Error::Nack);
             }
-
             timeout.check()?;
         }
     }
 
-    fn read_internal(&mut self, address: u8, read: &mut [u8], restart: bool, timeout: Timeout) -> Result<(), Error> {
+    fn read_internal(
+        &mut self,
+        address: Address,
+        read: &mut [u8],
+        restart: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
         let completed_chunks = read.len() / 255;
         let total_chunks = if completed_chunks * 255 == read.len() {
             completed_chunks
@@ -254,7 +398,7 @@ impl<'d, M: Mode> I2c<'d, M> {
 
         for (number, chunk) in read.chunks_mut(255).enumerate() {
             if number != 0 {
-                Self::master_continue(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
             }
 
             for byte in chunk {
@@ -267,7 +411,13 @@ impl<'d, M: Mode> I2c<'d, M> {
         Ok(())
     }
 
-    fn write_internal(&mut self, address: u8, write: &[u8], send_stop: bool, timeout: Timeout) -> Result<(), Error> {
+    fn write_internal(
+        &mut self,
+        address: Address,
+        write: &[u8],
+        send_stop: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
         let completed_chunks = write.len() / 255;
         let total_chunks = if completed_chunks * 255 == write.len() {
             completed_chunks
@@ -295,14 +445,14 @@ impl<'d, M: Mode> I2c<'d, M> {
 
         for (number, chunk) in write.chunks(255).enumerate() {
             if number != 0 {
-                Self::master_continue(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
             }
 
             for byte in chunk {
                 // Wait until we are allowed to send data
                 // (START has been ACKed or last byte when
                 // through)
-                if let Err(err) = self.wait_txe(timeout) {
+                if let Err(err) = self.wait_txis(timeout) {
                     if send_stop {
                         self.master_stop();
                     }
@@ -325,20 +475,20 @@ impl<'d, M: Mode> I2c<'d, M> {
 
     /// Blocking read.
     pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Error> {
-        self.read_internal(address, read, false, self.timeout())
+        self.read_internal(address.into(), read, false, self.timeout())
         // Automatic Stop
     }
 
     /// Blocking write.
     pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
-        self.write_internal(address, write, true, self.timeout())
+        self.write_internal(address.into(), write, true, self.timeout())
     }
 
     /// Blocking write, restart, read.
     pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
         let timeout = self.timeout();
-        self.write_internal(address, write, false, timeout)?;
-        self.read_internal(address, read, true, timeout)
+        self.write_internal(address.into(), write, false, timeout)?;
+        self.read_internal(address.into(), read, true, timeout)
         // Automatic Stop
     }
 
@@ -368,7 +518,7 @@ impl<'d, M: Mode> I2c<'d, M> {
 
         if let Err(err) = Self::master_write(
             self.info,
-            address,
+            address.into(),
             first_length.min(255),
             Stop::Software,
             (first_length > 255) || (last_slice_index != 0),
@@ -389,7 +539,7 @@ impl<'d, M: Mode> I2c<'d, M> {
             let last_chunk_idx = total_chunks.saturating_sub(1);
 
             if idx != 0 {
-                if let Err(err) = Self::master_continue(
+                if let Err(err) = Self::reload(
                     self.info,
                     slice_len.min(255),
                     (idx != last_slice_index) || (slice_len > 255),
@@ -402,7 +552,7 @@ impl<'d, M: Mode> I2c<'d, M> {
 
             for (number, chunk) in slice.chunks(255).enumerate() {
                 if number != 0 {
-                    if let Err(err) = Self::master_continue(
+                    if let Err(err) = Self::reload(
                         self.info,
                         chunk.len(),
                         (number != last_chunk_idx) || (idx != last_slice_index),
@@ -417,7 +567,7 @@ impl<'d, M: Mode> I2c<'d, M> {
                     // Wait until we are allowed to send data
                     // (START has been ACKed or last byte when
                     // through)
-                    if let Err(err) = self.wait_txe(timeout) {
+                    if let Err(err) = self.wait_txis(timeout) {
                         self.master_stop();
                         return Err(err);
                     }
@@ -435,10 +585,10 @@ impl<'d, M: Mode> I2c<'d, M> {
     }
 }
 
-impl<'d> I2c<'d, Async> {
+impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     async fn write_dma_internal(
         &mut self,
-        address: u8,
+        address: Address,
         write: &[u8],
         first_slice: bool,
         last_slice: bool,
@@ -512,7 +662,7 @@ impl<'d> I2c<'d, Async> {
                         timeout,
                     )?;
                 } else {
-                    Self::master_continue(self.info, total_len.min(255), (total_len > 255) || !last_slice, timeout)?;
+                    Self::reload(self.info, total_len.min(255), (total_len > 255) || !last_slice, timeout)?;
                     self.info.regs.cr1().modify(|w| w.set_tcie(true));
                 }
             } else if !(isr.tcr() || isr.tc()) {
@@ -523,7 +673,7 @@ impl<'d> I2c<'d, Async> {
             } else {
                 let last_piece = (remaining_len <= 255) && last_slice;
 
-                if let Err(e) = Self::master_continue(self.info, remaining_len.min(255), !last_piece, timeout) {
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, timeout) {
                     return Poll::Ready(Err(e));
                 }
                 self.info.regs.cr1().modify(|w| w.set_tcie(true));
@@ -551,7 +701,7 @@ impl<'d> I2c<'d, Async> {
 
     async fn read_dma_internal(
         &mut self,
-        address: u8,
+        address: Address,
         buffer: &mut [u8],
         restart: bool,
         timeout: Timeout,
@@ -626,7 +776,7 @@ impl<'d> I2c<'d, Async> {
             } else {
                 let last_piece = remaining_len <= 255;
 
-                if let Err(e) = Self::master_continue(self.info, remaining_len.min(255), !last_piece, timeout) {
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, timeout) {
                     return Poll::Ready(Err(e));
                 }
                 // Return here if we are on last chunk,
@@ -647,7 +797,6 @@ impl<'d> I2c<'d, Async> {
 
         Ok(())
     }
-
     // =========================
     //  Async public API
 
@@ -655,10 +804,10 @@ impl<'d> I2c<'d, Async> {
     pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
         let timeout = self.timeout();
         if write.is_empty() {
-            self.write_internal(address, write, true, timeout)
+            self.write_internal(address.into(), write, true, timeout)
         } else {
             timeout
-                .with(self.write_dma_internal(address, write, true, true, true, timeout))
+                .with(self.write_dma_internal(address.into(), write, true, true, true, timeout))
                 .await
         }
     }
@@ -666,7 +815,7 @@ impl<'d> I2c<'d, Async> {
     /// Write multiple buffers.
     ///
     /// The buffers are concatenated in a single write transaction.
-    pub async fn write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error> {
+    pub async fn write_vectored(&mut self, address: Address, write: &[&[u8]]) -> Result<(), Error> {
         let timeout = self.timeout();
 
         if write.is_empty() {
@@ -693,9 +842,9 @@ impl<'d> I2c<'d, Async> {
         let timeout = self.timeout();
 
         if buffer.is_empty() {
-            self.read_internal(address, buffer, false, timeout)
+            self.read_internal(address.into(), buffer, false, timeout)
         } else {
-            let fut = self.read_dma_internal(address, buffer, false, timeout);
+            let fut = self.read_dma_internal(address.into(), buffer, false, timeout);
             timeout.with(fut).await
         }
     }
@@ -705,16 +854,16 @@ impl<'d> I2c<'d, Async> {
         let timeout = self.timeout();
 
         if write.is_empty() {
-            self.write_internal(address, write, false, timeout)?;
+            self.write_internal(address.into(), write, false, timeout)?;
         } else {
-            let fut = self.write_dma_internal(address, write, true, true, false, timeout);
+            let fut = self.write_dma_internal(address.into(), write, true, true, false, timeout);
             timeout.with(fut).await?;
         }
 
         if read.is_empty() {
-            self.read_internal(address, read, true, timeout)?;
+            self.read_internal(address.into(), read, true, timeout)?;
         } else {
-            let fut = self.read_dma_internal(address, read, true, timeout);
+            let fut = self.read_dma_internal(address.into(), read, true, timeout);
             timeout.with(fut).await?;
         }
 
@@ -733,6 +882,414 @@ impl<'d> I2c<'d, Async> {
     }
 }
 
+impl<'d, M: Mode> I2c<'d, M, Master> {
+    /// Configure the I2C driver for slave operations, allowing for the driver to be used as a slave and a master (multimaster)
+    pub fn into_slave_multimaster(mut self, slave_addr_config: SlaveAddrConfig) -> I2c<'d, M, MultiMaster> {
+        let mut slave = I2c {
+            info: self.info,
+            state: self.state,
+            kernel_clock: self.kernel_clock,
+            tx_dma: self.tx_dma.take(),
+            rx_dma: self.rx_dma.take(),
+            #[cfg(feature = "time")]
+            timeout: self.timeout,
+            _phantom: PhantomData,
+            _phantom2: PhantomData,
+            _drop_guard: self._drop_guard,
+        };
+        slave.init_slave(slave_addr_config);
+        slave
+    }
+}
+
+impl<'d, M: Mode> I2c<'d, M, MultiMaster> {
+    pub(crate) fn init_slave(&mut self, config: SlaveAddrConfig) {
+        self.info.regs.cr1().modify(|reg| {
+            reg.set_pe(false);
+        });
+
+        self.info.regs.cr1().modify(|reg| {
+            reg.set_nostretch(false);
+            reg.set_gcen(config.general_call);
+            reg.set_sbc(true);
+            reg.set_pe(true);
+        });
+
+        self.reconfigure_addresses(config.addr);
+    }
+
+    /// Configure the slave address.
+    pub fn reconfigure_addresses(&mut self, addresses: OwnAddresses) {
+        match addresses {
+            OwnAddresses::OA1(oa1) => self.configure_oa1(oa1),
+            OwnAddresses::OA2(oa2) => self.configure_oa2(oa2),
+            OwnAddresses::Both { oa1, oa2 } => {
+                self.configure_oa1(oa1);
+                self.configure_oa2(oa2);
+            }
+        }
+    }
+
+    fn configure_oa1(&mut self, oa1: Address) {
+        match oa1 {
+            Address::SevenBit(addr) => self.info.regs.oar1().write(|reg| {
+                reg.set_oa1en(false);
+                reg.set_oa1((addr << 1) as u16);
+                reg.set_oa1mode(Addmode::BIT7);
+                reg.set_oa1en(true);
+            }),
+            Address::TenBit(addr) => self.info.regs.oar1().write(|reg| {
+                reg.set_oa1en(false);
+                reg.set_oa1(addr);
+                reg.set_oa1mode(Addmode::BIT10);
+                reg.set_oa1en(true);
+            }),
+        }
+    }
+
+    fn configure_oa2(&mut self, oa2: OA2) {
+        self.info.regs.oar2().write(|reg| {
+            reg.set_oa2en(false);
+            reg.set_oa2msk(oa2.mask.into());
+            reg.set_oa2(oa2.addr << 1);
+            reg.set_oa2en(true);
+        });
+    }
+
+    fn determine_matched_address(&self) -> Result<Address, Error> {
+        let matched = self.info.regs.isr().read().addcode();
+
+        if matched >> 3 == 0b11110 {
+            // is 10-bit address and we need to get the other 8 bits from the rxdr
+            // we do this by doing a blocking read of 1 byte
+            let mut buffer = [0];
+            self.slave_read_internal(&mut buffer, self.timeout())?;
+            Ok(Address::TenBit((matched as u16) << 6 | buffer[0] as u16))
+        } else {
+            Ok(Address::SevenBit(matched))
+        }
+    }
+}
+
+impl<'d, M: Mode> I2c<'d, M, MultiMaster> {
+    /// # Safety
+    /// This function will clear the address flag which will stop the clock stretching.
+    /// This should only be done after the dma transfer has been set up.
+    fn slave_start(info: &'static Info, length: usize, reload: bool) {
+        assert!(length < 256);
+
+        let reload = if reload {
+            i2c::vals::Reload::NOT_COMPLETED
+        } else {
+            i2c::vals::Reload::COMPLETED
+        };
+
+        info.regs.cr2().modify(|w| {
+            w.set_nbytes(length as u8);
+            w.set_reload(reload);
+        });
+
+        // clear the address flag, will stop the clock stretching.
+        // this should only be done after the dma transfer has been set up.
+        info.regs.icr().modify(|reg| reg.set_addrcf(true));
+        trace!("ADDRCF cleared (ADDR interrupt enabled, clock stretching ended)");
+    }
+
+    // A blocking read operation
+    fn slave_read_internal(&self, read: &mut [u8], timeout: Timeout) -> Result<usize, Error> {
+        let completed_chunks = read.len() / 255;
+        let total_chunks = if completed_chunks * 255 == read.len() {
+            completed_chunks
+        } else {
+            completed_chunks + 1
+        };
+        let last_chunk_idx = total_chunks.saturating_sub(1);
+        let total_len = read.len();
+        let mut remaining_len = total_len;
+
+        for (number, chunk) in read.chunks_mut(255).enumerate() {
+            trace!(
+                "--- Slave RX transmission start - chunk: {}, expected (max) size: {}",
+                number,
+                chunk.len()
+            );
+            if number == 0 {
+                Self::slave_start(self.info, chunk.len(), number != last_chunk_idx);
+            } else {
+                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+            }
+
+            let mut index = 0;
+
+            for byte in chunk {
+                // Wait until we have received something
+                match self.wait_rxne(timeout) {
+                    Ok(ReceiveResult::StopReceived) | Ok(ReceiveResult::NewStart) => {
+                        trace!("--- Slave RX transmission end (early)");
+                        return Ok(total_len - remaining_len); // Return N bytes read
+                    }
+                    Ok(ReceiveResult::DataAvailable) => {
+                        *byte = self.info.regs.rxdr().read().rxdata();
+                        remaining_len = remaining_len.saturating_sub(1);
+                        {
+                            trace!("Slave RX data {}: {:#04x}", index, byte);
+                            index = index + 1;
+                        }
+                    }
+                    Err(e) => return Err(e),
+                };
+            }
+        }
+        self.wait_stop_or_err(timeout)?;
+
+        trace!("--- Slave RX transmission end");
+        Ok(total_len - remaining_len) // Return N bytes read
+    }
+
+    // A blocking write operation
+    fn slave_write_internal(&mut self, write: &[u8], timeout: Timeout) -> Result<(), Error> {
+        let completed_chunks = write.len() / 255;
+        let total_chunks = if completed_chunks * 255 == write.len() {
+            completed_chunks
+        } else {
+            completed_chunks + 1
+        };
+        let last_chunk_idx = total_chunks.saturating_sub(1);
+
+        for (number, chunk) in write.chunks(255).enumerate() {
+            trace!(
+                "--- Slave TX transmission start - chunk: {}, size: {}",
+                number,
+                chunk.len()
+            );
+            if number == 0 {
+                Self::slave_start(self.info, chunk.len(), number != last_chunk_idx);
+            } else {
+                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+            }
+
+            let mut index = 0;
+
+            for byte in chunk {
+                // Wait until we are allowed to send data
+                // (START has been ACKed or last byte when through)
+                self.wait_txis(timeout)?;
+
+                {
+                    trace!("Slave TX data {}: {:#04x}", index, byte);
+                    index = index + 1;
+                }
+                self.info.regs.txdr().write(|w| w.set_txdata(*byte));
+            }
+        }
+        self.wait_af(timeout)?;
+        self.flush_txdr();
+        self.wait_stop_or_err(timeout)?;
+
+        trace!("--- Slave TX transmission end");
+        Ok(())
+    }
+
+    /// Listen for incoming I2C messages.
+    ///
+    /// The listen method is an asynchronous method but it does not require DMA to be asynchronous.
+    pub async fn listen(&mut self) -> Result<SlaveCommand, Error> {
+        let state = self.state;
+        self.info.regs.cr1().modify(|reg| {
+            reg.set_addrie(true);
+            trace!("Enable ADDRIE");
+        });
+
+        poll_fn(|cx| {
+            state.waker.register(cx.waker());
+            let isr = self.info.regs.isr().read();
+            if !isr.addr() {
+                Poll::Pending
+            } else {
+                trace!("ADDR triggered (address match)");
+                // we do not clear the address flag here as it will be cleared by the dma read/write
+                // if we clear it here the clock stretching will stop and the master will read in data before the slave is ready to send it
+                match isr.dir() {
+                    i2c::vals::Dir::WRITE => {
+                        trace!("DIR: write");
+                        Poll::Ready(Ok(SlaveCommand {
+                            kind: SlaveCommandKind::Write,
+                            address: self.determine_matched_address()?,
+                        }))
+                    }
+                    i2c::vals::Dir::READ => {
+                        trace!("DIR: read");
+                        Poll::Ready(Ok(SlaveCommand {
+                            kind: SlaveCommandKind::Read,
+                            address: self.determine_matched_address()?,
+                        }))
+                    }
+                }
+            }
+        })
+        .await
+    }
+
+    /// Respond to a write command.
+    ///
+    /// Returns total number of bytes received.
+    pub fn blocking_respond_to_write(&self, read: &mut [u8]) -> Result<usize, Error> {
+        let timeout = self.timeout();
+        self.slave_read_internal(read, timeout)
+    }
+
+    /// Respond to a read command.
+    pub fn blocking_respond_to_read(&mut self, write: &[u8]) -> Result<(), Error> {
+        let timeout = self.timeout();
+        self.slave_write_internal(write, timeout)
+    }
+}
+
+impl<'d> I2c<'d, Async, MultiMaster> {
+    /// Respond to a write command.
+    ///
+    /// Returns the total number of bytes received.
+    pub async fn respond_to_write(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
+        let timeout = self.timeout();
+        timeout.with(self.read_dma_internal_slave(buffer, timeout)).await
+    }
+
+    /// Respond to a read request from an I2C master.
+    pub async fn respond_to_read(&mut self, write: &[u8]) -> Result<SendStatus, Error> {
+        let timeout = self.timeout();
+        timeout.with(self.write_dma_internal_slave(write, timeout)).await
+    }
+
+    // for data reception in slave mode
+    //
+    // returns the total number of bytes received
+    async fn read_dma_internal_slave(&mut self, buffer: &mut [u8], timeout: Timeout) -> Result<usize, Error> {
+        let total_len = buffer.len();
+        let mut remaining_len = total_len;
+
+        let regs = self.info.regs;
+
+        let dma_transfer = unsafe {
+            regs.cr1().modify(|w| {
+                w.set_rxdmaen(true);
+                w.set_stopie(true);
+                w.set_tcie(true);
+            });
+            let src = regs.rxdr().as_ptr() as *mut u8;
+
+            self.rx_dma.as_mut().unwrap().read(src, buffer, Default::default())
+        };
+
+        let state = self.state;
+
+        let on_drop = OnDrop::new(|| {
+            regs.cr1().modify(|w| {
+                w.set_rxdmaen(false);
+                w.set_stopie(false);
+                w.set_tcie(false);
+            });
+        });
+
+        let total_received = poll_fn(|cx| {
+            state.waker.register(cx.waker());
+
+            let isr = regs.isr().read();
+
+            if remaining_len == total_len {
+                Self::slave_start(self.info, total_len.min(255), total_len > 255);
+                remaining_len = remaining_len.saturating_sub(255);
+                Poll::Pending
+            } else if isr.tcr() {
+                let is_last_slice = remaining_len <= 255;
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !is_last_slice, timeout) {
+                    return Poll::Ready(Err(e));
+                }
+                remaining_len = remaining_len.saturating_sub(255);
+                regs.cr1().modify(|w| w.set_tcie(true));
+                Poll::Pending
+            } else if isr.stopf() {
+                regs.icr().write(|reg| reg.set_stopcf(true));
+                let poll = Poll::Ready(Ok(total_len - remaining_len));
+                poll
+            } else {
+                Poll::Pending
+            }
+        })
+        .await?;
+
+        dma_transfer.await;
+
+        drop(on_drop);
+
+        Ok(total_received)
+    }
+
+    async fn write_dma_internal_slave(&mut self, buffer: &[u8], timeout: Timeout) -> Result<SendStatus, Error> {
+        let total_len = buffer.len();
+        let mut remaining_len = total_len;
+
+        let mut dma_transfer = unsafe {
+            let regs = self.info.regs;
+            regs.cr1().modify(|w| {
+                w.set_txdmaen(true);
+                w.set_stopie(true);
+                w.set_tcie(true);
+            });
+            let dst = regs.txdr().as_ptr() as *mut u8;
+
+            self.tx_dma.as_mut().unwrap().write(buffer, dst, Default::default())
+        };
+
+        let on_drop = OnDrop::new(|| {
+            let regs = self.info.regs;
+            regs.cr1().modify(|w| {
+                w.set_txdmaen(false);
+                w.set_stopie(false);
+                w.set_tcie(false);
+            })
+        });
+
+        let state = self.state;
+
+        let size = poll_fn(|cx| {
+            state.waker.register(cx.waker());
+
+            let isr = self.info.regs.isr().read();
+
+            if remaining_len == total_len {
+                Self::slave_start(self.info, total_len.min(255), total_len > 255);
+                remaining_len = remaining_len.saturating_sub(255);
+                Poll::Pending
+            } else if isr.tcr() {
+                let is_last_slice = remaining_len <= 255;
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !is_last_slice, timeout) {
+                    return Poll::Ready(Err(e));
+                }
+                remaining_len = remaining_len.saturating_sub(255);
+                self.info.regs.cr1().modify(|w| w.set_tcie(true));
+                Poll::Pending
+            } else if isr.stopf() {
+                self.info.regs.icr().write(|reg| reg.set_stopcf(true));
+                if remaining_len > 0 {
+                    dma_transfer.request_stop();
+                    Poll::Ready(Ok(SendStatus::LeftoverBytes(remaining_len as usize)))
+                } else {
+                    Poll::Ready(Ok(SendStatus::Done))
+                }
+            } else {
+                Poll::Pending
+            }
+        })
+        .await?;
+
+        dma_transfer.await;
+
+        drop(on_drop);
+
+        Ok(size)
+    }
+}
+
 /// I2C Stop Configuration
 ///
 /// Peripheral options for generating the STOP condition
@@ -857,7 +1414,7 @@ impl Timings {
     }
 }
 
-impl<'d, M: Mode> SetConfig for I2c<'d, M> {
+impl<'d, M: Mode> SetConfig for I2c<'d, M, Master> {
     type Config = Hertz;
     type ConfigError = ();
     fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
@@ -882,3 +1439,21 @@ impl<'d, M: Mode> SetConfig for I2c<'d, M> {
         Ok(())
     }
 }
+
+impl<'d, M: Mode> SetConfig for I2c<'d, M, MultiMaster> {
+    type Config = (Hertz, SlaveAddrConfig);
+    type ConfigError = ();
+    fn set_config(&mut self, (config, addr_config): &Self::Config) -> Result<(), ()> {
+        let timings = Timings::new(self.kernel_clock, *config);
+        self.info.regs.timingr().write(|reg| {
+            reg.set_presc(timings.prescale);
+            reg.set_scll(timings.scll);
+            reg.set_sclh(timings.sclh);
+            reg.set_sdadel(timings.sdadel);
+            reg.set_scldel(timings.scldel);
+        });
+        self.init_slave(*addr_config);
+
+        Ok(())
+    }
+}
diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs
index 20cd20dca..670d8332c 100644
--- a/embassy-stm32/src/ipcc.rs
+++ b/embassy-stm32/src/ipcc.rs
@@ -104,9 +104,6 @@ impl Ipcc {
         rcc::enable_and_reset::<IPCC>();
         IPCC::set_cpu2(true);
 
-        // set RF wake-up clock = LSE
-        crate::pac::RCC.csr().modify(|w| w.set_rfwkpsel(0b01));
-
         let regs = IPCC::regs();
 
         regs.cpu(0).cr().modify(|w| {
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 973acc9bb..c7a33ed72 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -178,7 +178,7 @@ pub use crate::_generated::interrupt;
 macro_rules! bind_interrupts {
     ($(#[$outer:meta])* $vis:vis struct $name:ident {
         $(
-            $(#[$inner:meta])*
+            $(#[doc = $doc:literal])*
             $(#[cfg($cond_irq:meta)])?
             $irq:ident => $(
                 $(#[cfg($cond_handler:meta)])?
@@ -194,13 +194,15 @@ macro_rules! bind_interrupts {
             #[allow(non_snake_case)]
             #[no_mangle]
             $(#[cfg($cond_irq)])?
-            $(#[$inner])*
+            $(#[doc = $doc])*
             unsafe extern "C" fn $irq() {
-                $(
-                    $(#[cfg($cond_handler)])?
-                    <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
+                unsafe {
+                    $(
+                        $(#[cfg($cond_handler)])?
+                        <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
 
-                )*
+                    )*
+                }
             }
 
             $(#[cfg($cond_irq)])?
@@ -242,12 +244,12 @@ pub struct Config {
     #[cfg(dbgmcu)]
     pub enable_debug_during_sleep: bool,
 
-    /// On low-power boards (eg. `stm32l4`, `stm32l5` and `stm32u5`),
+    /// On low-power boards (eg. `stm32l4`, `stm32l5`, `stm32wba` and `stm32u5`),
     /// some GPIO pins are powered by an auxiliary, independent power supply (`VDDIO2`),
     /// which needs to be enabled before these pins can be used.
     ///
     /// May increase power consumption. Defaults to true.
-    #[cfg(any(stm32l4, stm32l5, stm32u5))]
+    #[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba))]
     pub enable_independent_io_supply: bool,
 
     /// On the U5 series all analog peripherals are powered by a separate supply.
@@ -291,7 +293,7 @@ impl Default for Config {
             rcc: Default::default(),
             #[cfg(dbgmcu)]
             enable_debug_during_sleep: true,
-            #[cfg(any(stm32l4, stm32l5, stm32u5))]
+            #[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba))]
             enable_independent_io_supply: true,
             #[cfg(stm32u5)]
             enable_independent_analog_supply: true,
@@ -540,6 +542,13 @@ fn init_hw(config: Config) -> Peripherals {
                 w.set_iosv(config.enable_independent_io_supply);
             });
         }
+        #[cfg(stm32wba)]
+        {
+            use crate::pac::pwr::vals;
+            crate::pac::PWR.svmcr().modify(|w| {
+                w.set_io2sv(vals::Io2sv::B_0X1);
+            });
+        }
         #[cfg(stm32u5)]
         {
             crate::pac::PWR.svmcr().modify(|w| {
diff --git a/embassy-stm32/src/low_power.rs b/embassy-stm32/src/low_power.rs
index 7734365f1..d13df5a6b 100644
--- a/embassy-stm32/src/low_power.rs
+++ b/embassy-stm32/src/low_power.rs
@@ -124,15 +124,18 @@ pub enum StopMode {
     Stop2,
 }
 
-#[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0))]
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32u0))]
 use stm32_metapac::pwr::vals::Lpms;
 
-#[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0))]
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32u0))]
 impl Into<Lpms> for StopMode {
     fn into(self) -> Lpms {
         match self {
             StopMode::Stop1 => Lpms::STOP1,
+            #[cfg(not(stm32wba))]
             StopMode::Stop2 => Lpms::STOP2,
+            #[cfg(stm32wba)]
+            StopMode::Stop2 => Lpms::STOP1, // TODO: WBA has no STOP2?
         }
     }
 }
@@ -198,7 +201,7 @@ impl Executor {
 
     #[allow(unused_variables)]
     fn configure_stop(&mut self, stop_mode: StopMode) {
-        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0))]
+        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0, stm32wba))]
         crate::pac::PWR.cr1().modify(|m| m.set_lpms(stop_mode.into()));
         #[cfg(stm32h5)]
         crate::pac::PWR.pmcr().modify(|v| {
diff --git a/embassy-stm32/src/lptim/timer/mod.rs b/embassy-stm32/src/lptim/timer/mod.rs
index a629be62b..648da5940 100644
--- a/embassy-stm32/src/lptim/timer/mod.rs
+++ b/embassy-stm32/src/lptim/timer/mod.rs
@@ -115,6 +115,31 @@ impl<'d, T: Instance> Timer<'d, T> {
             .ccmr(0)
             .modify(|w| w.set_ccsel(channel.index(), direction.into()));
     }
+
+    /// Enable the timer interrupt.
+    pub fn enable_interrupt(&self) {
+        T::regs().dier().modify(|w| w.set_arrmie(true));
+    }
+
+    /// Disable the timer interrupt.
+    pub fn disable_interrupt(&self) {
+        T::regs().dier().modify(|w| w.set_arrmie(false));
+    }
+
+    /// Check if the timer interrupt is enabled.
+    pub fn is_interrupt_enabled(&self) -> bool {
+        T::regs().dier().read().arrmie()
+    }
+
+    /// Check if the timer interrupt is pending.
+    pub fn is_interrupt_pending(&self) -> bool {
+        T::regs().isr().read().arrm()
+    }
+
+    /// Clear the timer interrupt.
+    pub fn clear_interrupt(&self) {
+        T::regs().icr().write(|w| w.set_arrmcf(true));
+    }
 }
 
 #[cfg(not(any(lptim_v2a, lptim_v2b)))]
@@ -128,4 +153,29 @@ impl<'d, T: Instance> Timer<'d, T> {
     pub fn get_compare_value(&self) -> u16 {
         T::regs().cmp().read().cmp()
     }
+
+    /// Enable the timer interrupt.
+    pub fn enable_interrupt(&self) {
+        T::regs().ier().modify(|w| w.set_arrmie(true));
+    }
+
+    /// Disable the timer interrupt.
+    pub fn disable_interrupt(&self) {
+        T::regs().ier().modify(|w| w.set_arrmie(false));
+    }
+
+    /// Check if the timer interrupt is enabled.
+    pub fn is_interrupt_enabled(&self) -> bool {
+        T::regs().ier().read().arrmie()
+    }
+
+    /// Check if the timer interrupt is pending.
+    pub fn is_interrupt_pending(&self) -> bool {
+        T::regs().isr().read().arrm()
+    }
+
+    /// Clear the timer interrupt.
+    pub fn clear_interrupt(&self) {
+        T::regs().icr().write(|w| w.set_arrmcf(true));
+    }
 }
diff --git a/embassy-stm32/src/macros.rs b/embassy-stm32/src/macros.rs
index 7526bb180..3a0b490ba 100644
--- a/embassy-stm32/src/macros.rs
+++ b/embassy-stm32/src/macros.rs
@@ -81,17 +81,28 @@ macro_rules! dma_trait {
             /// Note: in some chips, ST calls this the "channel", and calls channels "streams".
             /// `embassy-stm32` always uses the "channel" and "request number" names.
             fn request(&self) -> crate::dma::Request;
+            #[doc = "Remap the DMA channel"]
+            fn remap(&self);
         }
     };
 }
 
 #[allow(unused)]
 macro_rules! dma_trait_impl {
-    (crate::$mod:ident::$trait:ident$(<$mode:ident>)?, $instance:ident, $channel:ident, $request:expr) => {
+    (crate::$mod:ident::$trait:ident$(<$mode:ident>)?, $instance:ident, $channel:ident, $request:expr, $remap:expr) => {
         impl crate::$mod::$trait<crate::peripherals::$instance $(, crate::$mod::$mode)?> for crate::peripherals::$channel {
             fn request(&self) -> crate::dma::Request {
                 $request
             }
+
+            fn remap(&self) {
+                critical_section::with(|_| {
+                    #[allow(unused_unsafe)]
+                    unsafe {
+                        $remap;
+                    }
+                });
+            }
         }
     };
 }
@@ -111,6 +122,7 @@ macro_rules! new_dma_nonopt {
 macro_rules! new_dma {
     ($name:ident) => {{
         let dma = $name;
+        dma.remap();
         let request = dma.request();
         Some(crate::dma::ChannelAndRequest {
             channel: dma.into(),
diff --git a/embassy-stm32/src/opamp.rs b/embassy-stm32/src/opamp.rs
index 2eb2e61c1..e36719ef3 100644
--- a/embassy-stm32/src/opamp.rs
+++ b/embassy-stm32/src/opamp.rs
@@ -4,10 +4,12 @@
 use embassy_hal_internal::PeripheralType;
 
 use crate::pac::opamp::vals::*;
+#[cfg(not(any(stm32g4, stm32f3)))]
+use crate::rcc::RccInfo;
 use crate::Peri;
 
 /// Performs a busy-wait delay for a specified number of microseconds.
-#[cfg(opamp_g4)]
+#[cfg(opamp_v5)]
 fn blocking_delay_ms(ms: u32) {
     #[cfg(feature = "time")]
     embassy_time::block_for(embassy_time::Duration::from_millis(ms as u64));
@@ -23,13 +25,13 @@ pub enum OpAmpGain {
     Mul4,
     Mul8,
     Mul16,
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     Mul32,
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     Mul64,
 }
 
-#[cfg(opamp_g4)]
+#[cfg(opamp_v5)]
 enum OpAmpDifferentialPair {
     P,
     N,
@@ -53,7 +55,7 @@ pub struct OpAmpOutput<'d, T: Instance> {
 /// OpAmp internal outputs, wired directly to ADC inputs.
 ///
 /// This struct can be used as an ADC input.
-#[cfg(opamp_g4)]
+#[cfg(opamp_v5)]
 pub struct OpAmpInternalOutput<'d, T: Instance> {
     _inner: &'d OpAmp<'d, T>,
 }
@@ -67,8 +69,10 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// Create a new driver instance.
     ///
     /// Does not enable the opamp, but does set the speed mode on some families.
-    pub fn new(opamp: Peri<'d, T>, #[cfg(opamp_g4)] speed: OpAmpSpeed) -> Self {
-        #[cfg(opamp_g4)]
+    pub fn new(opamp: Peri<'d, T>, #[cfg(opamp_v5)] speed: OpAmpSpeed) -> Self {
+        #[cfg(not(any(stm32g4, stm32f3)))]
+        T::info().rcc.enable_and_reset();
+        #[cfg(opamp_v5)]
         T::regs().csr().modify(|w| {
             w.set_opahsm(speed == OpAmpSpeed::HighSpeed);
         });
@@ -94,15 +98,15 @@ impl<'d, T: Instance> OpAmp<'d, T> {
         in_pin.set_as_analog();
         out_pin.set_as_analog();
 
-        #[cfg(opamp_g4)]
+        #[cfg(opamp_v5)]
         let vm_sel = VmSel::OUTPUT;
-        #[cfg(not(opamp_g4))]
+        #[cfg(not(opamp_v5))]
         let vm_sel = VmSel::from_bits(0b11);
 
         T::regs().csr().modify(|w| {
             w.set_vp_sel(VpSel::from_bits(in_pin.channel()));
             w.set_vm_sel(vm_sel);
-            #[cfg(opamp_g4)]
+            #[cfg(opamp_v5)]
             w.set_opaintoen(false);
             w.set_opampen(true);
         });
@@ -129,12 +133,12 @@ impl<'d, T: Instance> OpAmp<'d, T> {
         in_pin.set_as_analog();
         out_pin.set_as_analog();
 
-        #[cfg(opamp_g4)]
+        #[cfg(opamp_v5)]
         let vm_sel = VmSel::PGA;
-        #[cfg(not(opamp_g4))]
+        #[cfg(not(opamp_v5))]
         let vm_sel = VmSel::from_bits(0b10);
 
-        #[cfg(opamp_g4)]
+        #[cfg(opamp_v5)]
         let pga_gain = match gain {
             OpAmpGain::Mul2 => PgaGain::GAIN2,
             OpAmpGain::Mul4 => PgaGain::GAIN4,
@@ -143,7 +147,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
             OpAmpGain::Mul32 => PgaGain::GAIN32,
             OpAmpGain::Mul64 => PgaGain::GAIN64,
         };
-        #[cfg(not(opamp_g4))]
+        #[cfg(not(opamp_v5))]
         let pga_gain = PgaGain::from_bits(match gain {
             OpAmpGain::Mul2 => 0b00,
             OpAmpGain::Mul4 => 0b01,
@@ -155,7 +159,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
             w.set_vp_sel(VpSel::from_bits(in_pin.channel()));
             w.set_vm_sel(vm_sel);
             w.set_pga_gain(pga_gain);
-            #[cfg(opamp_g4)]
+            #[cfg(opamp_v5)]
             w.set_opaintoen(false);
             w.set_opampen(true);
         });
@@ -170,7 +174,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// preventing it being used elsewhere. The `OpAmpOutput` can then be
     /// directly used as an ADC input. The opamp will be disabled when the
     /// [`OpAmpOutput`] is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn buffer_dac(&mut self, out_pin: Peri<'_, impl OutputPin<T> + crate::gpio::Pin>) -> OpAmpOutput<'_, T> {
         out_pin.set_as_analog();
 
@@ -194,7 +198,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     ///
     /// The returned `OpAmpInternalOutput` struct may be used as an ADC input.
     /// The opamp output will be disabled when it is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn buffer_int(
         &mut self,
         pin: Peri<'_, impl NonInvertingPin<T> + crate::gpio::Pin>,
@@ -204,7 +208,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
         T::regs().csr().modify(|w| {
             w.set_vp_sel(VpSel::from_bits(pin.channel()));
             w.set_vm_sel(VmSel::OUTPUT);
-            #[cfg(opamp_g4)]
+            #[cfg(opamp_v5)]
             w.set_opaintoen(true);
             w.set_opampen(true);
         });
@@ -220,7 +224,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     ///
     /// The returned `OpAmpInternalOutput` struct may be used as an ADC input.
     /// The opamp output will be disabled when it is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn pga_int(
         &mut self,
         pin: Peri<'_, impl NonInvertingPin<T> + crate::gpio::Pin>,
@@ -257,7 +261,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     ///
     /// The returned `OpAmpInternalOutput` struct may be used as an ADC
     /// input. The opamp output will be disabled when it is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn standalone_dac_int(
         &mut self,
         m_pin: Peri<'_, impl InvertingPin<T> + crate::gpio::Pin>,
@@ -285,7 +289,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// The output pin is held within the returned [`OpAmpOutput`] struct,
     /// preventing it being used elsewhere. The opamp will be disabled when
     /// the [`OpAmpOutput`] is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn standalone_dac_ext(
         &mut self,
         m_pin: Peri<'_, impl InvertingPin<T> + crate::gpio::Pin>,
@@ -315,7 +319,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// The output pin is held within the returned [`OpAmpOutput`] struct,
     /// preventing it being used elsewhere. The opamp will be disabled when
     /// the [`OpAmpOutput`] is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn standalone_ext(
         &mut self,
         p_pin: Peri<'d, impl NonInvertingPin<T> + crate::gpio::Pin>,
@@ -346,7 +350,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     ///
     /// The returned `OpAmpOutput` struct may be used as an ADC
     /// input. The opamp output will be disabled when it is dropped.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn standalone_int(
         &mut self,
         p_pin: Peri<'d, impl NonInvertingPin<T> + crate::gpio::Pin>,
@@ -374,7 +378,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// while for high-speed mode, only the P differential pair is calibrated.
     ///
     /// Calibrating a differential pair requires waiting 12ms in the worst case (binary method).
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     pub fn calibrate(&mut self) {
         T::regs().csr().modify(|w| {
             w.set_opampen(true);
@@ -403,7 +407,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// The calibration range is from 0 to 31.
     ///
     /// The result is stored in the OPAMP_CSR register.
-    #[cfg(opamp_g4)]
+    #[cfg(opamp_v5)]
     fn calibrate_differential_pair(&mut self, pair: OpAmpDifferentialPair) {
         let mut low = 0;
         let mut high = 31;
@@ -452,6 +456,13 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     }
 }
 
+#[cfg(not(any(stm32g4, stm32f3)))]
+impl<'d, T: Instance> Drop for OpAmp<'d, T> {
+    fn drop(&mut self) {
+        T::info().rcc.disable();
+    }
+}
+
 impl<'d, T: Instance> Drop for OpAmpOutput<'d, T> {
     fn drop(&mut self) {
         T::regs().csr().modify(|w| {
@@ -460,7 +471,7 @@ impl<'d, T: Instance> Drop for OpAmpOutput<'d, T> {
     }
 }
 
-#[cfg(opamp_g4)]
+#[cfg(opamp_v5)]
 impl<'d, T: Instance> Drop for OpAmpInternalOutput<'d, T> {
     fn drop(&mut self) {
         T::regs().csr().modify(|w| {
@@ -469,7 +480,14 @@ impl<'d, T: Instance> Drop for OpAmpInternalOutput<'d, T> {
     }
 }
 
+#[cfg(not(any(stm32g4, stm32f3)))]
+pub(crate) struct Info {
+    rcc: RccInfo,
+}
+
 pub(crate) trait SealedInstance {
+    #[cfg(not(any(stm32g4, stm32f3)))]
+    fn info() -> &'static Info;
     fn regs() -> crate::pac::opamp::Opamp;
 }
 
@@ -545,7 +563,7 @@ foreach_peripheral!(
     };
 );
 
-#[cfg(opamp_g4)]
+#[cfg(opamp_v5)]
 macro_rules! impl_opamp_internal_output {
     ($inst:ident, $adc:ident, $ch:expr) => {
         foreach_adc!(
@@ -567,7 +585,7 @@ macro_rules! impl_opamp_internal_output {
     };
 }
 
-#[cfg(opamp_g4)]
+#[cfg(opamp_v5)]
 foreach_peripheral!(
     (opamp, OPAMP1) => {
         impl_opamp_internal_output!(OPAMP1, ADC1, 13);
@@ -600,6 +618,15 @@ foreach_peripheral!(
 foreach_peripheral! {
     (opamp, $inst:ident) => {
         impl SealedInstance for crate::peripherals::$inst {
+            // G4 and F3 use SYSCFGEN, which is always enabled
+            #[cfg(not(any(stm32g4, stm32f3)))]
+            fn info() -> &'static Info {
+                use crate::rcc::SealedRccPeripheral;
+                static INFO: Info = Info {
+                    rcc: crate::peripherals::$inst::RCC_INFO,
+                };
+                &INFO
+            }
             fn regs() -> crate::pac::opamp::Opamp {
                 crate::pac::$inst
             }
diff --git a/embassy-stm32/src/qspi/enums.rs b/embassy-stm32/src/qspi/enums.rs
index 9ec4c1b43..fa5e36d06 100644
--- a/embassy-stm32/src/qspi/enums.rs
+++ b/embassy-stm32/src/qspi/enums.rs
@@ -331,3 +331,19 @@ impl From<DummyCycles> for u8 {
         }
     }
 }
+
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum SampleShifting {
+    None,
+    HalfCycle,
+}
+
+impl From<SampleShifting> for bool {
+    fn from(value: SampleShifting) -> Self {
+        match value {
+            SampleShifting::None => false,
+            SampleShifting::HalfCycle => true,
+        }
+    }
+}
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index 0df057c53..1e20d7cd3 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -58,6 +58,8 @@ pub struct Config {
     pub fifo_threshold: FIFOThresholdLevel,
     /// Minimum number of cycles that chip select must be high between issued commands
     pub cs_high_time: ChipSelectHighTime,
+    /// Shift sampling point of input data (none, or half-cycle)
+    pub sample_shifting: SampleShifting,
 }
 
 impl Default for Config {
@@ -68,6 +70,7 @@ impl Default for Config {
             prescaler: 128,
             fifo_threshold: FIFOThresholdLevel::_17Bytes,
             cs_high_time: ChipSelectHighTime::_5Cycle,
+            sample_shifting: SampleShifting::None,
         }
     }
 }
@@ -120,7 +123,7 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
         T::REGS.cr().modify(|w| {
             w.set_en(true);
             //w.set_tcen(false);
-            w.set_sshift(false);
+            w.set_sshift(config.sample_shifting.into());
             w.set_fthres(config.fifo_threshold.into());
             w.set_prescaler(config.prescaler);
             w.set_fsel(fsel.into());
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index cac2a9149..c2295bab6 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -190,6 +190,8 @@ pub(crate) unsafe fn init(config: Config) {
         // TODO
         lsi: None,
         lse: None,
+        #[cfg(crs)]
+        hsi48: None,
     );
 
     RCC.ccipr()
diff --git a/embassy-stm32/src/rcc/hsi48.rs b/embassy-stm32/src/rcc/hsi48.rs
index 3ea5c96c9..49be4af5e 100644
--- a/embassy-stm32/src/rcc/hsi48.rs
+++ b/embassy-stm32/src/rcc/hsi48.rs
@@ -39,9 +39,9 @@ pub(crate) fn init_hsi48(config: Hsi48Config) -> Hertz {
     });
 
     // Enable HSI48
-    #[cfg(not(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32h7rs, stm32u5, stm32wba, stm32f0)))]
+    #[cfg(not(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32h7rs, stm32u5, stm32wba, stm32f0, stm32c071)))]
     let r = RCC.crrcr();
-    #[cfg(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32h7rs, stm32u5, stm32wba))]
+    #[cfg(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32h7rs, stm32u5, stm32wba, stm32c071))]
     let r = RCC.cr();
     #[cfg(any(stm32f0))]
     let r = RCC.cr2();
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs
index c50e071fb..96e628b1a 100644
--- a/embassy-stm32/src/rcc/mco.rs
+++ b/embassy-stm32/src/rcc/mco.rs
@@ -74,7 +74,7 @@ macro_rules! impl_peri {
     };
 }
 
-#[cfg(any(rcc_c0, rcc_g0, rcc_u0))]
+#[cfg(any(rcc_c0, rcc_c0v2, rcc_g0x0, rcc_g0x1, rcc_u0))]
 #[allow(unused_imports)]
 use self::{McoSource as Mco1Source, McoSource as Mco2Source};
 
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 3733fed56..c41f81816 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -95,6 +95,15 @@ pub(crate) unsafe fn get_freqs() -> &'static Clocks {
     unwrap!(CLOCK_FREQS_PTR.load(core::sync::atomic::Ordering::SeqCst).as_ref()).assume_init_ref()
 }
 
+/// Get the current clock configuration of the chip.
+pub fn clocks<'a>(_rcc: &'a crate::Peri<'a, crate::peripherals::RCC>) -> &'a Clocks {
+    // Safety: the existence of a `Peri<RCC>` means that `rcc::init()`
+    // has already been called, so `CLOCK_FREQS` must be initialized.
+    // The clocks could be modified again by `reinit()`, but reinit
+    // (for this reason) requires an exclusive reference to `Peri<RCC>`.
+    unsafe { get_freqs() }
+}
+
 pub(crate) trait SealedRccPeripheral {
     fn frequency() -> Hertz;
     #[allow(dead_code)]
@@ -381,7 +390,7 @@ pub fn disable<T: RccPeripheral>() {
 ///
 /// This should only be called after `init`.
 #[cfg(not(feature = "_dual-core"))]
-pub fn reinit(config: Config) {
+pub fn reinit<'a>(config: Config, _rcc: &'a mut crate::Peri<'a, crate::peripherals::RCC>) {
     critical_section::with(|cs| init_rcc(cs, config))
 }
 
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 97eb2eb6d..06895a99a 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -5,7 +5,7 @@ pub use crate::pac::rcc::vals::{
     Hpre as AHBPrescaler, Msirange, Msirange as MSIRange, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul,
     Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
 };
-use crate::pac::rcc::vals::{Hseext, Msirgsel, Pllmboost, Pllrge};
+use crate::pac::rcc::vals::{Hseext, Msipllfast, Msipllsel, Msirgsel, Pllmboost, Pllrge};
 #[cfg(all(peri_usb_otg_hs))]
 pub use crate::pac::{syscfg::vals::Usbrefcksel, SYSCFG};
 use crate::pac::{FLASH, PWR, RCC};
@@ -64,6 +64,46 @@ pub struct Pll {
     pub divr: Option<PllDiv>,
 }
 
+#[derive(Clone, Copy, PartialEq)]
+pub enum MsiAutoCalibration {
+    /// MSI auto-calibration is disabled
+    Disabled,
+    /// MSIS is given priority for auto-calibration
+    MSIS,
+    /// MSIK is given priority for auto-calibration
+    MSIK,
+    /// MSIS with fast mode (always on)
+    MsisFast,
+    /// MSIK with fast mode (always on)
+    MsikFast,
+}
+
+impl MsiAutoCalibration {
+    const fn default() -> Self {
+        MsiAutoCalibration::Disabled
+    }
+
+    fn base_mode(&self) -> Self {
+        match self {
+            MsiAutoCalibration::Disabled => MsiAutoCalibration::Disabled,
+            MsiAutoCalibration::MSIS => MsiAutoCalibration::MSIS,
+            MsiAutoCalibration::MSIK => MsiAutoCalibration::MSIK,
+            MsiAutoCalibration::MsisFast => MsiAutoCalibration::MSIS,
+            MsiAutoCalibration::MsikFast => MsiAutoCalibration::MSIK,
+        }
+    }
+
+    fn is_fast(&self) -> bool {
+        matches!(self, MsiAutoCalibration::MsisFast | MsiAutoCalibration::MsikFast)
+    }
+}
+
+impl Default for MsiAutoCalibration {
+    fn default() -> Self {
+        Self::default()
+    }
+}
+
 #[derive(Clone, Copy)]
 pub struct Config {
     // base clock sources
@@ -95,6 +135,7 @@ pub struct Config {
 
     /// Per-peripheral kernel clock selection muxes
     pub mux: super::mux::ClockMux,
+    pub auto_calibration: MsiAutoCalibration,
 }
 
 impl Config {
@@ -116,6 +157,7 @@ impl Config {
             voltage_range: VoltageScale::RANGE1,
             ls: crate::rcc::LsConfig::new(),
             mux: super::mux::ClockMux::default(),
+            auto_calibration: MsiAutoCalibration::default(),
         }
     }
 }
@@ -131,7 +173,42 @@ pub(crate) unsafe fn init(config: Config) {
     PWR.vosr().modify(|w| w.set_vos(config.voltage_range));
     while !PWR.vosr().read().vosrdy() {}
 
-    let msis = config.msis.map(|range| {
+    let lse_calibration_freq = if config.auto_calibration != MsiAutoCalibration::Disabled {
+        // LSE must be configured and peripherals clocked for MSI auto-calibration
+        let lse_config = config
+            .ls
+            .lse
+            .clone()
+            .expect("LSE must be configured for MSI auto-calibration");
+        assert!(lse_config.peripherals_clocked);
+
+        // Expect less than +/- 5% deviation for LSE frequency
+        if (31_100..=34_400).contains(&lse_config.frequency.0) {
+            // Check that the calibration is applied to an active clock
+            match (
+                config.auto_calibration.base_mode(),
+                config.msis.is_some(),
+                config.msik.is_some(),
+            ) {
+                (MsiAutoCalibration::MSIS, true, _) => {
+                    // MSIS is active and using LSE for auto-calibration
+                    Some(lse_config.frequency)
+                }
+                (MsiAutoCalibration::MSIK, _, true) => {
+                    // MSIK is active and using LSE for auto-calibration
+                    Some(lse_config.frequency)
+                }
+                // improper configuration
+                _ => panic!("MSIx auto-calibration is enabled for a source that has not been configured."),
+            }
+        } else {
+            panic!("LSE frequency more than 5% off from 32.768 kHz, cannot use for MSI auto-calibration");
+        }
+    } else {
+        None
+    };
+
+    let mut msis = config.msis.map(|range| {
         // Check MSI output per RM0456 § 11.4.10
         match config.voltage_range {
             VoltageScale::RANGE4 => {
@@ -156,11 +233,21 @@ pub(crate) unsafe fn init(config: Config) {
             w.set_msipllen(false);
             w.set_msison(true);
         });
+        let msis = if let (Some(freq), MsiAutoCalibration::MSIS) =
+            (lse_calibration_freq, config.auto_calibration.base_mode())
+        {
+            // Enable the MSIS auto-calibration feature
+            RCC.cr().modify(|w| w.set_msipllsel(Msipllsel::MSIS));
+            RCC.cr().modify(|w| w.set_msipllen(true));
+            calculate_calibrated_msi_frequency(range, freq)
+        } else {
+            msirange_to_hertz(range)
+        };
         while !RCC.cr().read().msisrdy() {}
-        msirange_to_hertz(range)
+        msis
     });
 
-    let msik = config.msik.map(|range| {
+    let mut msik = config.msik.map(|range| {
         // Check MSI output per RM0456 § 11.4.10
         match config.voltage_range {
             VoltageScale::RANGE4 => {
@@ -184,10 +271,44 @@ pub(crate) unsafe fn init(config: Config) {
         RCC.cr().modify(|w| {
             w.set_msikon(true);
         });
+        let msik = if let (Some(freq), MsiAutoCalibration::MSIK) =
+            (lse_calibration_freq, config.auto_calibration.base_mode())
+        {
+            // Enable the MSIK auto-calibration feature
+            RCC.cr().modify(|w| w.set_msipllsel(Msipllsel::MSIK));
+            RCC.cr().modify(|w| w.set_msipllen(true));
+            calculate_calibrated_msi_frequency(range, freq)
+        } else {
+            msirange_to_hertz(range)
+        };
         while !RCC.cr().read().msikrdy() {}
-        msirange_to_hertz(range)
+        msik
     });
 
+    if let Some(lse_freq) = lse_calibration_freq {
+        // If both MSIS and MSIK are enabled, we need to check if they are using the same internal source.
+        if let (Some(msis_range), Some(msik_range)) = (config.msis, config.msik) {
+            if (msis_range as u8 >> 2) == (msik_range as u8 >> 2) {
+                // Clock source is shared, both will be auto calibrated, recalculate other frequency
+                match config.auto_calibration.base_mode() {
+                    MsiAutoCalibration::MSIS => {
+                        msik = Some(calculate_calibrated_msi_frequency(msik_range, lse_freq));
+                    }
+                    MsiAutoCalibration::MSIK => {
+                        msis = Some(calculate_calibrated_msi_frequency(msis_range, lse_freq));
+                    }
+                    _ => {}
+                }
+            }
+        }
+        // Check if Fast mode should be used
+        if config.auto_calibration.is_fast() {
+            RCC.cr().modify(|w| {
+                w.set_msipllfast(Msipllfast::FAST);
+            });
+        }
+    }
+
     let hsi = config.hsi.then(|| {
         RCC.cr().modify(|w| w.set_hsion(true));
         while !RCC.cr().read().hsirdy() {}
@@ -514,3 +635,37 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput, voltag
 
     PllOutput { p, q, r }
 }
+
+/// Fraction structure for MSI auto-calibration
+/// Represents the multiplier as numerator/denominator that LSE frequency is multiplied by
+#[derive(Debug, Clone, Copy)]
+struct MsiFraction {
+    numerator: u32,
+    denominator: u32,
+}
+
+impl MsiFraction {
+    const fn new(numerator: u32, denominator: u32) -> Self {
+        Self { numerator, denominator }
+    }
+
+    /// Calculate the calibrated frequency given an LSE frequency
+    fn calculate_frequency(&self, lse_freq: Hertz) -> Hertz {
+        Hertz(lse_freq.0 * self.numerator / self.denominator)
+    }
+}
+
+fn get_msi_calibration_fraction(range: Msirange) -> MsiFraction {
+    // Exploiting the MSIx internals to make calculations compact
+    let denominator = (range as u32 & 0x03) + 1;
+    // Base multipliers are deduced from Table 82: MSI oscillator characteristics in data sheet
+    let numerator = [1465, 122, 94, 12][range as usize >> 2];
+
+    MsiFraction::new(numerator, denominator)
+}
+
+/// Calculate the calibrated MSI frequency for a given range and LSE frequency
+fn calculate_calibrated_msi_frequency(range: Msirange, lse_freq: Hertz) -> Hertz {
+    let fraction = get_msi_calibration_fraction(range);
+    fraction.calculate_frequency(lse_freq)
+}
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index b9fc4e423..b494997b3 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -176,6 +176,7 @@ pub(crate) unsafe fn init(config: Config) {
         // TODO
         lse: None,
         lsi: None,
+        pll1_p: None,
         pll1_q: None,
     );
 }
diff --git a/embassy-stm32/src/rtc/low_power.rs b/embassy-stm32/src/rtc/low_power.rs
index cd075f3de..78ccd3e6c 100644
--- a/embassy-stm32/src/rtc/low_power.rs
+++ b/embassy-stm32/src/rtc/low_power.rs
@@ -66,7 +66,7 @@ pub(crate) enum WakeupPrescaler {
 }
 
 #[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0
+    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba
 ))]
 impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
     fn from(val: WakeupPrescaler) -> Self {
@@ -82,7 +82,7 @@ impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
 }
 
 #[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0
+    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba
 ))]
 impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
     fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
@@ -227,7 +227,7 @@ impl Rtc {
         <RTC as crate::rtc::SealedInstance>::WakeupInterrupt::unpend();
         unsafe { <RTC as crate::rtc::SealedInstance>::WakeupInterrupt::enable() };
 
-        #[cfg(not(any(stm32u5, stm32u0)))]
+        #[cfg(not(any(stm32u5, stm32u0, stm32wba)))]
         {
             use crate::pac::EXTI;
             EXTI.rtsr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
@@ -247,5 +247,11 @@ impl Rtc {
             RCC.srdamr().modify(|w| w.set_rtcapbamen(true));
             RCC.apb3smenr().modify(|w| w.set_rtcapbsmen(true));
         }
+        #[cfg(stm32wba)]
+        {
+            use crate::pac::RCC;
+            // RCC.srdamr().modify(|w| w.set_rtcapbamen(true));
+            RCC.apb7smenr().modify(|w| w.set_rtcapbsmen(true));
+        }
     }
 }
diff --git a/embassy-stm32/src/rtc/mod.rs b/embassy-stm32/src/rtc/mod.rs
index 49f423f37..449f3008a 100644
--- a/embassy-stm32/src/rtc/mod.rs
+++ b/embassy-stm32/src/rtc/mod.rs
@@ -25,7 +25,7 @@ use crate::time::Hertz;
     ),
     path = "v2.rs"
 )]
-#[cfg_attr(any(rtc_v3, rtc_v3u5, rtc_v3l5, rtc_v3h7rs), path = "v3.rs")]
+#[cfg_attr(any(rtc_v3, rtc_v3u5, rtc_v3l5, rtc_v3h7rs, rtc_v3c0), path = "v3.rs")]
 mod _version;
 #[allow(unused_imports)]
 pub use _version::*;
@@ -296,7 +296,7 @@ trait SealedInstance {
     const BACKUP_REGISTER_COUNT: usize;
 
     #[cfg(feature = "low-power")]
-    #[cfg(not(any(stm32u5, stm32u0)))]
+    #[cfg(not(any(stm32wba, stm32u5, stm32u0)))]
     const EXTI_WAKEUP_LINE: usize;
 
     #[cfg(feature = "low-power")]
diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs
index 39aa6c5cb..d0b52049e 100644
--- a/embassy-stm32/src/rtc/v3.rs
+++ b/embassy-stm32/src/rtc/v3.rs
@@ -146,7 +146,7 @@ impl SealedInstance for crate::peripherals::RTC {
             type WakeupInterrupt = crate::interrupt::typelevel::RTC_WKUP;
         } else if #[cfg(any(stm32g0, stm32u0))] {
             type WakeupInterrupt = crate::interrupt::typelevel::RTC_TAMP;
-        } else if #[cfg(any(stm32l5, stm32h5, stm32u5))] {
+        } else if #[cfg(any(stm32l5, stm32h5, stm32u5, stm32wba))] {
             type WakeupInterrupt = crate::interrupt::typelevel::RTC;
         }
     );
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index 6a02aae70..6e5d735d7 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -32,25 +32,48 @@ pub struct InterruptHandler<T: Instance> {
 }
 
 impl<T: Instance> InterruptHandler<T> {
-    fn data_interrupts(enable: bool) {
+    fn enable_interrupts() {
         let regs = T::regs();
         regs.maskr().write(|w| {
-            w.set_dcrcfailie(enable);
-            w.set_dtimeoutie(enable);
-            w.set_dataendie(enable);
+            w.set_dcrcfailie(true);
+            w.set_dtimeoutie(true);
+            w.set_dataendie(true);
+            w.set_dbckendie(true);
 
             #[cfg(sdmmc_v1)]
-            w.set_stbiterre(enable);
+            w.set_stbiterre(true);
             #[cfg(sdmmc_v2)]
-            w.set_dabortie(enable);
+            w.set_dabortie(true);
         });
     }
 }
 
 impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
     unsafe fn on_interrupt() {
-        Self::data_interrupts(false);
         T::state().wake();
+        let status = T::regs().star().read();
+        T::regs().maskr().modify(|w| {
+            if status.dcrcfail() {
+                w.set_dcrcfailie(false)
+            }
+            if status.dtimeout() {
+                w.set_dtimeoutie(false)
+            }
+            if status.dataend() {
+                w.set_dataendie(false)
+            }
+            if status.dbckend() {
+                w.set_dbckendie(false)
+            }
+            #[cfg(sdmmc_v1)]
+            if status.stbiterr() {
+                w.set_stbiterre(false)
+            }
+            #[cfg(sdmmc_v2)]
+            if status.dabort() {
+                w.set_dabortie(false)
+            }
+        });
     }
 }
 
@@ -225,8 +248,7 @@ fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(bool, u8, Hertz), Error> {
         return Ok((true, 0, ker_ck));
     }
 
-    // `ker_ck / sdmmc_ck` rounded up
-    let clk_div = match (ker_ck.0 + sdmmc_ck - 1) / sdmmc_ck {
+    let clk_div = match ker_ck.0.div_ceil(sdmmc_ck) {
         0 | 1 => Ok(0),
         x @ 2..=258 => Ok((x - 2) as u8),
         _ => Err(Error::BadClock),
@@ -244,12 +266,11 @@ fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(bool, u8, Hertz), Error> {
 /// `clk_div` is the divisor register value and `clk_f` is the resulting new clock frequency.
 #[cfg(sdmmc_v2)]
 fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(bool, u16, Hertz), Error> {
-    // `ker_ck / sdmmc_ck` rounded up
-    match (ker_ck.0 + sdmmc_ck - 1) / sdmmc_ck {
+    match ker_ck.0.div_ceil(sdmmc_ck) {
         0 | 1 => Ok((false, 0, ker_ck)),
         x @ 2..=2046 => {
             // SDMMC_CK frequency = SDMMCCLK / [CLKDIV * 2]
-            let clk_div = ((x + 1) / 2) as u16;
+            let clk_div = x.div_ceil(2) as u16;
             let clk = Hertz(ker_ck.0 / (clk_div as u32 * 2));
 
             Ok((false, clk_div, clk))
@@ -751,7 +772,6 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         Self::wait_idle();
         Self::clear_interrupt_flags();
 
-        regs.dtimer().write(|w| w.set_datatime(config.data_transfer_timeout));
         regs.dlenr().write(|w| w.set_datalength(length_bytes));
 
         #[cfg(sdmmc_v1)]
@@ -789,8 +809,6 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         Self::wait_idle();
         Self::clear_interrupt_flags();
 
-        regs.dtimer()
-            .write(|w| w.set_datatime(self.config.data_transfer_timeout));
         regs.dlenr().write(|w| w.set_datalength(length_bytes));
 
         #[cfg(sdmmc_v1)]
@@ -1007,14 +1025,14 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             // Wait for the abort
             while Self::data_active() {}
         }
-        InterruptHandler::<T>::data_interrupts(false);
+        regs.maskr().write(|_| ()); // disable irqs
         Self::clear_interrupt_flags();
         Self::stop_datapath();
     }
 
     /// Wait for a previously started datapath transfer to complete from an interrupt.
     #[inline]
-    async fn complete_datapath_transfer() -> Result<(), Error> {
+    async fn complete_datapath_transfer(block: bool) -> Result<(), Error> {
         let regs = T::regs();
 
         let res = poll_fn(|cx| {
@@ -1034,7 +1052,11 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             if status.stbiterr() {
                 return Poll::Ready(Err(Error::StBitErr));
             }
-            if status.dataend() {
+            let done = match block {
+                true => status.dbckend(),
+                false => status.dataend(),
+            };
+            if done {
                 return Poll::Ready(Ok(()));
             }
             Poll::Pending
@@ -1072,10 +1094,10 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             512,
             9,
         );
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
         Self::cmd(common_cmd::read_single_block(address), true)?;
 
-        let res = Self::complete_datapath_transfer().await;
+        let res = Self::complete_datapath_transfer(true).await;
 
         if res.is_ok() {
             on_drop.defuse();
@@ -1105,7 +1127,6 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         };
         Self::cmd(common_cmd::set_block_length(512), false)?; // CMD16
 
-        let regs = T::regs();
         let on_drop = OnDrop::new(|| Self::on_drop());
 
         let transfer = Self::prepare_datapath_read(
@@ -1116,30 +1137,11 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             512 * blocks.len() as u32,
             9,
         );
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
 
         Self::cmd(common_cmd::read_multiple_blocks(address), true)?;
 
-        let res = poll_fn(|cx| {
-            T::state().register(cx.waker());
-            let status = regs.star().read();
-
-            if status.dcrcfail() {
-                return Poll::Ready(Err(Error::Crc));
-            }
-            if status.dtimeout() {
-                return Poll::Ready(Err(Error::Timeout));
-            }
-            #[cfg(sdmmc_v1)]
-            if status.stbiterr() {
-                return Poll::Ready(Err(Error::StBitErr));
-            }
-            if status.dataend() {
-                return Poll::Ready(Ok(()));
-            }
-            Poll::Pending
-        })
-        .await;
+        let res = Self::complete_datapath_transfer(false).await;
 
         Self::cmd(common_cmd::stop_transmission(), false)?; // CMD12
         Self::clear_interrupt_flags();
@@ -1174,12 +1176,12 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         Self::cmd(common_cmd::write_single_block(address), true)?;
 
         let transfer = self.prepare_datapath_write(buffer, 512, 9);
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
 
         #[cfg(sdmmc_v2)]
         Self::cmd(common_cmd::write_single_block(address), true)?;
 
-        let res = Self::complete_datapath_transfer().await;
+        let res = Self::complete_datapath_transfer(true).await;
 
         match res {
             Ok(_) => {
@@ -1230,7 +1232,6 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
         let block_count = blocks.len();
 
-        let regs = T::regs();
         let on_drop = OnDrop::new(|| Self::on_drop());
 
         #[cfg(sdmmc_v1)]
@@ -1238,36 +1239,12 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
         // Setup write command
         let transfer = self.prepare_datapath_write(buffer, 512 * block_count as u32, 9);
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
 
         #[cfg(sdmmc_v2)]
         Self::cmd(common_cmd::write_multiple_blocks(address), true)?; // CMD25
 
-        let res = poll_fn(|cx| {
-            T::state().register(cx.waker());
-
-            let status = regs.star().read();
-
-            if status.dcrcfail() {
-                return Poll::Ready(Err(Error::Crc));
-            }
-            if status.dtimeout() {
-                return Poll::Ready(Err(Error::Timeout));
-            }
-            if status.txunderr() {
-                return Poll::Ready(Err(Error::Underrun));
-            }
-            #[cfg(sdmmc_v1)]
-            if status.stbiterr() {
-                return Poll::Ready(Err(Error::StBitErr));
-            }
-            if status.dataend() {
-                return Poll::Ready(Ok(()));
-            }
-
-            Poll::Pending
-        })
-        .await;
+        let res = Self::complete_datapath_transfer(false).await;
 
         Self::cmd(common_cmd::stop_transmission(), false)?; // CMD12
         Self::clear_interrupt_flags();
@@ -1349,6 +1326,8 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             #[cfg(sdmmc_v1)]
             w.set_bypass(_bypass);
         });
+        regs.dtimer()
+            .write(|w| w.set_datatime(self.config.data_transfer_timeout));
 
         regs.power().modify(|w| w.set_pwrctrl(PowerCtrl::On as u8));
         Self::cmd(common_cmd::idle(), false)?;
@@ -1600,10 +1579,10 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             64,
             6,
         );
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
         Self::cmd(sd_cmd::cmd6(set_function), true)?; // CMD6
 
-        let res = Self::complete_datapath_transfer().await;
+        let res = Self::complete_datapath_transfer(true).await;
 
         // Host is allowed to use the new functions at least 8
         // clocks after the end of the switch command
@@ -1660,10 +1639,10 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             8,
             3,
         );
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
         Self::cmd(sd_cmd::send_scr(), true)?;
 
-        let res = Self::complete_datapath_transfer().await;
+        let res = Self::complete_datapath_transfer(true).await;
 
         if res.is_ok() {
             on_drop.defuse();
@@ -1706,10 +1685,10 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             64,
             6,
         );
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
         Self::cmd(sd_cmd::sd_status(), true)?;
 
-        let res = Self::complete_datapath_transfer().await;
+        let res = Self::complete_datapath_transfer(true).await;
 
         if res.is_ok() {
             on_drop.defuse();
@@ -1756,10 +1735,10 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             512,
             9,
         );
-        InterruptHandler::<T>::data_interrupts(true);
+        InterruptHandler::<T>::enable_interrupts();
         Self::cmd(emmc_cmd::send_ext_csd(), true)?;
 
-        let res = Self::complete_datapath_transfer().await;
+        let res = Self::complete_datapath_transfer(true).await;
 
         if res.is_ok() {
             on_drop.defuse();
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 9e2ba093a..c8d83f07e 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -843,7 +843,7 @@ impl<'d> Spi<'d, Async> {
 
         set_rxdmaen(self.info.regs, true);
 
-        let rx_src = self.info.regs.rx_ptr();
+        let rx_src = self.info.regs.rx_ptr::<W>();
         let rx_f = unsafe { self.rx_dma.as_mut().unwrap().read_raw(rx_src, read, Default::default()) };
 
         let tx_dst: *mut W = self.info.regs.tx_ptr();
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 8eec6c0c7..b00cc18ad 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -5,14 +5,12 @@ use core::marker::PhantomData;
 use stm32_metapac::timer::vals::Ckd;
 
 use super::low_level::{CountingMode, OutputPolarity, Timer};
-use super::simple_pwm::{Ch1, Ch2, Ch3, Ch4, PwmPin};
-use super::{
-    AdvancedInstance4Channel, Channel, Channel1ComplementaryPin, Channel2ComplementaryPin, Channel3ComplementaryPin,
-    Channel4ComplementaryPin,
-};
+use super::simple_pwm::PwmPin;
+use super::{AdvancedInstance4Channel, Ch1, Ch2, Ch3, Ch4, Channel, TimerComplementaryPin};
 use crate::gpio::{AnyPin, OutputType};
 use crate::time::Hertz;
 use crate::timer::low_level::OutputCompareMode;
+use crate::timer::TimerChannel;
 use crate::Peri;
 
 /// Complementary PWM pin wrapper.
@@ -23,32 +21,23 @@ pub struct ComplementaryPwmPin<'d, T, C> {
     phantom: PhantomData<(T, C)>,
 }
 
-macro_rules! complementary_channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: AdvancedInstance4Channel> ComplementaryPwmPin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " complementary PWM pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, output_type: OutputType) -> Self {
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        crate::gpio::AfType::output(output_type, crate::gpio::Speed::VeryHigh),
-                    );
-                });
-                ComplementaryPwmPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+impl<'d, T: AdvancedInstance4Channel, C: TimerChannel> ComplementaryPwmPin<'d, T, C> {
+    /// Create a new  complementary PWM pin instance.
+    pub fn new(pin: Peri<'d, impl TimerComplementaryPin<T, C>>, output_type: OutputType) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            pin.set_as_af(
+                pin.af_num(),
+                crate::gpio::AfType::output(output_type, crate::gpio::Speed::VeryHigh),
+            );
+        });
+        ComplementaryPwmPin {
+            _pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
+    }
 }
 
-complementary_channel_impl!(new_ch1, Ch1, Channel1ComplementaryPin);
-complementary_channel_impl!(new_ch2, Ch2, Channel2ComplementaryPin);
-complementary_channel_impl!(new_ch3, Ch3, Channel3ComplementaryPin);
-complementary_channel_impl!(new_ch4, Ch4, Channel4ComplementaryPin);
-
 /// PWM driver with support for standard and complementary outputs.
 pub struct ComplementaryPwm<'d, T: AdvancedInstance4Channel> {
     inner: Timer<'d, T>,
@@ -88,6 +77,7 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
                 this.inner.set_output_compare_mode(channel, OutputCompareMode::PwmMode1);
                 this.inner.set_output_compare_preload(channel, true);
             });
+        this.inner.set_autoreload_preload(true);
 
         this
     }
@@ -121,7 +111,11 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     ///
     /// This value depends on the configured frequency and the timer's clock rate from RCC.
     pub fn get_max_duty(&self) -> u16 {
-        self.inner.get_max_compare_value() as u16 + 1
+        if self.inner.get_counting_mode().is_center_aligned() {
+            self.inner.get_max_compare_value() as u16
+        } else {
+            self.inner.get_max_compare_value() as u16 + 1
+        }
     }
 
     /// Set the duty for a given channel.
@@ -171,7 +165,11 @@ impl<'d, T: AdvancedInstance4Channel> embedded_hal_02::Pwm for ComplementaryPwm<
     }
 
     fn get_max_duty(&self) -> Self::Duty {
-        self.inner.get_max_compare_value() as u16 + 1
+        if self.inner.get_counting_mode().is_center_aligned() {
+            self.inner.get_max_compare_value() as u16
+        } else {
+            self.inner.get_max_compare_value() as u16 + 1
+        }
     }
 
     fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index ec8b1ddf1..dda33e7f1 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -6,14 +6,12 @@ use core::pin::Pin;
 use core::task::{Context, Poll};
 
 use super::low_level::{CountingMode, FilterValue, InputCaptureMode, InputTISelection, Timer};
-use super::{
-    CaptureCompareInterruptHandler, Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin,
-    GeneralInstance4Channel,
-};
+use super::{CaptureCompareInterruptHandler, Channel, GeneralInstance4Channel, TimerPin};
 pub use super::{Ch1, Ch2, Ch3, Ch4};
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::time::Hertz;
+use crate::timer::TimerChannel;
 use crate::Peri;
 
 /// Capture pin wrapper.
@@ -23,27 +21,17 @@ pub struct CapturePin<'d, T, C> {
     _pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
-
-macro_rules! channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: GeneralInstance4Channel> CapturePin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " capture pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, pull: Pull) -> Self {
-                pin.set_as_af(pin.af_num(), AfType::input(pull));
-                CapturePin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+impl<'d, T: GeneralInstance4Channel, C: TimerChannel> CapturePin<'d, T, C> {
+    /// Create a new capture pin instance.
+    pub fn new(pin: Peri<'d, impl TimerPin<T, C>>, pull: Pull) -> Self {
+        pin.set_as_af(pin.af_num(), AfType::input(pull));
+        CapturePin {
+            _pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
+    }
 }
 
-channel_impl!(new_ch1, Ch1, Channel1Pin);
-channel_impl!(new_ch2, Ch2, Channel2Pin);
-channel_impl!(new_ch3, Ch3, Channel3Pin);
-channel_impl!(new_ch4, Ch4, Channel4Pin);
-
 /// Input capture driver.
 pub struct InputCapture<'d, T: GeneralInstance4Channel> {
     inner: Timer<'d, T>,
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index b29382fc8..7062f5f4c 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -51,6 +51,80 @@ pub enum Ch3 {}
 /// Channel 4 marker type.
 pub enum Ch4 {}
 
+/// Timer channel trait.
+#[allow(private_bounds)]
+pub trait TimerChannel: SealedTimerChannel {
+    /// The runtime channel.
+    const CHANNEL: Channel;
+}
+
+trait SealedTimerChannel {}
+
+impl TimerChannel for Ch1 {
+    const CHANNEL: Channel = Channel::Ch1;
+}
+
+impl TimerChannel for Ch2 {
+    const CHANNEL: Channel = Channel::Ch2;
+}
+
+impl TimerChannel for Ch3 {
+    const CHANNEL: Channel = Channel::Ch3;
+}
+
+impl TimerChannel for Ch4 {
+    const CHANNEL: Channel = Channel::Ch4;
+}
+
+impl SealedTimerChannel for Ch1 {}
+impl SealedTimerChannel for Ch2 {}
+impl SealedTimerChannel for Ch3 {}
+impl SealedTimerChannel for Ch4 {}
+
+/// Timer break input.
+#[derive(Clone, Copy)]
+pub enum BkIn {
+    /// Break input 1.
+    BkIn1,
+    /// Break input 2.
+    BkIn2,
+}
+
+impl BkIn {
+    /// Get the channel index (0..3)
+    pub fn index(&self) -> usize {
+        match self {
+            BkIn::BkIn1 => 0,
+            BkIn::BkIn2 => 1,
+        }
+    }
+}
+
+/// Break input 1 marker type.
+pub enum BkIn1 {}
+/// Break input 2 marker type.
+pub enum BkIn2 {}
+
+/// Timer channel trait.
+#[allow(private_bounds)]
+pub trait BreakInput: SealedBreakInput {
+    /// The runtim timer channel.
+    const INPUT: BkIn;
+}
+
+trait SealedBreakInput {}
+
+impl BreakInput for BkIn1 {
+    const INPUT: BkIn = BkIn::BkIn1;
+}
+
+impl BreakInput for BkIn2 {
+    const INPUT: BkIn = BkIn::BkIn2;
+}
+
+impl SealedBreakInput for BkIn1 {}
+impl SealedBreakInput for BkIn2 {}
+
 /// Amount of bits of a timer.
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -149,33 +223,20 @@ pub trait AdvancedInstance2Channel: BasicInstance + GeneralInstance2Channel + Ad
 /// Advanced 16-bit timer with 4 channels instance.
 pub trait AdvancedInstance4Channel: AdvancedInstance2Channel + GeneralInstance4Channel {}
 
-pin_trait!(Channel1Pin, GeneralInstance4Channel);
-pin_trait!(Channel2Pin, GeneralInstance4Channel);
-pin_trait!(Channel3Pin, GeneralInstance4Channel);
-pin_trait!(Channel4Pin, GeneralInstance4Channel);
+pin_trait!(TimerPin, GeneralInstance4Channel, TimerChannel);
 pin_trait!(ExternalTriggerPin, GeneralInstance4Channel);
 
-pin_trait!(Channel1ComplementaryPin, AdvancedInstance4Channel);
-pin_trait!(Channel2ComplementaryPin, AdvancedInstance4Channel);
-pin_trait!(Channel3ComplementaryPin, AdvancedInstance4Channel);
-pin_trait!(Channel4ComplementaryPin, AdvancedInstance4Channel);
-
-pin_trait!(BreakInputPin, AdvancedInstance4Channel);
-pin_trait!(BreakInput2Pin, AdvancedInstance4Channel);
+pin_trait!(TimerComplementaryPin, AdvancedInstance4Channel, TimerChannel);
 
-pin_trait!(BreakInputComparator1Pin, AdvancedInstance4Channel);
-pin_trait!(BreakInputComparator2Pin, AdvancedInstance4Channel);
+pin_trait!(BreakInputPin, AdvancedInstance4Channel, BreakInput);
 
-pin_trait!(BreakInput2Comparator1Pin, AdvancedInstance4Channel);
-pin_trait!(BreakInput2Comparator2Pin, AdvancedInstance4Channel);
+pin_trait!(BreakInputComparator1Pin, AdvancedInstance4Channel, BreakInput);
+pin_trait!(BreakInputComparator2Pin, AdvancedInstance4Channel, BreakInput);
 
 // Update Event trigger DMA for every timer
 dma_trait!(UpDma, BasicInstance);
 
-dma_trait!(Ch1Dma, GeneralInstance4Channel);
-dma_trait!(Ch2Dma, GeneralInstance4Channel);
-dma_trait!(Ch3Dma, GeneralInstance4Channel);
-dma_trait!(Ch4Dma, GeneralInstance4Channel);
+dma_trait!(Dma, GeneralInstance4Channel, TimerChannel);
 
 #[allow(unused)]
 macro_rules! impl_core_timer {
diff --git a/embassy-stm32/src/timer/one_pulse.rs b/embassy-stm32/src/timer/one_pulse.rs
index 933165ef9..498d9c082 100644
--- a/embassy-stm32/src/timer/one_pulse.rs
+++ b/embassy-stm32/src/timer/one_pulse.rs
@@ -7,11 +7,9 @@ use core::pin::Pin;
 use core::task::{Context, Poll};
 
 use super::low_level::{
-    CountingMode, FilterValue, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource,
-};
-use super::{
-    CaptureCompareInterruptHandler, Channel, Channel1Pin, Channel2Pin, ExternalTriggerPin, GeneralInstance4Channel,
+    CountingMode, FilterValue, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource as Ts,
 };
+use super::{CaptureCompareInterruptHandler, Channel, ExternalTriggerPin, GeneralInstance4Channel, TimerPin};
 pub use super::{Ch1, Ch2};
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
@@ -48,24 +46,78 @@ pub struct TriggerPin<'d, T, C> {
     phantom: PhantomData<(T, C)>,
 }
 
-macro_rules! channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: GeneralInstance4Channel> TriggerPin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " trigger pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, pull: Pull) -> Self {
-                pin.set_as_af(pin.af_num(), AfType::input(pull));
-                TriggerPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
-        }
-    };
+trait SealedTriggerSource {}
+
+/// Marker trait for a trigger source.
+#[expect(private_bounds)]
+pub trait TriggerSource: SealedTriggerSource {}
+
+impl TriggerSource for Ch1 {}
+impl TriggerSource for Ch2 {}
+impl TriggerSource for Ext {}
+
+impl SealedTriggerSource for Ch1 {}
+impl SealedTriggerSource for Ch2 {}
+impl SealedTriggerSource for Ext {}
+
+trait SealedTimerTriggerPin<T, S>: crate::gpio::Pin {}
+
+/// Marker trait for a trigger pin.
+#[expect(private_bounds)]
+// TODO: find better naming scheme than prefixing all pin traits with "Timer".
+// The trait name cannot conflict with the corresponding type's name.
+// Applies to other timer submodules as well.
+pub trait TimerTriggerPin<T, S>: SealedTimerTriggerPin<T, S> {
+    /// Get the AF number needed to use this pin as a trigger source.
+    fn af_num(&self) -> u8;
+}
+
+impl<T, P, C> TimerTriggerPin<T, C> for P
+where
+    T: GeneralInstance4Channel,
+    P: TimerPin<T, C>,
+    C: super::TimerChannel + TriggerSource,
+{
+    fn af_num(&self) -> u8 {
+        TimerPin::af_num(self)
+    }
+}
+
+impl<T, P> TimerTriggerPin<T, Ext> for P
+where
+    T: GeneralInstance4Channel,
+    P: ExternalTriggerPin<T>,
+{
+    fn af_num(&self) -> u8 {
+        ExternalTriggerPin::af_num(self)
+    }
+}
+
+impl<T, P, C> SealedTimerTriggerPin<T, C> for P
+where
+    T: GeneralInstance4Channel,
+    P: TimerPin<T, C>,
+    C: super::TimerChannel + TriggerSource,
+{
 }
 
-channel_impl!(new_ch1, Ch1, Channel1Pin);
-channel_impl!(new_ch2, Ch2, Channel2Pin);
-channel_impl!(new_ext, Ext, ExternalTriggerPin);
+impl<T, P> SealedTimerTriggerPin<T, Ext> for P
+where
+    T: GeneralInstance4Channel,
+    P: ExternalTriggerPin<T>,
+{
+}
+
+impl<'d, T: GeneralInstance4Channel, C: TriggerSource> TriggerPin<'d, T, C> {
+    /// "Create a new Ch1 trigger pin instance.
+    pub fn new(pin: Peri<'d, impl TimerTriggerPin<T, C>>, pull: Pull) -> Self {
+        pin.set_as_af(pin.af_num(), AfType::input(pull));
+        TriggerPin {
+            _pin: pin.into(),
+            phantom: PhantomData,
+        }
+    }
+}
 
 /// One pulse driver.
 ///
@@ -89,7 +141,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     ) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
-        this.inner.set_trigger_source(TriggerSource::TI1F_ED);
+        this.inner.set_trigger_source(Ts::TI1F_ED);
         this.inner
             .set_input_ti_selection(Channel::Ch1, InputTISelection::Normal);
         this.inner
@@ -114,7 +166,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     ) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
-        this.inner.set_trigger_source(TriggerSource::TI1FP1);
+        this.inner.set_trigger_source(Ts::TI1FP1);
         this.inner
             .set_input_ti_selection(Channel::Ch1, InputTISelection::Normal);
         this.inner
@@ -131,7 +183,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     /// as an output.
     pub fn new_ch2(
         tim: Peri<'d, T>,
-        _pin: TriggerPin<'d, T, Ch1>,
+        _pin: TriggerPin<'d, T, Ch2>,
         _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
         freq: Hertz,
         pulse_end: u32,
@@ -140,7 +192,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     ) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
-        this.inner.set_trigger_source(TriggerSource::TI2FP2);
+        this.inner.set_trigger_source(Ts::TI2FP2);
         this.inner
             .set_input_ti_selection(Channel::Ch2, InputTISelection::Normal);
         this.inner
@@ -172,7 +224,7 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
             // No filtering
             r.set_etf(FilterValue::NO_FILTER);
         });
-        this.inner.set_trigger_source(TriggerSource::ETRF);
+        this.inner.set_trigger_source(Ts::ETRF);
         this.new_inner(freq, pulse_end, counting_mode);
 
         this
diff --git a/embassy-stm32/src/timer/pwm_input.rs b/embassy-stm32/src/timer/pwm_input.rs
index 98b798634..1e55f2919 100644
--- a/embassy-stm32/src/timer/pwm_input.rs
+++ b/embassy-stm32/src/timer/pwm_input.rs
@@ -1,12 +1,16 @@
 //! PWM Input driver.
 
 use super::low_level::{CountingMode, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource};
-use super::{Channel, Channel1Pin, Channel2Pin, GeneralInstance4Channel};
+use super::{Ch1, Ch2, Channel, GeneralInstance4Channel, TimerPin};
 use crate::gpio::{AfType, Pull};
 use crate::time::Hertz;
 use crate::Peri;
 
 /// PWM Input driver.
+///
+/// Only works with CH1 or CH2
+/// Note: Not all timer peripherals are supported
+/// Double check your chips reference manual
 pub struct PwmInput<'d, T: GeneralInstance4Channel> {
     channel: Channel,
     inner: Timer<'d, T>,
@@ -14,14 +18,14 @@ pub struct PwmInput<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
     /// Create a new PWM input driver.
-    pub fn new(tim: Peri<'d, T>, pin: Peri<'d, impl Channel1Pin<T>>, pull: Pull, freq: Hertz) -> Self {
+    pub fn new_ch1(tim: Peri<'d, T>, pin: Peri<'d, impl TimerPin<T, Ch1>>, pull: Pull, freq: Hertz) -> Self {
         pin.set_as_af(pin.af_num(), AfType::input(pull));
 
         Self::new_inner(tim, freq, Channel::Ch1, Channel::Ch2)
     }
 
     /// Create a new PWM input driver.
-    pub fn new_alt(tim: Peri<'d, T>, pin: Peri<'d, impl Channel2Pin<T>>, pull: Pull, freq: Hertz) -> Self {
+    pub fn new_ch2(tim: Peri<'d, T>, pin: Peri<'d, impl TimerPin<T, Ch2>>, pull: Pull, freq: Hertz) -> Self {
         pin.set_as_af(pin.af_num(), AfType::input(pull));
 
         Self::new_inner(tim, freq, Channel::Ch2, Channel::Ch1)
@@ -37,6 +41,7 @@ impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
 
         // Configuration steps from ST RM0390 (STM32F446) chapter 17.3.6
         // or ST RM0008 (STM32F103) chapter 15.3.6 Input capture mode
+        // or ST RM0440 (STM32G4) chapter 30.4.8 PWM input mode
         inner.set_input_ti_selection(ch1, InputTISelection::Normal);
         inner.set_input_capture_mode(ch1, InputCaptureMode::Rising);
 
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index f3c81667c..eabe1b22a 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -6,8 +6,9 @@ use stm32_metapac::timer::vals;
 
 use super::low_level::Timer;
 pub use super::{Ch1, Ch2};
-use super::{Channel1Pin, Channel2Pin, GeneralInstance4Channel};
+use super::{GeneralInstance4Channel, TimerPin};
 use crate::gpio::{AfType, AnyPin, Pull};
+use crate::timer::TimerChannel;
 use crate::Peri;
 
 /// Counting direction
@@ -24,26 +25,31 @@ pub struct QeiPin<'d, T, Channel> {
     phantom: PhantomData<(T, Channel)>,
 }
 
-macro_rules! channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: GeneralInstance4Channel> QeiPin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " QEI pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(pin.af_num(), AfType::input(Pull::None));
-                });
-                QeiPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+impl<'d, T: GeneralInstance4Channel, C: QeiChannel> QeiPin<'d, T, C> {
+    /// Create a new  QEI pin instance.
+    pub fn new(pin: Peri<'d, impl TimerPin<T, C>>) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            pin.set_as_af(pin.af_num(), AfType::input(Pull::None));
+        });
+        QeiPin {
+            _pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
+    }
 }
 
-channel_impl!(new_ch1, Ch1, Channel1Pin);
-channel_impl!(new_ch2, Ch2, Channel2Pin);
+trait SealedQeiChannel: TimerChannel {}
+
+/// Marker trait for a timer channel eligible for use with QEI.
+#[expect(private_bounds)]
+pub trait QeiChannel: SealedQeiChannel {}
+
+impl QeiChannel for Ch1 {}
+impl QeiChannel for Ch2 {}
+
+impl SealedQeiChannel for Ch1 {}
+impl SealedQeiChannel for Ch2 {}
 
 /// Quadrature decoder driver.
 pub struct Qei<'d, T: GeneralInstance4Channel> {
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index f7f433154..c04b1ab97 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -4,22 +4,13 @@ use core::marker::PhantomData;
 use core::mem::ManuallyDrop;
 
 use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer};
-use super::{Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin, GeneralInstance4Channel, TimerBits};
+use super::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance4Channel, TimerBits, TimerChannel, TimerPin};
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::time::Hertz;
 use crate::Peri;
 
-/// Channel 1 marker type.
-pub enum Ch1 {}
-/// Channel 2 marker type.
-pub enum Ch2 {}
-/// Channel 3 marker type.
-pub enum Ch3 {}
-/// Channel 4 marker type.
-pub enum Ch4 {}
-
 /// PWM pin wrapper.
 ///
 /// This wraps a pin to make it usable with PWM.
@@ -43,46 +34,37 @@ pub struct PwmPinConfig {
     pub pull: Pull,
 }
 
-macro_rules! channel_impl {
-    ($new_chx:ident, $new_chx_with_config:ident, $channel:ident, $pin_trait:ident) => {
-        impl<'d, T: GeneralInstance4Channel> PwmPin<'d, T, $channel> {
-            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
-            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, output_type: OutputType) -> Self {
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(pin.af_num(), AfType::output(output_type, Speed::VeryHigh));
-                });
-                PwmPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
-
-            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance with config.")]
-            pub fn $new_chx_with_config(pin: Peri<'d, impl $pin_trait<T>>, pin_config: PwmPinConfig) -> Self {
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        #[cfg(gpio_v1)]
-                        AfType::output(pin_config.output_type, pin_config.speed),
-                        #[cfg(gpio_v2)]
-                        AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull),
-                    );
-                });
-                PwmPin {
-                    _pin: pin.into(),
-                    phantom: PhantomData,
-                }
-            }
+impl<'d, T: GeneralInstance4Channel, C: TimerChannel> PwmPin<'d, T, C> {
+    /// Create a new PWM pin instance.
+    pub fn new(pin: Peri<'d, impl TimerPin<T, C>>, output_type: OutputType) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            pin.set_as_af(pin.af_num(), AfType::output(output_type, Speed::VeryHigh));
+        });
+        PwmPin {
+            _pin: pin.into(),
+            phantom: PhantomData,
         }
-    };
-}
+    }
 
-channel_impl!(new_ch1, new_ch1_with_config, Ch1, Channel1Pin);
-channel_impl!(new_ch2, new_ch2_with_config, Ch2, Channel2Pin);
-channel_impl!(new_ch3, new_ch3_with_config, Ch3, Channel3Pin);
-channel_impl!(new_ch4, new_ch4_with_config, Ch4, Channel4Pin);
+    /// Create a new PWM pin instance with config.
+    pub fn new_with_config(pin: Peri<'d, impl TimerPin<T, C>>, pin_config: PwmPinConfig) -> Self {
+        critical_section::with(|_| {
+            pin.set_low();
+            pin.set_as_af(
+                pin.af_num(),
+                #[cfg(gpio_v1)]
+                AfType::output(pin_config.output_type, pin_config.speed),
+                #[cfg(gpio_v2)]
+                AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull),
+            );
+        });
+        PwmPin {
+            _pin: pin.into(),
+            phantom: PhantomData,
+        }
+    }
+}
 
 /// A single channel of a pwm, obtained from [`SimplePwm::split`],
 /// [`SimplePwm::channel`], [`SimplePwm::ch1`], etc.
@@ -466,107 +448,98 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     }
 }
 
-macro_rules! impl_waveform_chx {
-    ($fn_name:ident, $dma_ch:ident, $cc_ch:ident) => {
-        impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
-            /// Generate a sequence of PWM waveform
-            pub async fn $fn_name(&mut self, dma: Peri<'_, impl super::$dma_ch<T>>, duty: &[u16]) {
-                use crate::pac::timer::vals::Ccds;
+impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
+    /// Generate a sequence of PWM waveform
+    pub async fn waveform<C: TimerChannel>(&mut self, dma: Peri<'_, impl super::Dma<T, C>>, duty: &[u16]) {
+        use crate::pac::timer::vals::Ccds;
+
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
 
-                #[allow(clippy::let_unit_value)] // eg. stm32f334
-                let req = dma.request();
+        let cc_channel = C::CHANNEL;
 
-                let cc_channel = Channel::$cc_ch;
+        let original_duty_state = self.channel(cc_channel).current_duty_cycle();
+        let original_enable_state = self.channel(cc_channel).is_enabled();
+        let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ON_UPDATE;
+        let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel);
 
-                let original_duty_state = self.channel(cc_channel).current_duty_cycle();
-                let original_enable_state = self.channel(cc_channel).is_enabled();
-                let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ON_UPDATE;
-                let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel);
+        // redirect CC DMA request onto Update Event
+        if !original_cc_dma_on_update {
+            self.inner.set_cc_dma_selection(Ccds::ON_UPDATE)
+        }
 
-                // redirect CC DMA request onto Update Event
-                if !original_cc_dma_on_update {
-                    self.inner.set_cc_dma_selection(Ccds::ON_UPDATE)
-                }
+        if !original_cc_dma_enabled {
+            self.inner.set_cc_dma_enable_state(cc_channel, true);
+        }
 
-                if !original_cc_dma_enabled {
-                    self.inner.set_cc_dma_enable_state(cc_channel, true);
-                }
+        if !original_enable_state {
+            self.channel(cc_channel).enable();
+        }
 
-                if !original_enable_state {
-                    self.channel(cc_channel).enable();
-                }
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
 
-                unsafe {
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr8,
+                ..Default::default()
+            };
+
+            match self.inner.bits() {
+                TimerBits::Bits16 => {
+                    Transfer::new_write(
+                        dma,
+                        req,
+                        duty,
+                        self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16,
+                        dma_transfer_option,
+                    )
+                    .await
+                }
+                #[cfg(not(any(stm32l0)))]
+                TimerBits::Bits32 => {
                     #[cfg(not(any(bdma, gpdma)))]
-                    use crate::dma::{Burst, FifoThreshold};
-                    use crate::dma::{Transfer, TransferOptions};
-
-                    let dma_transfer_option = TransferOptions {
-                        #[cfg(not(any(bdma, gpdma)))]
-                        fifo_threshold: Some(FifoThreshold::Full),
-                        #[cfg(not(any(bdma, gpdma)))]
-                        mburst: Burst::Incr8,
-                        ..Default::default()
-                    };
-
-                    match self.inner.bits() {
-                        TimerBits::Bits16 => {
-                            Transfer::new_write(
-                                dma,
-                                req,
-                                duty,
-                                self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16,
-                                dma_transfer_option,
-                            )
-                            .await
-                        }
-                        #[cfg(not(any(stm32l0)))]
-                        TimerBits::Bits32 => {
-                            #[cfg(not(any(bdma, gpdma)))]
-                            panic!("unsupported timer bits");
-
-                            #[cfg(any(bdma, gpdma))]
-                            Transfer::new_write(
-                                dma,
-                                req,
-                                duty,
-                                self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32,
-                                dma_transfer_option,
-                            )
-                            .await
-                        }
-                    };
-                };
-
-                // restore output compare state
-                if !original_enable_state {
-                    self.channel(cc_channel).disable();
+                    panic!("unsupported timer bits");
+
+                    #[cfg(any(bdma, gpdma))]
+                    Transfer::new_write(
+                        dma,
+                        req,
+                        duty,
+                        self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32,
+                        dma_transfer_option,
+                    )
+                    .await
                 }
+            };
+        };
+
+        // restore output compare state
+        if !original_enable_state {
+            self.channel(cc_channel).disable();
+        }
 
-                self.channel(cc_channel).set_duty_cycle(original_duty_state);
+        self.channel(cc_channel).set_duty_cycle(original_duty_state);
 
-                // Since DMA is closed before timer Capture Compare Event trigger DMA is turn off,
-                // this can almost always trigger a DMA FIFO error.
-                //
-                // optional TODO:
-                // clean FEIF after disable UDE
-                if !original_cc_dma_enabled {
-                    self.inner.set_cc_dma_enable_state(cc_channel, false);
-                }
+        // Since DMA is closed before timer Capture Compare Event trigger DMA is turn off,
+        // this can almost always trigger a DMA FIFO error.
+        //
+        // optional TODO:
+        // clean FEIF after disable UDE
+        if !original_cc_dma_enabled {
+            self.inner.set_cc_dma_enable_state(cc_channel, false);
+        }
 
-                if !original_cc_dma_on_update {
-                    self.inner.set_cc_dma_selection(Ccds::ON_COMPARE)
-                }
-            }
+        if !original_cc_dma_on_update {
+            self.inner.set_cc_dma_selection(Ccds::ON_COMPARE)
         }
-    };
+    }
 }
 
-impl_waveform_chx!(waveform_ch1, Ch1Dma, Ch1);
-impl_waveform_chx!(waveform_ch2, Ch2Dma, Ch2);
-impl_waveform_chx!(waveform_ch3, Ch3Dma, Ch3);
-impl_waveform_chx!(waveform_ch4, Ch4Dma, Ch4);
-
 impl<'d, T: GeneralInstance4Channel> embedded_hal_1::pwm::ErrorType for SimplePwmChannel<'d, T> {
     type Error = core::convert::Infallible;
 }
diff --git a/embassy-stm32/src/tsc/acquisition_banks.rs b/embassy-stm32/src/tsc/acquisition_banks.rs
index 6791ef6c1..7d6442b48 100644
--- a/embassy-stm32/src/tsc/acquisition_banks.rs
+++ b/embassy-stm32/src/tsc/acquisition_banks.rs
@@ -32,7 +32,7 @@ impl AcquisitionBankPins {
     /// Returns an iterator over the pins in this acquisition bank.
     ///
     /// This method allows for easy traversal of all configured pins in the bank.
-    pub fn iter(&self) -> AcquisitionBankPinsIterator {
+    pub fn iter(&self) -> AcquisitionBankPinsIterator<'_> {
         AcquisitionBankPinsIterator(AcquisitionBankIterator::new(self))
     }
 }
@@ -90,7 +90,7 @@ impl<'a> Iterator for AcquisitionBankPinsIterator<'a> {
 
 impl AcquisitionBankPins {
     /// Returns an iterator over the available pins in the bank
-    pub fn pins_iterator(&self) -> AcquisitionBankPinsIterator {
+    pub fn pins_iterator(&self) -> AcquisitionBankPinsIterator<'_> {
         AcquisitionBankPinsIterator(AcquisitionBankIterator::new(self))
     }
 }
@@ -107,7 +107,7 @@ pub struct AcquisitionBank {
 
 impl AcquisitionBank {
     /// Returns an iterator over the available pins in the bank.
-    pub fn pins_iterator(&self) -> AcquisitionBankPinsIterator {
+    pub fn pins_iterator(&self) -> AcquisitionBankPinsIterator<'_> {
         self.pins.pins_iterator()
     }
 
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 73ab46404..729440c46 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -87,6 +87,8 @@ unsafe fn on_interrupt(r: Regs, state: &'static State) {
 
         r.cr1().modify(|w| {
             w.set_tcie(false);
+            // Reenable receiver for half-duplex if it was disabled
+            w.set_re(true);
         });
 
         state.tx_done.store(true, Ordering::Release);
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index b3f8bc00c..5bece6d66 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -550,6 +550,20 @@ impl<'d, M: Mode> UartTx<'d, M> {
         reconfigure(self.info, self.kernel_clock, config)
     }
 
+    /// Write a single u8 if there is tx empty, otherwise return WouldBlock
+    pub(crate) fn nb_write(&mut self, byte: u8) -> Result<(), nb::Error<Error>> {
+        let r = self.info.regs;
+        let sr = sr(r).read();
+        if sr.txe() {
+            unsafe {
+                tdr(r).write_volatile(byte);
+            }
+            Ok(())
+        } else {
+            Err(nb::Error::WouldBlock)
+        }
+    }
+
     /// Perform a blocking UART write
     pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
         let r = self.info.regs;
@@ -637,7 +651,7 @@ pub fn send_break(regs: &Regs) {
 /// In case of readback, keep Receiver enabled
 fn half_duplex_set_rx_tx_before_write(r: &Regs, enable_readback: bool) {
     let mut cr1 = r.cr1().read();
-    if r.cr3().read().hdsel() && !cr1.te() {
+    if r.cr3().read().hdsel() {
         cr1.set_te(true);
         cr1.set_re(enable_readback);
         r.cr1().write_value(cr1);
@@ -1864,7 +1878,7 @@ impl<'d, M: Mode> embedded_hal_nb::serial::Read for UartRx<'d, M> {
 
 impl<'d, M: Mode> embedded_hal_nb::serial::Write for UartTx<'d, M> {
     fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
-        self.blocking_write(&[char]).map_err(nb::Error::Other)
+        self.nb_write(char)
     }
 
     fn flush(&mut self) -> nb::Result<(), Self::Error> {
diff --git a/embassy-stm32/src/usb/mod.rs b/embassy-stm32/src/usb/mod.rs
index ae5963420..692897b59 100644
--- a/embassy-stm32/src/usb/mod.rs
+++ b/embassy-stm32/src/usb/mod.rs
@@ -15,7 +15,7 @@ fn common_init<T: Instance>() {
     let freq = T::frequency();
 
     // On the H7RS, the USBPHYC embeds a PLL accepting one of the input frequencies listed below and providing 48MHz to OTG_FS and 60MHz to OTG_HS internally
-    #[cfg(any(stm32h7rs, all(stm32u5, peri_usb_otg_hs)))]
+    #[cfg(any(stm32h7rs, all(stm32u5, peri_usb_otg_hs), all(stm32wba, peri_usb_otg_hs)))]
     if ![16_000_000, 19_200_000, 20_000_000, 24_000_000, 26_000_000, 32_000_000].contains(&freq.0) {
         panic!(
             "USB clock should be one of 16, 19.2, 20, 24, 26, 32Mhz but is {} Hz. Please double-check your RCC settings.",
@@ -25,7 +25,7 @@ fn common_init<T: Instance>() {
     // Check frequency is within the 0.25% tolerance allowed by the spec.
     // Clock might not be exact 48Mhz due to rounding errors in PLL calculation, or if the user
     // has tight clock restrictions due to something else (like audio).
-    #[cfg(not(any(stm32h7rs, all(stm32u5, peri_usb_otg_hs))))]
+    #[cfg(not(any(stm32h7rs, all(stm32u5, peri_usb_otg_hs), all(stm32wba, peri_usb_otg_hs))))]
     if freq.0.abs_diff(48_000_000) > 120_000 {
         panic!(
             "USB clock should be 48Mhz but is {} Hz. Please double-check your RCC settings.",
@@ -102,6 +102,30 @@ fn common_init<T: Instance>() {
         }
     }
 
+    #[cfg(stm32wba)]
+    {
+        // Enable USB power
+        critical_section::with(|_| {
+            crate::pac::PWR.svmcr().modify(|w| {
+                w.set_usv(crate::pac::pwr::vals::Usv::B_0X1);
+                // w.set_uvmen(true);
+            })
+        });
+
+        // Wait for USB power to stabilize
+        while !crate::pac::PWR.vosr().read().vdd11usbrdy() {}
+
+        // Now set up transceiver power if it's a OTG-HS
+        #[cfg(peri_usb_otg_hs)]
+        {
+            crate::pac::PWR.vosr().modify(|w| {
+                w.set_usbpwren(true);
+                w.set_usbboosten(true);
+            });
+            while !crate::pac::PWR.vosr().read().usbboostrdy() {}
+        }
+    }
+
     T::Interrupt::unpend();
     unsafe { T::Interrupt::enable() };
 
diff --git a/embassy-stm32/src/usb/otg.rs b/embassy-stm32/src/usb/otg.rs
index 590d1a427..b074cfa1b 100644
--- a/embassy-stm32/src/usb/otg.rs
+++ b/embassy-stm32/src/usb/otg.rs
@@ -105,7 +105,7 @@ impl<'d, T: Instance> Driver<'d, T> {
         config: Config,
     ) -> Self {
         // For STM32U5 High speed pins need to be left in analog mode
-        #[cfg(not(all(stm32u5, peri_usb_otg_hs)))]
+        #[cfg(not(any(all(stm32u5, peri_usb_otg_hs), all(stm32wba, peri_usb_otg_hs))))]
         {
             _dp.set_as_af(_dp.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
             _dm.set_as_af(_dm.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
@@ -231,19 +231,23 @@ impl<'d, T: Instance> embassy_usb_driver::Driver<'d> for Driver<'d, T> {
     fn alloc_endpoint_in(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointIn, EndpointAllocError> {
-        self.inner.alloc_endpoint_in(ep_type, max_packet_size, interval_ms)
+        self.inner
+            .alloc_endpoint_in(ep_type, ep_addr, max_packet_size, interval_ms)
     }
 
     fn alloc_endpoint_out(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointOut, EndpointAllocError> {
-        self.inner.alloc_endpoint_out(ep_type, max_packet_size, interval_ms)
+        self.inner
+            .alloc_endpoint_out(ep_type, ep_addr, max_packet_size, interval_ms)
     }
 
     fn start(self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
@@ -323,6 +327,20 @@ impl<'d, T: Instance> Bus<'d, T> {
             });
         }
 
+        #[cfg(all(stm32wba, peri_usb_otg_hs))]
+        {
+            crate::pac::SYSCFG.otghsphycr().modify(|w| {
+                w.set_en(true);
+            });
+
+            critical_section::with(|_| {
+                crate::pac::RCC.ahb2enr().modify(|w| {
+                    w.set_usb_otg_hsen(true);
+                    w.set_otghsphyen(true);
+                });
+            });
+        }
+
         let r = T::regs();
         let core_id = r.cid().read().0;
         trace!("Core id {:08x}", core_id);
@@ -464,6 +482,7 @@ foreach_interrupt!(
                     stm32f7,
                     stm32l4,
                     stm32u5,
+                    stm32wba,
                 ))] {
                     const FIFO_DEPTH_WORDS: u16 = 320;
                     const ENDPOINT_COUNT: usize = 6;
@@ -473,7 +492,7 @@ foreach_interrupt!(
                 } else if #[cfg(any(stm32h7, stm32h7rs))] {
                     const FIFO_DEPTH_WORDS: u16 = 1024;
                     const ENDPOINT_COUNT: usize = 9;
-                } else if #[cfg(stm32u5)] {
+                } else if #[cfg(any(stm32wba, stm32u5))] {
                     const FIFO_DEPTH_WORDS: u16 = 320;
                     const ENDPOINT_COUNT: usize = 6;
                 } else {
@@ -523,7 +542,7 @@ foreach_interrupt!(
                 ))] {
                     const FIFO_DEPTH_WORDS: u16 = 1024;
                     const ENDPOINT_COUNT: usize = 9;
-                } else if #[cfg(stm32u5)] {
+                } else if #[cfg(any(stm32u5, stm32wba))] {
                     const FIFO_DEPTH_WORDS: u16 = 1024;
                     const ENDPOINT_COUNT: usize = 9;
                 } else {
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index 3e8e74a1f..92c1601cc 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -359,9 +359,38 @@ impl<'d, T: Instance> Driver<'d, T> {
         addr
     }
 
+    fn is_endpoint_available<D: Dir>(&self, index: usize, ep_type: EndpointType) -> bool {
+        if index == 0 && ep_type != EndpointType::Control {
+            return false; // EP0 is reserved for control
+        }
+
+        let ep = match self.alloc.get(index) {
+            Some(ep) => ep,
+            None => return false,
+        };
+
+        let used = ep.used_out || ep.used_in;
+
+        if used && ep.ep_type == EndpointType::Isochronous {
+            // Isochronous endpoints are always double-buffered.
+            // Their corresponding endpoint/channel registers are forced to be unidirectional.
+            // Do not reuse this index.
+            // FIXME: Bulk endpoints can be double buffered, but are not in the current implementation.
+            return false;
+        }
+
+        let used_dir = match D::dir() {
+            Direction::Out => ep.used_out,
+            Direction::In => ep.used_in,
+        };
+
+        !used || (ep.ep_type == ep_type && !used_dir)
+    }
+
     fn alloc_endpoint<D: Dir>(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Endpoint<'d, T, D>, driver::EndpointAllocError> {
@@ -373,28 +402,17 @@ impl<'d, T: Instance> Driver<'d, T> {
             D::dir()
         );
 
-        let index = self.alloc.iter_mut().enumerate().find(|(i, ep)| {
-            if *i == 0 && ep_type != EndpointType::Control {
-                return false; // reserved for control pipe
-            }
-            let used = ep.used_out || ep.used_in;
-            if used && (ep.ep_type == EndpointType::Isochronous) {
-                // Isochronous endpoints are always double-buffered.
-                // Their corresponding endpoint/channel registers are forced to be unidirectional.
-                // Do not reuse this index.
-                // FIXME: Bulk endpoints can be double buffered, but are not in the current implementation.
-                return false;
-            }
-
-            let used_dir = match D::dir() {
-                Direction::Out => ep.used_out,
-                Direction::In => ep.used_in,
-            };
-            !used || (ep.ep_type == ep_type && !used_dir)
-        });
+        let index = if let Some(addr) = ep_addr {
+            // Use the specified endpoint address
+            self.is_endpoint_available::<D>(addr.index(), ep_type)
+                .then_some(addr.index())
+        } else {
+            // Find any available endpoint
+            (0..self.alloc.len()).find(|&i| self.is_endpoint_available::<D>(i, ep_type))
+        };
 
         let (index, ep) = match index {
-            Some(x) => x,
+            Some(i) => (i, &mut self.alloc[i]),
             None => return Err(EndpointAllocError),
         };
 
@@ -479,27 +497,29 @@ impl<'d, T: Instance> driver::Driver<'d> for Driver<'d, T> {
     fn alloc_endpoint_in(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointIn, driver::EndpointAllocError> {
-        self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
+        self.alloc_endpoint(ep_type, ep_addr, max_packet_size, interval_ms)
     }
 
     fn alloc_endpoint_out(
         &mut self,
         ep_type: EndpointType,
+        ep_addr: Option<EndpointAddress>,
         max_packet_size: u16,
         interval_ms: u8,
     ) -> Result<Self::EndpointOut, driver::EndpointAllocError> {
-        self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
+        self.alloc_endpoint(ep_type, ep_addr, max_packet_size, interval_ms)
     }
 
     fn start(mut self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
         let ep_out = self
-            .alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
+            .alloc_endpoint(EndpointType::Control, None, control_max_packet_size, 0)
             .unwrap();
         let ep_in = self
-            .alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
+            .alloc_endpoint(EndpointType::Control, None, control_max_packet_size, 0)
             .unwrap();
         assert_eq!(ep_out.info.addr.index(), 0);
         assert_eq!(ep_in.info.addr.index(), 0);