diff options
| author | Joonas Javanainen <[email protected]> | 2022-04-30 11:41:17 +0300 |
|---|---|---|
| committer | Joonas Javanainen <[email protected]> | 2022-04-30 11:41:17 +0300 |
| commit | e88559c5ca2450bbcfd6fe65e73fe0fe47465680 (patch) | |
| tree | 8dd7f813e8eb542e0af6903440f5319a4206df25 /examples/stm32f2 | |
| parent | 1d5f9b86fb0dbfd1556f2e161d193f4475e2db6e (diff) | |
Use defmt-friendly error handling
Diffstat (limited to 'examples/stm32f2')
| -rw-r--r-- | examples/stm32f2/src/bin/pll.rs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/examples/stm32f2/src/bin/pll.rs b/examples/stm32f2/src/bin/pll.rs index 348a583ab..4bd74f0bd 100644 --- a/examples/stm32f2/src/bin/pll.rs +++ b/examples/stm32f2/src/bin/pll.rs | |||
| @@ -30,13 +30,13 @@ fn config() -> Config { | |||
| 30 | config.rcc.pll_mux = PLLSrc::HSE; | 30 | config.rcc.pll_mux = PLLSrc::HSE; |
| 31 | config.rcc.pll = PLLConfig { | 31 | config.rcc.pll = PLLConfig { |
| 32 | // 8 MHz clock source / 8 = 1 MHz PLL input | 32 | // 8 MHz clock source / 8 = 1 MHz PLL input |
| 33 | pre_div: PLLPreDiv::try_from(8).unwrap(), | 33 | pre_div: unwrap!(PLLPreDiv::try_from(8)), |
| 34 | // 1 MHz PLL input * 240 = 240 MHz PLL VCO | 34 | // 1 MHz PLL input * 240 = 240 MHz PLL VCO |
| 35 | mul: PLLMul::try_from(240).unwrap(), | 35 | mul: unwrap!(PLLMul::try_from(240)), |
| 36 | // 240 MHz PLL VCO / 2 = 120 MHz main PLL output | 36 | // 240 MHz PLL VCO / 2 = 120 MHz main PLL output |
| 37 | main_div: PLLMainDiv::Div2, | 37 | main_div: PLLMainDiv::Div2, |
| 38 | // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output | 38 | // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output |
| 39 | pll48_div: PLL48Div::try_from(5).unwrap(), | 39 | pll48_div: unwrap!(PLL48Div::try_from(5)), |
| 40 | }; | 40 | }; |
| 41 | // System clock comes from PLL (= the 120 MHz main PLL output) | 41 | // System clock comes from PLL (= the 120 MHz main PLL output) |
| 42 | config.rcc.mux = ClockSrc::PLL; | 42 | config.rcc.mux = ClockSrc::PLL; |