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authorDario Nieuwenhuis <[email protected]>2023-11-13 01:53:27 +0100
committerDario Nieuwenhuis <[email protected]>2023-11-13 01:56:50 +0100
commit2376b3bdfa573027c1ee4d66f8fdd6ca422a0fdd (patch)
tree7f5159472bc75c53734dc2559ab9b0579a28af79 /examples/stm32f4/src/bin/sdmmc.rs
parentf00e97a5f14b25d261eafba7cbc63b035c938996 (diff)
stm32/rcc: fix pll enum naming on f4, f7.
Diffstat (limited to 'examples/stm32f4/src/bin/sdmmc.rs')
-rw-r--r--examples/stm32f4/src/bin/sdmmc.rs4
1 files changed, 2 insertions, 2 deletions
diff --git a/examples/stm32f4/src/bin/sdmmc.rs b/examples/stm32f4/src/bin/sdmmc.rs
index 37e42384b..91747b2d5 100644
--- a/examples/stm32f4/src/bin/sdmmc.rs
+++ b/examples/stm32f4/src/bin/sdmmc.rs
@@ -30,8 +30,8 @@ async fn main(_spawner: Spawner) {
30 config.rcc.pll = Some(Pll { 30 config.rcc.pll = Some(Pll {
31 prediv: PllPreDiv::DIV4, 31 prediv: PllPreDiv::DIV4,
32 mul: PllMul::MUL168, 32 mul: PllMul::MUL168,
33 divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. 33 divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
34 divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. 34 divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
35 divr: None, 35 divr: None,
36 }); 36 });
37 config.rcc.ahb_pre = AHBPrescaler::DIV1; 37 config.rcc.ahb_pre = AHBPrescaler::DIV1;