diff options
| author | Dario Nieuwenhuis <[email protected]> | 2023-10-09 02:48:22 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2023-10-09 02:48:22 +0200 |
| commit | 6186fe08070c5f497d72586640db287193b41894 (patch) | |
| tree | aaef02d5344086bde66725a853851546961520fa /examples/stm32h7/src/bin/low_level_timer_api.rs | |
| parent | c4cff0b79bc54634db9d0fa24a24add49b7ec7fe (diff) | |
stm32/rcc: use PLL enums from PAC.
Diffstat (limited to 'examples/stm32h7/src/bin/low_level_timer_api.rs')
| -rw-r--r-- | examples/stm32h7/src/bin/low_level_timer_api.rs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs index a1e955c39..f4fa06909 100644 --- a/examples/stm32h7/src/bin/low_level_timer_api.rs +++ b/examples/stm32h7/src/bin/low_level_timer_api.rs | |||
| @@ -22,10 +22,10 @@ async fn main(_spawner: Spawner) { | |||
| 22 | config.rcc.hsi48 = true; // needed for RNG | 22 | config.rcc.hsi48 = true; // needed for RNG |
| 23 | config.rcc.pll_src = PllSource::Hsi; | 23 | config.rcc.pll_src = PllSource::Hsi; |
| 24 | config.rcc.pll1 = Some(Pll { | 24 | config.rcc.pll1 = Some(Pll { |
| 25 | prediv: 4, | 25 | prediv: PllPreDiv::DIV4, |
| 26 | mul: 50, | 26 | mul: PllMul::MUL50, |
| 27 | divp: Some(2), | 27 | divp: Some(PllDiv::DIV2), |
| 28 | divq: Some(8), // 100 Mhz | 28 | divq: Some(PllDiv::DIV8), // 100mhz |
| 29 | divr: None, | 29 | divr: None, |
| 30 | }); | 30 | }); |
| 31 | config.rcc.sys = Sysclk::Pll1P; // 400 Mhz | 31 | config.rcc.sys = Sysclk::Pll1P; // 400 Mhz |