diff options
| author | Dario Nieuwenhuis <[email protected]> | 2023-10-23 00:28:54 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2023-10-23 00:31:36 +0200 |
| commit | b9e13cb5d1ca3e85a02b2a37b7ee14f73663b1bd (patch) | |
| tree | 1ae33453bcee12a6aaf4cfdd8dc1795187c7cadc /examples/stm32wl/src/bin/random.rs | |
| parent | 46ff2c82aa3193dd1378b142be284aa746045923 (diff) | |
stm32/rcc: merge wl into l4/l5.
Diffstat (limited to 'examples/stm32wl/src/bin/random.rs')
| -rw-r--r-- | examples/stm32wl/src/bin/random.rs | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/examples/stm32wl/src/bin/random.rs b/examples/stm32wl/src/bin/random.rs index 70676c704..2cf7ef9d0 100644 --- a/examples/stm32wl/src/bin/random.rs +++ b/examples/stm32wl/src/bin/random.rs | |||
| @@ -4,9 +4,9 @@ | |||
| 4 | 4 | ||
| 5 | use defmt::*; | 5 | use defmt::*; |
| 6 | use embassy_executor::Spawner; | 6 | use embassy_executor::Spawner; |
| 7 | use embassy_stm32::rcc::{ClockSrc, MSIRange}; | ||
| 8 | use embassy_stm32::rng::{self, Rng}; | 7 | use embassy_stm32::rng::{self, Rng}; |
| 9 | use embassy_stm32::{bind_interrupts, pac, peripherals}; | 8 | use embassy_stm32::time::Hertz; |
| 9 | use embassy_stm32::{bind_interrupts, peripherals}; | ||
| 10 | use {defmt_rtt as _, panic_probe as _}; | 10 | use {defmt_rtt as _, panic_probe as _}; |
| 11 | 11 | ||
| 12 | bind_interrupts!(struct Irqs{ | 12 | bind_interrupts!(struct Irqs{ |
| @@ -16,11 +16,24 @@ bind_interrupts!(struct Irqs{ | |||
| 16 | #[embassy_executor::main] | 16 | #[embassy_executor::main] |
| 17 | async fn main(_spawner: Spawner) { | 17 | async fn main(_spawner: Spawner) { |
| 18 | let mut config = embassy_stm32::Config::default(); | 18 | let mut config = embassy_stm32::Config::default(); |
| 19 | config.rcc.mux = ClockSrc::MSI(MSIRange::RANGE32M); | 19 | { |
| 20 | use embassy_stm32::rcc::*; | ||
| 21 | config.rcc.hse = Some(Hse { | ||
| 22 | freq: Hertz(32_000_000), | ||
| 23 | mode: HseMode::Bypass, | ||
| 24 | }); | ||
| 25 | config.rcc.mux = ClockSrc::PLL1_R; | ||
| 26 | config.rcc.pll = Some(Pll { | ||
| 27 | source: PLLSource::HSE, | ||
| 28 | prediv: PllPreDiv::DIV2, | ||
| 29 | mul: PllMul::MUL6, | ||
| 30 | divp: None, | ||
| 31 | divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG | ||
| 32 | divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2) | ||
| 33 | }); | ||
| 34 | } | ||
| 20 | let p = embassy_stm32::init(config); | 35 | let p = embassy_stm32::init(config); |
| 21 | 36 | ||
| 22 | pac::RCC.ccipr().modify(|w| w.set_rngsel(0b11)); // msi | ||
| 23 | |||
| 24 | info!("Hello World!"); | 37 | info!("Hello World!"); |
| 25 | 38 | ||
| 26 | let mut rng = Rng::new(p.RNG, Irqs); | 39 | let mut rng = Rng::new(p.RNG, Irqs); |
